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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Update csr.sv
Program clean up
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17724f7832
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@ -123,6 +123,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
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logic [P.XLEN-1:0] TVecAlignedM;
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logic InstrValidNotFlushedM;
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logic STimerInt;
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logic MENVCFG_STCE;
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// only valid unflushed instructions can access CSRs
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assign InstrValidNotFlushedM = InstrValidM & ~StallW & ~FlushW;
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@ -213,7 +214,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
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csri #(P) csri(.clk, .reset,
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.CSRMWriteM, .CSRSWriteM, .CSRWriteValM, .CSRAdrM,
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.MExtInt, .SExtInt, .MTimerInt, .STimerInt, .MSwInt,
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.MIDELEG_REGW, .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable);
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.MIDELEG_REGW, .MENVCFG_STCE, .MIP_REGW, .MIE_REGW, .MIP_REGW_writeable);
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csrsr #(P) csrsr(.clk, .reset, .StallW,
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.WriteMSTATUSM, .WriteMSTATUSHM, .WriteSSTATUSM,
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@ -231,7 +232,8 @@ module csr import cvw::*; #(parameter cvw_t P) (
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.MEPC_REGW, .MCOUNTEREN_REGW, .MCOUNTINHIBIT_REGW,
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.MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.MIP_REGW, .MIE_REGW, .WriteMSTATUSM, .WriteMSTATUSHM,
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.IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM);
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.IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM,
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.MENVCFG_STCE);
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if (P.S_SUPPORTED) begin:csrs
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@ -242,7 +244,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
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.CSRWriteValM, .PrivilegeModeW,
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.CSRSReadValM, .STVEC_REGW, .SEPC_REGW,
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.SCOUNTEREN_REGW,
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.SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MTIME_CLINT,
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.SATP_REGW, .MIP_REGW, .MIE_REGW, .MIDELEG_REGW, .MTIME_CLINT, .MENVCFG_STCE,
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.WriteSSTATUSM, .IllegalCSRSAccessM, .STimerInt);
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end else begin
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assign WriteSSTATUSM = 0;
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@ -266,7 +268,7 @@ module csr import cvw::*; #(parameter cvw_t P) (
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assign IllegalCSRUAccessM = 1;
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end
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if (P.ZICOUNTERS_SUPPORTED) begin:counters
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if (P.ZICNTR_SUPPORTED) begin:counters
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csrc #(P) counters(.clk, .reset, .StallE, .StallM, .FlushM,
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.InstrValidNotFlushedM, .LoadStallD, .StoreStallD, .CSRWriteM, .CSRMWriteM,
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.BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM,
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