diff --git a/config/buildroot/config.vh b/config/buildroot/config.vh index 35264cd13..6376904dc 100644 --- a/config/buildroot/config.vh +++ b/config/buildroot/config.vh @@ -159,4 +159,4 @@ localparam ZBS_SUPPORTED = 0; // Memory synthesis configuration localparam USE_SRAM = 0; -`include "test-shared.vh" +`include "config-shared.vh" diff --git a/config/fpga/config.vh b/config/fpga/config.vh index 1e81c653f..3551da010 100644 --- a/config/fpga/config.vh +++ b/config/fpga/config.vh @@ -172,4 +172,4 @@ localparam ZBS_SUPPORTED = 1; // Memory synthesis configuration localparam USE_SRAM = 0; -`include "test-shared.vh" +`include "config-shared.vh" diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index 762e962fe..83c4efd52 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -160,5 +160,5 @@ localparam ZBS_SUPPORTED = 0; // Memory synthesis configuration localparam USE_SRAM = 0; -`include "test-shared.vh" +`include "config-shared.vh" diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index ad03c2956..5479e5fde 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -161,4 +161,4 @@ localparam ZBS_SUPPORTED = 1; // Memory synthesis configuration localparam USE_SRAM = 0; -`include "test-shared.vh" +`include "config-shared.vh" diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index 9ceaec1f8..1897ddeb2 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -160,4 +160,4 @@ localparam ZBS_SUPPORTED = 0; // Memory synthesis configuration localparam USE_SRAM = 0; -`include "test-shared.vh" +`include "config-shared.vh" diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index fd0e28b65..85d3597f9 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -159,4 +159,4 @@ localparam ZBS_SUPPORTED = 0; // Memory synthesis configuration localparam USE_SRAM = 0; -`include "test-shared.vh" +`include "config-shared.vh" diff --git a/config/rv64fpquad/config.vh b/config/rv64fpquad/config.vh index ba74da9a3..f0c6cc6b2 100644 --- a/config/rv64fpquad/config.vh +++ b/config/rv64fpquad/config.vh @@ -162,4 +162,4 @@ localparam ZBS_SUPPORTED = 0; // Memory synthesis configuration localparam USE_SRAM = 0; -`include "test-shared.vh" +`include "config-shared.vh" diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index e79e65680..31336c6b8 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -165,4 +165,4 @@ localparam ZBS_SUPPORTED = 1; // Memory synthesis configuration localparam USE_SRAM = 0; -`include "test-shared.vh" +`include "config-shared.vh" diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index 3c0b6f77b..3d7f33544 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -162,4 +162,4 @@ localparam ZBS_SUPPORTED = 0; // Memory synthesis configuration localparam USE_SRAM = 0; -`include "test-shared.vh" +`include "config-shared.vh" diff --git a/config/shared/test-shared.vh b/config/shared/config-shared.vh similarity index 100% rename from config/shared/test-shared.vh rename to config/shared/config-shared.vh diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index ef14bda78..5e14d3122 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -112,8 +112,6 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( assign Xfract = (IFX << ell) << 1; assign Dfract = (IFD << mE) << 1; - // *** CT: move to fdivsqrtintpreshift - ////////////////////////////////////////////////////// // Integer Right Shift to digit boundary // Determine DivXShifted (X shifted to digit boundary) @@ -141,8 +139,8 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( assign IntTrunc = TotalIntBits % P.RK; // Truncation check for ceiling operator assign IntSteps = (TotalIntBits >> P.LOGRK) + |IntTrunc; // Number of steps for int div assign nE = (IntSteps * P.DIVCOPIES) - 1; // Fractional digits - assign RightShiftX = P.RK - 1 - ((TotalIntBits - 1) % P.RK); // Right shift amount - assign DivXShifted = DivX >> RightShiftX; // shift X by up to R*K-1 to complete in nE steps + assign RightShiftX = P.RK - 1 - ((TotalIntBits - 1) % P.RK); // Right shift amount + assign DivXShifted = DivX >> RightShiftX; // shift X by up to R*K-1 to complete in nE steps /* verilator lint_on WIDTH */ end else begin // radix 2 1 copy doesn't require shifting assign nE = p; @@ -152,14 +150,14 @@ module fdivsqrtpreproc import cvw::*; #(parameter cvw_t P) ( assign ISpecialCaseE = 0; end - // CT *** fdivsqrtfplead1 - ////////////////////////////////////////////////////// // Floating-Point Preprocessing // append leading 1 (for nonzero inputs) // shift square root to be in range [1/4, 1) // Normalized numbers are shifted right by 1 if the exponent is odd - // Denormalized numbers have Xe = 0 and an unbiased exponent of 1-BIAS. They are shifted right if the number of leading zeros is odd. + // Subnormal numbers have Xe = 0 and an unbiased exponent of 1-BIAS. They are shifted right if the number of leading zeros is odd. + // NOTE: there might be a discrepancy that X is never right shifted by 2. However + // it comes out in the wash and gives the right answer. Investigate later if possible. ////////////////////////////////////////////////////// assign DivX = {3'b000, ~NumerZeroE, Xfract}; diff --git a/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv index ea564ec63..f2a643101 100644 --- a/src/uncore/plic_apb.sv +++ b/src/uncore/plic_apb.sv @@ -73,6 +73,15 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( logic [`C-1:0][7:1] threshMask; logic [P.PLIC_NUM_SRC-1:0] One; + // hacks to handle gracefully PLIC_NUM_SRC being smaller than 32 + // Otherwise Questa and other simulators produce part-select out of bounds even + // though sources >=32 are never used + + localparam PLIC_SRC_TOP = (P.PLIC_NUM_SRC >= 32) ? P.PLIC_NUM_SRC : 1; + localparam PLIC_SRC_BOT = (P.PLIC_NUM_SRC >= 32) ? 32 : 1; + localparam PLIC_SRC_DINTOP = (P.PLIC_NUM_SRC >= 32) ? P.PLIC_NUM_SRC -32 : 0; + localparam PLIC_SRC_EXT = (P.PLIC_NUM_SRC >= 32) ? 63-P.PLIC_NUM_SRC : 31; + // ======= // AHB I/O // ======= @@ -107,18 +116,13 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( intInProgress <= #1 '0; // writing end else begin - if (memwrite) + if (memwrite) casez(entry) 24'h0000??: intPriority[entry[7:2]] <= #1 Din[2:0]; 24'h002000: intEn[0][PLIC_NUM_SRC_MIN_32:1] <= #1 Din[PLIC_NUM_SRC_MIN_32:1]; 24'h002080: intEn[1][PLIC_NUM_SRC_MIN_32:1] <= #1 Din[PLIC_NUM_SRC_MIN_32:1]; - - // verilator lint_off SELRANGE - // *** RT: Long term we want to factor out these variable number of registers as a generate loop - // I think this won't work as a case statement. - 24'h002004: if (P.PLIC_NUM_SRC >= 32) intEn[0][P.PLIC_NUM_SRC:32] <= #1 Din[P.PLIC_NUM_SRC-32:0]; - 24'h002084: if (P.PLIC_NUM_SRC >= 32) intEn[1][P.PLIC_NUM_SRC:32] <= #1 Din[P.PLIC_NUM_SRC-32:0]; - // verilator lint_on SELRANGE + 24'h002004: if (P.PLIC_NUM_SRC >= 32) intEn[0][PLIC_SRC_TOP:PLIC_SRC_BOT] <= #1 Din[PLIC_SRC_DINTOP:0]; + 24'h002084: if (P.PLIC_NUM_SRC >= 32) intEn[1][PLIC_SRC_TOP:PLIC_SRC_BOT] <= #1 Din[PLIC_SRC_DINTOP:0]; 24'h200000: intThreshold[0] <= #1 Din[2:0]; 24'h200004: intInProgress <= #1 intInProgress & ~(One << (Din[5:0]-1)); // lower "InProgress" to signify completion 24'h201000: intThreshold[1] <= #1 Din[2:0]; @@ -131,20 +135,10 @@ module plic_apb import cvw::*; #(parameter cvw_t P) ( 24'h0000??: Dout <= #1 {29'b0,intPriority[entry[7:2]]}; 24'h001000: Dout <= #1 {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intPending[PLIC_NUM_SRC_MIN_32:1],1'b0}; 24'h002000: Dout <= #1 {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intEn[0][PLIC_NUM_SRC_MIN_32:1],1'b0}; - - // verilator lint_off SELRANGE - // verilator lint_off WIDTHTRUNC - 24'h001004: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intPending[P.PLIC_NUM_SRC:32]}; - 24'h002004: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intEn[0][P.PLIC_NUM_SRC:32]}; - // verilator lint_on SELRANGE - // verilator lint_on WIDTHTRUNC - + 24'h001004: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(PLIC_SRC_EXT){1'b0}},intPending[PLIC_SRC_TOP:PLIC_SRC_BOT]}; + 24'h002004: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(PLIC_SRC_EXT){1'b0}},intEn[0][PLIC_SRC_TOP:PLIC_SRC_BOT]}; 24'h002080: Dout <= #1 {{(31-PLIC_NUM_SRC_MIN_32){1'b0}},intEn[1][PLIC_NUM_SRC_MIN_32:1],1'b0}; - // verilator lint_off SELRANGE - // verilator lint_off WIDTHTRUNC - 24'h002084: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(63-P.PLIC_NUM_SRC){1'b0}},intEn[1][P.PLIC_NUM_SRC:32]}; - // verilator lint_on SELRANGE - // verilator lint_on WIDTHTRUNC + 24'h002084: if (P.PLIC_NUM_SRC >= 32) Dout <= #1 {{(PLIC_SRC_EXT){1'b0}},intEn[1][PLIC_SRC_TOP:PLIC_SRC_BOT]}; 24'h200000: Dout <= #1 {29'b0,intThreshold[0]}; 24'h200004: begin Dout <= #1 {26'b0,intClaim[0]};