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CacheFSM logic simplification for AMO operations

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Ran this by Ross.
This commit is contained in:
Alec Vercruysse 2023-04-19 01:32:43 -07:00
parent de93bd6937
commit faaf266558
1 changed files with 4 additions and 5 deletions
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9
src/cache/cachefsm.sv vendored
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@ -69,7 +69,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
); );
logic resetDelay; logic resetDelay;
logic AMO, StoreAMO; logic StoreAMO;
logic AnyUpdateHit, AnyHit; logic AnyUpdateHit, AnyHit;
logic AnyMiss; logic AnyMiss;
logic FlushFlag; logic FlushFlag;
@ -86,16 +86,15 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
statetype CurrState, NextState; statetype CurrState, NextState;
assign AMO = CacheAtomic[1] & (&CacheRW); assign StoreAMO = CacheRW[0]; // AMO operations assert CacheRW[0]
assign StoreAMO = AMO | CacheRW[0];
assign AnyMiss = (StoreAMO | CacheRW[1]) & ~CacheHit & ~InvalidateCache; // exclusion-tag: icache storeAMO assign AnyMiss = (StoreAMO | CacheRW[1]) & ~CacheHit & ~InvalidateCache; // exclusion-tag: cache AnyMiss
assign AnyUpdateHit = (StoreAMO) & CacheHit; // exclusion-tag: icache storeAMO1 assign AnyUpdateHit = (StoreAMO) & CacheHit; // exclusion-tag: icache storeAMO1
assign AnyHit = AnyUpdateHit | (CacheRW[1] & CacheHit); // exclusion-tag: icache AnyUpdateHit assign AnyHit = AnyUpdateHit | (CacheRW[1] & CacheHit); // exclusion-tag: icache AnyUpdateHit
assign FlushFlag = FlushAdrFlag & FlushWayFlag; assign FlushFlag = FlushAdrFlag & FlushWayFlag;
// outputs for the performance counters. // outputs for the performance counters.
assign CacheAccess = (AMO | CacheRW[1] | CacheRW[0]) & CurrState == STATE_READY; // exclusion-tag: icache CacheW assign CacheAccess = (|CacheRW) & CurrState == STATE_READY; // exclusion-tag: icache CacheW
assign CacheMiss = CacheAccess & ~CacheHit; assign CacheMiss = CacheAccess & ~CacheHit;
// special case on reset. When the fsm first exists reset the // special case on reset. When the fsm first exists reset the