From fa8914a8304be207fcebc037bf4654fe255a80f9 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 31 Jan 2022 12:11:42 -0600 Subject: [PATCH] Cleanup busdp. --- pipelined/src/lsu/busdp.sv | 39 ++++----- pipelined/src/lsu/busfsm.sv | 30 +++---- pipelined/src/lsu/lsu.sv | 163 ++++++++++++++++++------------------ 3 files changed, 112 insertions(+), 120 deletions(-) diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv index 0dbc5688d..1b5f7c716 100644 --- a/pipelined/src/lsu/busdp.sv +++ b/pipelined/src/lsu/busdp.sv @@ -77,30 +77,25 @@ module busdp #(parameter WORDSPERLINE, parameter LINELEN) logic [LOGWPL-1:0] WordCount; genvar index; - for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer - flopen #(`XLEN) fb(.clk, .en(LSUBusAck & LSUBusRead & (index == WordCount)), - .d(LSUBusHRDATA), .q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN])); - end + for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer + flopen #(`XLEN) fb(.clk, .en(LSUBusAck & LSUBusRead & (index == WordCount)), + .d(LSUBusHRDATA), .q(DCacheMemWriteData[(index+1)*`XLEN-1:index*`XLEN])); + end - assign LocalLSUBusAdr = SelUncachedAdr ? LSUPAdrM : DCacheBusAdr ; - assign LSUBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLSUBusAdr; - assign PreLSUBusHWDATA = ReadDataLineSetsM[WordCount]; // only in lsu, not ifu - // exclude the subword write for uncached. We don't read the data first so we cannot - // select the subword by masking. Subword write also exists inside the uncore to - // suport subword masking for i/o. I'm not sure if this is necessary. - assign LSUBusHWDATA = SelUncachedAdr ? FinalAMOWriteDataM : PreLSUBusHWDATA; // only in lsu, not ifu - assign LSUBusSize = SelUncachedAdr ? LSUFunct3M : (`XLEN == 32 ? 3'b010 : 3'b011); // ifu: always the XLEN value. + mux2 #(`PA_BITS) localadrmux(DCacheBusAdr, LSUPAdrM, SelUncachedAdr, LocalLSUBusAdr); + assign LSUBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalLSUBusAdr; + assign PreLSUBusHWDATA = ReadDataLineSetsM[WordCount]; // only in lsu, not ifu + mux2 #(`XLEN) lsubushwdatamux(.d0(PreLSUBusHWDATA), .d1(FinalAMOWriteDataM), + .s(SelUncachedAdr), .y(LSUBusHWDATA)); + mux2 #(3) lsubussizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), + .s(SelUncachedAdr), .y(LSUBusSize)); + mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM), .d1(DCacheMemWriteData[`XLEN-1:0]), + .s(SelUncachedAdr), .y(ReadDataWordMuxM)); - // select between dcache and direct from the BUS. Always selected if no dcache. - mux2 #(`XLEN) UnCachedDataMux(.d0(ReadDataWordM), - .d1(DCacheMemWriteData[`XLEN-1:0]), - .s(SelUncachedAdr), - .y(ReadDataWordMuxM)); - - busfsm #(WordCountThreshold, LOGWPL, `MEM_DCACHE) - busfsm(.clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine, - .LSUBusAck, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusRead, - .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount); + busfsm #(WordCountThreshold, LOGWPL, `MEM_DCACHE) + busfsm(.clk, .reset, .IgnoreRequest, .LSURWM, .DCacheFetchLine, .DCacheWriteLine, + .LSUBusAck, .CPUBusy, .CacheableM, .BusStall, .LSUBusWrite, .LSUBusRead, + .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount); endmodule diff --git a/pipelined/src/lsu/busfsm.sv b/pipelined/src/lsu/busfsm.sv index ae85fa870..9eb6b386a 100644 --- a/pipelined/src/lsu/busfsm.sv +++ b/pipelined/src/lsu/busfsm.sv @@ -33,23 +33,23 @@ module busfsm #(parameter integer WordCountThreshold, parameter integer LOGWPL, parameter logic CacheEnabled ) - (input logic clk, - input logic reset, + (input logic clk, + input logic reset, - input logic IgnoreRequest, - input logic [1:0] LSURWM, - input logic DCacheFetchLine, - input logic DCacheWriteLine, - input logic LSUBusAck, - input logic CPUBusy, - input logic CacheableM, + input logic IgnoreRequest, + input logic [1:0] LSURWM, + input logic DCacheFetchLine, + input logic DCacheWriteLine, + input logic LSUBusAck, + input logic CPUBusy, + input logic CacheableM, - output logic BusStall, - output logic LSUBusWrite, - output logic LSUBusRead, - output logic DCacheBusAck, - output logic BusCommittedM, - output logic SelUncachedAdr, + output logic BusStall, + output logic LSUBusWrite, + output logic LSUBusRead, + output logic DCacheBusAck, + output logic BusCommittedM, + output logic SelUncachedAdr, output logic [LOGWPL-1:0] WordCount); diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 07194535d..587060c54 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -33,79 +33,79 @@ `include "wally-config.vh" module lsu ( - input logic clk, reset, - input logic StallM, FlushM, StallW, FlushW, - output logic LSUStallM, + input logic clk, reset, + input logic StallM, FlushM, StallW, FlushW, + output logic LSUStallM, // connected to cpu (controls) - input logic [1:0] MemRWM, - input logic [2:0] Funct3M, - input logic [6:0] Funct7M, - input logic [1:0] AtomicM, - input logic TrapM, - input logic FlushDCacheM, - output logic CommittedM, - output logic SquashSCW, - output logic DCacheMiss, - output logic DCacheAccess, + input logic [1:0] MemRWM, + input logic [2:0] Funct3M, + input logic [6:0] Funct7M, + input logic [1:0] AtomicM, + input logic TrapM, + input logic FlushDCacheM, + output logic CommittedM, + output logic SquashSCW, + output logic DCacheMiss, + output logic DCacheAccess, // address and write data - input logic [`XLEN-1:0] IEUAdrE, - (* mark_debug = "true" *)output logic [`XLEN-1:0] IEUAdrM, - input logic [`XLEN-1:0] WriteDataM, - output logic [`XLEN-1:0] ReadDataM, + input logic [`XLEN-1:0] IEUAdrE, + (* mark_debug = "true" *)output logic [`XLEN-1:0] IEUAdrM, + input logic [`XLEN-1:0] WriteDataM, + output logic [`XLEN-1:0] ReadDataM, // cpu privilege - input logic [1:0] PrivilegeModeW, - input logic DTLBFlushM, + input logic [1:0] PrivilegeModeW, + input logic DTLBFlushM, // faults - output logic LoadPageFaultM, StoreAmoPageFaultM, - output logic LoadMisalignedFaultM, LoadAccessFaultM, + output logic LoadPageFaultM, StoreAmoPageFaultM, + output logic LoadMisalignedFaultM, LoadAccessFaultM, // cpu hazard unit (trap) - output logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM, - // connect to ahb -(* mark_debug = "true" *) output logic [`PA_BITS-1:0] LSUBusAdr, -(* mark_debug = "true" *) output logic LSUBusRead, -(* mark_debug = "true" *) output logic LSUBusWrite, -(* mark_debug = "true" *) input logic LSUBusAck, -(* mark_debug = "true" *) input logic [`XLEN-1:0] LSUBusHRDATA, -(* mark_debug = "true" *) output logic [`XLEN-1:0] LSUBusHWDATA, -(* mark_debug = "true" *) output logic [2:0] LSUBusSize, - // page table walker - input logic [`XLEN-1:0] SATP_REGW, // from csr - input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, - input logic [1:0] STATUS_MPP, - input logic [`XLEN-1:0] PCF, - input logic ITLBMissF, - output logic [`XLEN-1:0] PTE, - output logic [1:0] PageType, - output logic ITLBWriteF, - input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], - input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // *** this one especially has a large note attached to it in pmpchecker. + output logic StoreAmoMisalignedFaultM, StoreAmoAccessFaultM, + // connect to ahb + (* mark_debug = "true" *) output logic [`PA_BITS-1:0] LSUBusAdr, + (* mark_debug = "true" *) output logic LSUBusRead, + (* mark_debug = "true" *) output logic LSUBusWrite, + (* mark_debug = "true" *) input logic LSUBusAck, + (* mark_debug = "true" *) input logic [`XLEN-1:0] LSUBusHRDATA, + (* mark_debug = "true" *) output logic [`XLEN-1:0] LSUBusHWDATA, + (* mark_debug = "true" *) output logic [2:0] LSUBusSize, + // page table walker + input logic [`XLEN-1:0] SATP_REGW, // from csr + input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, + input logic [1:0] STATUS_MPP, + input logic [`XLEN-1:0] PCF, + input logic ITLBMissF, + output logic [`XLEN-1:0] PTE, + output logic [1:0] PageType, + output logic ITLBWriteF, + input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], + input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // *** this one especially has a large note attached to it in pmpchecker. ); - logic [`PA_BITS-1:0] LSUPAdrM; // from mmu to dcache - logic DTLBMissM; - logic DTLBWriteM; - logic [1:0] LSURWM; - logic [1:0] PreLSURWM; - logic [2:0] LSUFunct3M; - logic [6:0] LSUFunct7M; - logic [1:0] LSUAtomicM; -(* mark_debug = "true" *) logic [`PA_BITS-1:0] PreLSUPAdrM, LocalLSUBusAdr; - logic [11:0] PreLSUAdrE, LSUAdrE; - logic CPUBusy; - logic DCacheStallM; - logic CacheableM; - logic SelHPTW; - logic BusStall; - logic InterlockStall; - logic IgnoreRequest; - logic BusCommittedM, DCacheCommittedM; - - //////////////////////////////////////////////////////////////////////////////////////////////// - // HPTW and Interlock FSM (only needed if VM supported) - // MMU include PMP and is needed if any privileged supported - //////////////////////////////////////////////////////////////////////////////////////////////// + logic [`PA_BITS-1:0] LSUPAdrM; // from mmu to dcache + logic DTLBMissM; + logic DTLBWriteM; + logic [1:0] LSURWM; + logic [1:0] PreLSURWM; + logic [2:0] LSUFunct3M; + logic [6:0] LSUFunct7M; + logic [1:0] LSUAtomicM; + (* mark_debug = "true" *) logic [`PA_BITS-1:0] PreLSUPAdrM; + logic [11:0] PreLSUAdrE, LSUAdrE; + logic CPUBusy; + logic DCacheStallM; + logic CacheableM; + logic SelHPTW; + logic BusStall; + logic InterlockStall; + logic IgnoreRequest; + logic BusCommittedM, DCacheCommittedM; flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); + + ///////////////////////////////////////////////////////////////////////////////////////////// + // HPTW and Interlock FSM (only needed if VM supported) + // MMU include PMP and is needed if any privileged supported + ///////////////////////////////////////////////////////////////////////////////////////////// logic [`XLEN+1:0] IEUAdrExtM; assign IEUAdrExtM = {2'b00, IEUAdrM}; @@ -118,8 +118,7 @@ module lsu ( .LSUAdrE, .PreLSUPAdrM, .CPUBusy, .InterlockStall, .SelHPTW, .IgnoreRequest); - end // if (`MEM_VIRTMEM) - else begin + end else begin assign {InterlockStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF} = '0; assign IgnoreRequest = TrapM; assign CPUBusy = StallW; @@ -168,10 +167,10 @@ module lsu ( end assign LSUStallM = DCacheStallM | InterlockStall | BusStall; - //////////////////////////////////////////////////////////////////////////////////////////////// + ///////////////////////////////////////////////////////////////////////////////////////////// // Hart Memory System // Either Data Cache or Data Tightly Integrated Memory or just bus interface - //////////////////////////////////////////////////////////////////////////////////////////////// + ///////////////////////////////////////////////////////////////////////////////////////////// localparam integer WORDSPERLINE = `MEM_DCACHE ? `DCACHE_LINELENINBITS/`XLEN : 1; localparam integer LINELEN = `MEM_DCACHE ? `DCACHE_LINELENINBITS : `XLEN; @@ -207,13 +206,14 @@ module lsu ( cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(`DCACHE_NUMWAYS), .DCACHE(1)) dcache(.clk, .reset, .CPUBusy, - .RW(CacheableM ? LSURWM : 2'b00), .FlushCache(FlushDCacheM), .Atomic(CacheableM ? LSUAtomicM : 2'b00), - .NextAdr(LSUAdrE), .PAdr(LSUPAdrM), - .FinalWriteData(FinalWriteDataM), .ReadDataWord(ReadDataWordM), .CacheStall(DCacheStallM), - .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), - .IgnoreRequest, .CacheCommitted(DCacheCommittedM), - .CacheBusAdr(DCacheBusAdr), .ReadDataLineSets(ReadDataLineSetsM), .CacheMemWriteData(DCacheMemWriteData), - .CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0)); + .RW(CacheableM ? LSURWM : 2'b00), .FlushCache(FlushDCacheM), + .Atomic(CacheableM ? LSUAtomicM : 2'b00), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM), + .FinalWriteData(FinalWriteDataM), .ReadDataWord(ReadDataWordM), + .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), + .IgnoreRequest, .CacheCommitted(DCacheCommittedM), .CacheBusAdr(DCacheBusAdr), + .ReadDataLineSets(ReadDataLineSetsM), .CacheMemWriteData(DCacheMemWriteData), + .CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine), + .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0)); end else begin : passthrough assign {ReadDataWordM, DCacheStallM, DCacheCommittedM, DCacheWriteLine, DCacheFetchLine, DCacheBusAdr} = '0; @@ -237,19 +237,16 @@ module lsu ( .HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM)); - //////////////////////////////////////////////////////////////////////////////////////////////// + ///////////////////////////////////////////////////////////////////////////////////////////// // Atomic operations - //////////////////////////////////////////////////////////////////////////////////////////////// + ///////////////////////////////////////////////////////////////////////////////////////////// if (`A_SUPPORTED) begin:lrsc - /*atomic atomic(.clk, .reset, .FlushW, .CPUBusy, .MemRead, .PreLSURWM, .LSUAtomicM, .LSUPAdrM, - .SquashSCM, .LSURWM, ... ); *** */ - atomic atomic(.clk, .reset, .FlushW, .CPUBusy, .ReadDataM, .WriteDataM, .LSUPAdrM, .LSUFunct7M, - .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, .DTLBMissM, - .FinalAMOWriteDataM, .SquashSCW, .LSURWM); + atomic atomic(.clk, .reset, .FlushW, .CPUBusy, .ReadDataM, .WriteDataM, .LSUPAdrM, + .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, + .DTLBMissM, .FinalAMOWriteDataM, .SquashSCW, .LSURWM); end else begin:lrsc assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign FinalAMOWriteDataM = WriteDataM; end endmodule -