Merge branch 'main' of https://github.com/openhwgroup/cvw

README.md

@@ -1,12 +1,15 @@
 # core-v-wally
-Configurable RISC-V Processor
 
-Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, and M extensions, FENCE.I, and the various privileged modes and CSRs.  It is written in SystemVerilog.  It passes the RISC-V Arch Tests and boots Linux on an FPGA.
+Wally is a 5-stage pipelined processor configurable to support all the standard RISC-V options, incluidng RV32/64, A, C, F, D, Q, M, and Zb* extensions, virtual memory, PMP, and the various privileged modes and CSRs. It provides optional caches, branch prediction, and standard RISC-V peripherals (CLINT, PLIC, UART, GPIO).   Wally is written in SystemVerilog.  It passes the RISC-V Arch Tests and boots Linux on an FPGA.  Configurations range from a minimal RV32E core to a fully featured RV64GC application processor.
 
 ![Wally block diagram](wallyriscvTopAll.png)
 
 Wally is described in an upcoming textbook, *RISC-V System-on-Chip Design*, by Harris, Stine, Thompson, and Harris.  Users should follow the setup instructions below.  A system administrator must install CAD tools using the directions further down.
 
+# Verification
+
+Wally is presently at Technology Readiness Level 4, passing the RISC-V compatibility test suite and custom tests, and booting Linux in simulation and on an FPGA.  See the [Test Plan](docs/testplan.md) for details.
+
 # New User Setup
 
 New users may wish to do the following setup to access the server via a GUI and use a text editor.

bin/CacheSim.py

@@ -5,7 +5,7 @@
 ##
 ## Written: lserafini@hmc.edu
 ## Created: 27 March 2023
-## Modified: 5 April 2023
+## Modified: 12 April 2023
 ##
 ## Purpose: Simulate a L1 D$ or I$ for comparison with Wally
 ##
@@ -36,6 +36,9 @@
 # This helps avoid unexpected logger behavior.
 # With verbose mode off, the simulator only reports mismatches between its and Wally's behavior.
 # With verbose mode on, the simulator logs each access into the cache.
+# Add -p or --perf to report the hit/miss ratio. 
+# Add -d or --dist to report the distribution of loads, stores, and atomic ops.
+# These distributions may not add up to 100; this is because of flushes or invalidations.
 
 import sys
 import math
@@ -197,11 +200,24 @@ if __name__ == "__main__":
     parser.add_argument('taglen', type=int, help="Length of the tag in bits", metavar="T")
     parser.add_argument('-f', "--file", required=True, help="Log file to simulate from")
     parser.add_argument('-v', "--verbose", action='store_true', help="verbose/full-trace mode")
+    parser.add_argument('-p', "--perf", action='store_true', help="Report hit/miss ratio")
+    parser.add_argument('-d', "--dist", action='store_true', help="Report distribution of operations")
 
     args = parser.parse_args()
     cache = Cache(args.numlines, args.numways, args.addrlen, args.taglen)
-    #numtests = -1
     extfile = os.path.expanduser(args.file)
+    nofails = True
+
+    if args.perf:
+        hits = 0
+        misses = 0
+
+    if args.dist:
+        loads = 0
+        stores = 0
+        atoms = 0
+        totalops = 0
+
     with open(extfile, "r") as f:
         for ln in f:
             ln = ln.strip()
@@ -212,11 +228,13 @@ if __name__ == "__main__":
                     # trying TRAIN clears instead
                     cache.invalidate() # a new test is starting, so 'empty' the cache
                     cache.clear_pLRU()
-                    #numtests +=1
                     if args.verbose:
                         print("New Test")
                         
             else:
+                if args.dist:
+                    totalops += 1
+                
                 if lninfo[1] == 'F':
                     cache.flush()
                     if args.verbose:
@@ -229,13 +247,37 @@ if __name__ == "__main__":
                     addr = int(lninfo[0], 16)
                     iswrite = lninfo[1] == 'W' or lninfo[1] == 'A'
                     result = cache.cacheaccess(addr, iswrite)
+                    
                     if args.verbose:
                         tag, setnum, offset = cache.splitaddr(addr)
                         print(hex(addr), hex(tag), hex(setnum), hex(offset), lninfo[2], result)
+                    
+                    if args.perf:
+                        if result == 'H':
+                            hits += 1
+                        else:
+                            misses += 1
+                    
+                    if args.dist:
+                        if lninfo[1] == 'R':
+                            loads += 1
+                        elif lninfo[1] == 'W':
+                            stores += 1
+                        elif lninfo[1] == 'A':
+                            atoms += 1
+                    
                     if not result == lninfo[2]:
-                        print("Result mismatch at address", lninfo[0], ". Wally:", lninfo[2],", Sim:", result) #, "in test", numtests)
+                        print("Result mismatch at address", lninfo[0]+ ". Wally:", lninfo[2]+", Sim:", result)
-                        
+                        nofails = False
-                        
+    if args.dist:
-
+        percent_loads = str(round(100*loads/totalops))
+        percent_stores = str(round(100*stores/totalops))
+        percent_atoms = str(round(100*atoms/totalops))
+        print("This log had", percent_loads+"% loads,", percent_stores+"% stores, and", percent_atoms+"% atomic operations.")
     
-
+    if args.perf:
+        ratio = round(hits/misses,3)
+        print("There were", hits, "hits and", misses, "misses. The hit/miss ratio was", str(ratio)+".")
+    
+    if nofails:
+        print("SUCCESS! There were no mismatches between Wally and the sim.")

config/rv32gc/wally-config.vh

@@ -137,7 +137,7 @@
 `define BPRED_SIZE 16
 `define BTB_SIZE 10
 
-`define SVADU_SUPPORTED 0
+`define SVADU_SUPPORTED 1
 `define ZMMUL_SUPPORTED 0
 
 // FPU division architecture

config/rv64gc/wally-config.vh

@@ -140,7 +140,7 @@
 `define BPRED_SIZE 10
 `define BTB_SIZE 10
 
-`define SVADU_SUPPORTED 0
+`define SVADU_SUPPORTED 1
 `define ZMMUL_SUPPORTED 0
 
 // FPU division architecture

docs/testplans/testplan.md

@@ -0,0 +1,29 @@
+# CORE-V Wally Test Plan
+
+CORE-V Wally is tested in the following ways:
+
+* Run [RISC-V Architecture Compatibility Tests](https://github.com/riscv-non-isa/riscv-arch-test) in lock-step against the ImperasDV reference model.
+* Run custom tests to cover virtual memory, PMP, privileged unit, and peripherals in lock step against ImperasDV.
+* ***pending: Run random tests generated by risc-dv
+* Run CoreMark and Embench benchmarks.
+* Run performance validation against reference models for the branch predictor and caches.
+* Run the TestFloat suite against all precisions of all operations for the FPU unit.
+* *** 83.5% coverage of statements, branches, expressions, and FSM states and transitions
+* Boot Buildroot Linux in lock-step against ImperasDV.
+* Boot Buildroot Linux on an FPGA and run programs.
+
+# Running Tests
+
+# 
+
+# Detailed Test Plans
+
+The test plans for specific units are lined below:
+
+* Privileged Unit
+* Memory Management Unit
+* Peripherals
+* Branch Predictor Performance Validation
+* Cache Performance Validation
+
+Wally is described in an upcoming textbook, *RISC-V System-on-Chip Design*, by Harris, Stine, Thompson, and Harris.  

examples/fp/softfloat_demo/softfloat_demo2.c

@@ -0,0 +1,77 @@
+//
+// softfloat_div.c
+// james.stine@okstate.edu 12 April 2023
+// 
+// Demonstrate using SoftFloat to compute 754 fp divide, then print results
+// (adapted from original C built by David Harris)
+//
+
+#include <stdio.h>
+#include <stdint.h>
+#include "softfloat.h"
+#include "softfloat_types.h"
+typedef union sp {
+  uint32_t v;
+  unsigned short x[2];
+  float f;
+} sp;
+
+void printF32 (char *msg, float32_t f) {
+  sp conv;
+  int i, j;
+  conv.v = f.v; // use union to convert between hexadecimal and floating-point views
+  printf("%s: ", msg);  // print out nicely
+  printf("0x%04x_%04x = %1.15g\n", (conv.v >> 16),(conv.v & 0xFFFF), conv.f);
+}
+
+void printFlags(void) {
+  int NX = softfloat_exceptionFlags % 2;
+  int UF = (softfloat_exceptionFlags >> 1) % 2;
+  int OF = (softfloat_exceptionFlags >> 2) % 2;
+  int DZ = (softfloat_exceptionFlags >> 3) % 2;
+  int NV = (softfloat_exceptionFlags >> 4) % 2;
+  printf ("Flags: Inexact %d Underflow %d Overflow %d DivideZero %d Invalid %d\n", 
+          NX, UF, OF, DZ, NV);
+}
+
+void softfloatInit(void) {
+    // RNE: softfloat_round_near_even
+    // RZ:  softfloat_round_minMag
+    // RU:  softfloat_round_max
+    // RD:  softfloat_round_min
+    // RM: softfloat_round_near_maxMag   
+    softfloat_roundingMode = softfloat_round_near_even; 
+    softfloat_exceptionFlags = 0; // clear exceptions
+    softfloat_detectTininess = softfloat_tininess_afterRounding; // RISC-V behavior for tininess
+}
+
+int main() {
+
+  // float32_t is typedef in SoftFloat
+  float32_t x, y, r1, r2;
+  sp convx, convy;
+
+  // Choose two random values
+  convx.f = 1.30308703073;
+  convy.f = 1.903038030370;
+  // Convert to SoftFloat format
+  x.v = (convx.x[1] << 16) + convx.x[0];
+  y.v = (convy.x[1] << 16) + convy.x[0];  
+
+  printf("Example using SoftFloat\n");
+  
+  softfloatInit();
+  r1 = f32_div(x, y);
+  printf("-------\n");
+  printF32("X", x);
+  printF32("Y", y); 
+  printF32("result = X/Y", r1);
+  printFlags();
+
+  r2 = f32_sqrt(x);
+  printf("-------\n");    
+  printF32("X", x);
+  printF32("result = sqrt(X)", r2);
+  printFlags();  
+
+}

sim/GetLineNum.do

@@ -0,0 +1,18 @@
+# Alec Vercruysse
+# 2023-04-12
+# Note that the target string is regex, and needs to be double-escaped.
+# e.g. to match a (, you need \\(.
+proc GetLineNum {fname target} {
+    set f [open $fname]
+    set linectr 1
+    while {[gets $f line] != -1} {
+         if {[regexp $target $line]} {
+             close $f
+             return $linectr
+         }
+         incr linectr
+     }
+    close $f
+    return -code error \
+         "target string not found"
+}

sim/coverage-exclusions-rv64gc.do

@@ -27,23 +27,101 @@
 # This file should be a last resort.  It's preferable to put 
 # // coverage off 
 # statements inline with the code whenever possible.
+# a hack to describe coverage exclusions without hardcoding linenumbers:
+do GetLineNum.do
 
 # LZA (i<64) statement confuses coverage tool 
 # This is ugly to exlcude the whole file - is there a better option?  // coverage off isn't working
 coverage exclude -srcfile lzc.sv 
 
+# FDIVSQRT has 
+coverage exclude -scope /dut/core/fpu/fpu/fdivsqrt/fdivsqrtfsm -ftrans state DONE->BUSY
 
-######################
+### Exclude D$ states and logic for the I$ instance
-# Toggle exclusions
+# This is cleaner than trying to set an I$-specific pragma in cachefsm.sv (which would exclude it for the D$ instance too)
-#   Not used because toggle coverage isn't measured
+# Also exclude the write line to ready transition for the I$ since we can't get a flush during this operation.
-######################
+coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -fstate CurrState STATE_FLUSH STATE_FLUSH_WRITEBACK STATE_FLUSH_WRITEBACK STATE_WRITEBACK
+coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -ftrans CurrState STATE_WRITE_LINE->STATE_READY
+# exclude unused transitions from case statement. Unfortunately the whole branch needs to be excluded I think. Expression coverage should still work.
+coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache state-case"] -item b 1
+# exclude branch/condition coverage: LineDirty if statement
+coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache FETCHStatement"] -item bc 1
+# exclude the unreachable logic
+set start [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-start: icache case"]
+set end [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-end: icache case"]
+coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange $start-$end
+coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache WRITEBACKStatement"]
+# exclude Atomic Operation logic
+coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: cache AnyMiss"] -item e 1 -fecexprrow 6
+coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache storeAMO1"] -item e 1 -fecexprrow 2-4
+coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache AnyUpdateHit"] -item e 1 -fecexprrow 2
+# cache write logic
+coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache CacheW"] -item e 1 -fecexprrow 4
+# output signal logic
+coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache StallStates"] -item e 1 -fecexprrow 8 12 14
+set start [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-start: icache flushdirtycontrols"]
+set end [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-end: icache flushdirtycontrols"]
+coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange $start-$end
+coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache CacheBusW"]
+coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache SelAdrCauses"] -item e 1 -fecexprrow 4 10
+coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache CacheBusRCauses"] -item e 1 -fecexprrow 1-2 12
+# cache.sv AdrSelMux and CacheBusAdrMux, excluding unhit Flush branch
+coverage exclude -scope /dut/core/ifu/bus/icache/icache/AdrSelMux -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1
+coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheBusAdrMux -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1 3
+# CacheWay Dirty logic. -scope does not accept wildcards.
+set numcacheways 4
+for {set i 0} {$i < $numcacheways} {incr i} {
+    coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SetDirtyWay"] -item e 1
+    coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SelectedWiteWordEn"] -item e 1 -fecexprrow 4 6
+    # below: flushD can't go high during an icache write b/c of pipeline stall
+    coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SetValidEN"] -item e 1 -fecexprrow 4
+}
 
-# Exclude DivBusyE from all design units because rv64gc uses the fdivsqrt unit for integer division
+## D$ Exclusions.
-#coverage exclude -togglenode DivBusyE -du *
+# InvalidateCache is I$ only:
-# Exclude QuotM and RemM from MDU because rv64gc uses the fdivsqrt rather tha div unit for integer division
+coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: dcache InvalidateCheck"] -item b 2
-#coverage exclude -togglenode /dut/core/mdu/mdu/QuotM
+coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: dcache InvalidateCheck"] -item s 1
-#coverage exclude -togglenode /dut/core/mdu/mdu/RemM
+coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: dcache CacheEn"] -item e 1 -fecexprrow 12
+coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: cache AnyMiss"] -item e 1 -fecexprrow 4
+set numcacheways 4
+for {set i 0} {$i < $numcacheways} {incr i} {
+    coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: dcache invalidateway"] -item be 1 -fecexprrow 4
+}
+# D$ writeback, flush, write_line, or flush_writeback states can't be cancelled by a flush
+coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -ftrans CurrState STATE_WRITEBACK->STATE_READY STATE_FLUSH->STATE_READY STATE_WRITE_LINE->STATE_READY STATE_FLUSH_WRITEBACK->STATE_READY
 
-# StallFCause is hardwired to 0
-#coverage exclude -togglenode /dut/core/hzu/StallFCause
 
+# Excluding peripherals as sources of instructions for the ifu
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/clintdec
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/gpiodec
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uartdec
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/plicdec
+
+# Excluding so far un-used instruction sources for the ifu
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/bootromdec
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uncoreramdec
+
+
+#Excluding the bootrom, uncoreran, and clint as sources for the lsu
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/bootromdec
+
+
+#Excluding signals in lsu: clintdec and uncoreram accept all sizes so 'SizeValid' will never be 0
+set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"]
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/clintdec -linerange $line-$line -item e 1 -fecexprrow 5
+set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"]
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uncoreramdec -linerange $line-$line -item e 1 -fecexprrow 5
+
+# Excluding signals in lsu: the lsu never executes instructions so 'ExecuteAccess' will never be 1
+set line [GetLineNum ../src/mmu/pmachecker.sv "AccessRWX ="]
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 6
+set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"]
+coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 4
+
+# Excluding ReadAccess and WriteAccess signal in the ifu that will never be true
+set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| WriteAccessM"]
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 4
+set line [GetLineNum ../src/mmu/pmachecker.sv "WriteAccessM \\| ExecuteAccessF"]
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-5
+set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"]
+coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-3

sim/imperas.ic

@@ -30,8 +30,8 @@
 --override cpu/ignore_non_leaf_DAU=1
 --override cpu/wfi_is_nop=T
 --override cpu/misa_Extensions_mask=0x0
-#--override cpu/updatePTEA=T
+--override cpu/updatePTEA=T
-#--override cpu/updatePTED=T
+--override cpu/updatePTED=T
 --override cpu/Sstc=T
 
 # THIS NEEDS FIXING to 16

sim/regression-wally

@@ -28,6 +28,7 @@ regressionDir = os.path.dirname(os.path.abspath(__file__))
 os.chdir(regressionDir)
 
 coverage = '-coverage' in sys.argv
+fp = '-fp' in sys.argv
 
 TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr'])
 # name:     the name of this test configuration (used in printing human-readable
@@ -140,6 +141,9 @@ if (coverage):  # delete all but 64gc tests when running coverage
                  "arch64zi", "wally64a", "wally64periph", "wally64priv", 
                  "arch64zba",  "arch64zbb",  "arch64zbc",  "arch64zbs", 
                  "imperas64f", "imperas64d", "imperas64c", "imperas64i"] 
+    if (fp):
+       tests64gc.append("arch64f")
+       tests64gc.append("arch64d")
     coverStr = '-coverage'
 else:
    coverStr = ''

sim/rv64gc_CacheSim.py

@@ -0,0 +1,80 @@
+#!/usr/bin/env python3
+
+###########################################
+## rv64gc_CacheSim.py
+##
+## Written: lserafini@hmc.edu
+## Created: 11 April 2023
+## Modified: 12 April 2023
+##
+## Purpose: Run the cache simulator on each rv64gc test suite in turn. 
+##
+## A component of the CORE-V-WALLY configurable RISC-V project.
+##
+## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+##
+## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+##
+## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+## except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+## may obtain a copy of the License at
+##
+## https:##solderpad.org/licenses/SHL-2.1/
+##
+## Unless required by applicable law or agreed to in writing, any work distributed under the 
+## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+## either express or implied. See the License for the specific language governing permissions 
+## and limitations under the License.
+################################################################################################
+import sys
+import os
+import argparse
+
+# NOTE: make sure testbench.sv has the ICache and DCache loggers enabled!
+# This does not check the test output for correctness, run regression for that.
+# Add -p or --perf to report the hit/miss ratio. 
+# Add -d or --dist to report the distribution of loads, stores, and atomic ops.
+# These distributions may not add up to 100; this is because of flushes or invalidations.
+
+class bcolors:
+    HEADER = '\033[95m'
+    OKBLUE = '\033[94m'
+    OKCYAN = '\033[96m'
+    OKGREEN = '\033[92m'
+    WARNING = '\033[93m'
+    FAIL = '\033[91m'
+    ENDC = '\033[0m'
+    BOLD = '\033[1m'
+    UNDERLINE = '\033[4m'
+
+# tests64gc = ["coverage64gc", "arch64f", "arch64d", "arch64i", "arch64priv", "arch64c",  "arch64m", 
+tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c",  "arch64m",             
+             "arch64zi", "wally64a", "wally64periph", "wally64priv", 
+             "arch64zba",  "arch64zbb",  "arch64zbc",  "arch64zbs", 
+             "imperas64f", "imperas64d", "imperas64c", "imperas64i"]
+
+cachetypes = ["ICache", "DCache"]
+simdir = os.path.expanduser("~/cvw/sim")
+
+if __name__ == '__main__':
+    parser = argparse.ArgumentParser(description="Runs the cache simulator on all rv64gc test suites")
+    parser.add_argument('-p', "--perf", action='store_true', help="Report hit/miss ratio")
+    parser.add_argument('-d', "--dist", action='store_true', help="Report distribution of operations")
+
+    args = parser.parse_args()
+
+    testcmd = "vsim -do \"do wally-batch.do rv64gc {}\" -c > /dev/null"
+    cachecmd = "CacheSim.py 64 4 56 44 -f {}"
+    
+    if args.perf:
+        cachecmd += " -p"
+    if args.dist:
+        cachecmd += " -d"
+    
+    for test in tests64gc:
+        print(f"{bcolors.HEADER}Commencing test", test+f":{bcolors.ENDC}")
+        os.system(testcmd.format(test))
+        for cache in cachetypes:
+            print(f"{bcolors.OKCYAN}Running the", cache, f"simulator.{bcolors.ENDC}")
+            os.system(cachecmd.format(cache+".log"))
+        print()

sim/sim-testfloat-batch

@@ -4,9 +4,12 @@
 # cmp    - test comparison unit's LT, LE, EQ opperations (fcmp)
 # add    - test addition
 # fma    - test fma
+# mul    - test mult with fma
 # sub    - test subtraction
 # div    - test division
 # sqrt   - test square root
 # all    - test everything
 
-vsim -c -do "do testfloat.do rv64fpquad $1"
+# nowave for 2nd argument supresses wlf files
+
+vsim -c -do "do testfloat.do rv64fpquad $1 $2"

sim/testfloat.do

@@ -29,16 +29,19 @@ vlog +incdir+../config/$1 +incdir+../config/shared ../testbench/testbench-fp.sv
 
 vsim -voptargs=+acc work.testbenchfp -G TEST=$2
 
-view wave
+# Determine if nowave argument is provided
-#-- display input and output signals as hexidecimal values
+#   this removes any output to a wlf or wave window to reduce
-#do ./wave-dos/peripheral-waves.do
+#   disk space.
-add log -recursive /*
+if {($argc > 2) && ($3 eq "nowave")} {
-#do wave.do deal with when ready
+    puts "No wave output is selected"
-
+} else {
-do wave-fpu.do
+    puts "wave output is selected"
+    view wave
+    add log -recursive /*
+    do wave-fpu.do    
+}  
 
 #-- Run the Simulation 
-#run 3600 
 run -all
 noview testbench-fp.sv
 view wave

src/cache/cache.sv

@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// cache 
+// cache.sv
 //
 // Written: Ross Thompson ross1728@gmail.com
 // Created: 7 July 2021
@@ -122,7 +122,7 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
   // Select victim way for associative caches
   if(NUMWAYS > 1) begin:vict
     cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cacheLRU(
-      .clk, .reset, .CacheEn, .FlushStage, .HitWay, .ValidWay, .VictimWay, .CacheSet, .LRUWriteEn(LRUWriteEn & ~FlushStage),
+      .clk, .reset, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSet, .LRUWriteEn,
       .SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache, .FlushCache);
   end else 
     assign VictimWay = 1'b1; // one hot.
@@ -167,22 +167,22 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
     // Adjust byte mask from word to cache line
     onehotdecoder #(LOGCWPL) adrdec(.bin(PAdr[LOGCWPL+LOGLLENBYTES-1:LOGLLENBYTES]), .decoded(MemPAdrDecoded));
     for(index = 0; index < 2**LOGCWPL; index++) begin
-       assign DemuxedByteMask[(index+1)*(WORDLEN/8)-1:index*(WORDLEN/8)] = MemPAdrDecoded[index] ? ByteMask : '0;
+      assign DemuxedByteMask[(index+1)*(WORDLEN/8)-1:index*(WORDLEN/8)] = MemPAdrDecoded[index] ? ByteMask : '0;
     end
     assign FetchBufferByteSel = SetValid & ~SetDirty ? '1 : ~DemuxedByteMask;  // If load miss set all muxes to 1.
 
     // Merge write data into fetched cache line for store miss
     for(index = 0; index < LINELEN/8; index++) begin
-       mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]),
+      mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]),
-         .d1(FetchBuffer[8*index+7:8*index]), .s(FetchBufferByteSel[index]), .y(LineWriteData[8*index+7:8*index]));
+        .d1(FetchBuffer[8*index+7:8*index]), .s(FetchBufferByteSel[index]), .y(LineWriteData[8*index+7:8*index]));
     end
     assign LineByteMask = SetValid ? '1 : SetDirty ? DemuxedByteMask : '0;
   end
   else
     begin:WriteSelLogic
-       // No need for this mux if the cache does not handle writes.
+      // No need for this mux if the cache does not handle writes.
-       assign LineWriteData = FetchBuffer;
+      assign LineWriteData = FetchBuffer;
-       assign LineByteMask = '1;
+      assign LineByteMask = '1;
     end
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Flush logic
@@ -203,8 +203,8 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
     assign FlushWayFlag = FlushWay[NUMWAYS-1];
   end // block: flushlogic
   else begin:flushlogic
-     assign FlushWayFlag = 0;
+    assign FlushWayFlag = 0;
-     assign FlushAdrFlag = 0;
+    assign FlushAdrFlag = 0;
   end
    
   /////////////////////////////////////////////////////////////////////////////////////////////

src/cache/cacheLRU.sv

@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// dcache (data cache)
+// cacheLRU.sv
 //
 // Written: Ross Thompson ross1728@gmail.com
 // Created: 20 July 2021
@@ -32,12 +32,11 @@
 module cacheLRU
   #(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMLINES = 128) (
   input  logic                clk, 
-  input  logic                reset, 
+  input  logic                reset,
-  input  logic                FlushStage,      // Pipeline flush of second stage (prevent writes and bus operations)
   input  logic                CacheEn,         // Enable the cache memory arrays.  Disable hold read data constant
   input  logic [NUMWAYS-1:0]  HitWay,          // Which way is valid and matches PAdr's tag
   input  logic [NUMWAYS-1:0]  ValidWay,        // Which ways for a particular set are valid, ignores tag
-  input  logic [SETLEN-1:0]   CacheSet,            // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
+  input  logic [SETLEN-1:0]   CacheSet,        // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
   input  logic [SETLEN-1:0]   PAdr,            // Physical address 
   input  logic                LRUWriteEn,      // Update the LRU state
   input  logic                SetValid,        // Set the dirty bit in the selected way and set
@@ -90,16 +89,26 @@ module cacheLRU
     assign WayExpanded[StartIndex : EndIndex] = {{DuplicationFactor}{WayEncoded[row]}};
   end
 
-  genvar               r, a, s;
+  genvar               node;
   assign LRUUpdate[NUMWAYS-2] = '1;
-  for(s = NUMWAYS-2; s >= NUMWAYS/2; s--) begin : enables
+  for(node = NUMWAYS-2; node >= NUMWAYS/2; node--) begin : enables
-    localparam p = NUMWAYS - s - 1;
+    localparam ctr = NUMWAYS - node - 1;
-    localparam g = log2(p);
+    localparam ctr_depth = log2(ctr);
-    localparam t0 = s - p;
+    localparam lchild = node - ctr;
-    localparam t1 = t0 - 1;
+    localparam rchild = lchild - 1;
-    localparam r = LOGNUMWAYS - g;
+    localparam r = LOGNUMWAYS - ctr_depth;
-    assign LRUUpdate[t0] = LRUUpdate[s] & ~WayEncoded[r];
+
-    assign LRUUpdate[t1] = LRUUpdate[s] & WayEncoded[r];
+    // the child node will be updated if its parent was updated and
+    // the WayEncoded bit was the correct value.
+    // The if statement is only there for coverage since LRUUpdate[root] is always 1.
+    if (node == NUMWAYS-2) begin
+      assign LRUUpdate[lchild] = ~WayEncoded[r];
+      assign LRUUpdate[rchild] = WayEncoded[r];
+    end
+    else begin
+      assign LRUUpdate[lchild] = LRUUpdate[node] & ~WayEncoded[r];
+      assign LRUUpdate[rchild] = LRUUpdate[node] & WayEncoded[r];
+    end
   end
 
   // The root node of the LRU tree will always be selected in LRUUpdate. No mux needed.
@@ -107,15 +116,15 @@ module cacheLRU
   mux2 #(1) LRUMuxes[NUMWAYS-3:0](CurrLRU[NUMWAYS-3:0], ~WayExpanded[NUMWAYS-3:0], LRUUpdate[NUMWAYS-3:0], NextLRU[NUMWAYS-3:0]);
 
   // Compute next victim way.
-  for(s = NUMWAYS-2; s >= NUMWAYS/2; s--) begin
+  for(node = NUMWAYS-2; node >= NUMWAYS/2; node--) begin
-    localparam t0 = 2*s - NUMWAYS;
+    localparam t0 = 2*node - NUMWAYS;
     localparam t1 = t0 + 1;
-    assign Intermediate[s] = CurrLRU[s] ? Intermediate[t0] : Intermediate[t1];
+    assign Intermediate[node] = CurrLRU[node] ? Intermediate[t0] : Intermediate[t1];
   end
-  for(s = NUMWAYS/2-1; s >= 0; s--) begin
+  for(node = NUMWAYS/2-1; node >= 0; node--) begin
-    localparam int0 = (NUMWAYS/2-1-s)*2;
+    localparam int0 = (NUMWAYS/2-1-node)*2;
     localparam int1 = int0 + 1;
-    assign Intermediate[s] = CurrLRU[s] ? int1[LOGNUMWAYS-1:0] : int0[LOGNUMWAYS-1:0];
+    assign Intermediate[node] = CurrLRU[node] ? int1[LOGNUMWAYS-1:0] : int0[LOGNUMWAYS-1:0];
   end
 
   logic [NUMWAYS-1:0] FirstZero;
@@ -134,11 +143,9 @@ module cacheLRU
   always_ff @(posedge clk) begin
     if (reset) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0;
     if(CacheEn) begin
-      // if((InvalidateCache | FlushCache) & ~FlushStage) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0;
+      if(LRUWriteEn)
-      if (LRUWriteEn & ~FlushStage) begin 
         LRUMemory[PAdr] <= NextLRU;
-      end
+      if(LRUWriteEn & (PAdr == CacheSet))
-      if(LRUWriteEn & ~FlushStage & (PAdr == CacheSet))
         CurrLRU <= #1 NextLRU;
       else 
         CurrLRU <= #1 LRUMemory[CacheSet];

src/cache/cachefsm.sv

@@ -1,11 +1,11 @@
 ///////////////////////////////////////////
-// dcache (data cache) fsm
+// cachefsm.sv
 //
 // Written: Ross Thompson ross1728@gmail.com
 // Created: 25 August 2021
 // Modified: 20 January 2023
 //
-// Purpose: Controller for the dcache fsm
+// Purpose: Controller for the cache fsm
 //
 // Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.14 and Table 7.1)
 //
@@ -47,7 +47,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
   output logic [1:0] CacheBusRW,        // [1] Read (cache line fetch) or [0] write bus (cache line writeback)
   // performance counter outputs
   output logic       CacheMiss,         // Cache miss  
-  output logic       CacheAccess,    // Cache access
+  output logic       CacheAccess,       // Cache access
 
   // cache internals
   input  logic       CacheHit,          // Exactly 1 way hits
@@ -55,7 +55,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
   input  logic       FlushAdrFlag,      // On last set of a cache flush
   input  logic       FlushWayFlag,      // On the last way for any set of a cache flush
   output logic       SelAdr,            // [0] SRAM reads from NextAdr, [1] SRAM reads from PAdr
-  output logic       SetValid,          // Set the dirty bit in the selected way and set
+  output logic       SetValid,          // Set the valid bit in the selected way and set
   output logic       ClearDirty,        // Clear the dirty bit in the selected way and set
   output logic       SetDirty,          // Set the dirty bit in the selected way and set
   output logic       SelWriteback,      // Overrides cached tag check to select a specific way and set for writeback
@@ -69,7 +69,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
 );
   
   logic              resetDelay;
-  logic              AMO, StoreAMO;
+  logic              StoreAMO;
   logic              AnyUpdateHit, AnyHit;
   logic              AnyMiss;
   logic              FlushFlag;
@@ -86,16 +86,15 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
 
   statetype CurrState, NextState;
 
-  assign AMO = CacheAtomic[1] & (&CacheRW);
+  assign StoreAMO = CacheRW[0]; // AMO operations assert CacheRW[0]
-  assign StoreAMO = AMO | CacheRW[0];
 
-  assign AnyMiss = (StoreAMO | CacheRW[1]) & ~CacheHit & ~InvalidateCache;
+  assign AnyMiss = (StoreAMO | CacheRW[1]) & ~CacheHit & ~InvalidateCache; // exclusion-tag: cache AnyMiss
-  assign AnyUpdateHit = (StoreAMO) & CacheHit;
+  assign AnyUpdateHit = (StoreAMO) & CacheHit;                             // exclusion-tag: icache storeAMO1
-  assign AnyHit = AnyUpdateHit | (CacheRW[1] & CacheHit);  
+  assign AnyHit = AnyUpdateHit | (CacheRW[1] & CacheHit);                  // exclusion-tag: icache AnyUpdateHit
   assign FlushFlag = FlushAdrFlag & FlushWayFlag;
 
   // outputs for the performance counters.
-  assign CacheAccess = (AMO | CacheRW[1] | CacheRW[0]) & CurrState == STATE_READY;
+  assign CacheAccess = (|CacheRW) & CurrState == STATE_READY; // exclusion-tag: icache CacheW
   assign CacheMiss = CacheAccess & ~CacheHit;
 
   // special case on reset. When the fsm first exists reset the
@@ -109,17 +108,18 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
   
   always_comb begin
     NextState = STATE_READY;
-    case (CurrState)
+    case (CurrState)                                                                                        // exclusion-tag: icache state-case
-      STATE_READY:           if(InvalidateCache)                               NextState = STATE_READY;
+      STATE_READY:           if(InvalidateCache)                               NextState = STATE_READY;     // exclusion-tag: dcache InvalidateCheck
                              else if(FlushCache & ~READ_ONLY_CACHE)            NextState = STATE_FLUSH;
-                             else if(AnyMiss & (READ_ONLY_CACHE | ~LineDirty)) NextState = STATE_FETCH;
+                             else if(AnyMiss & (READ_ONLY_CACHE | ~LineDirty)) NextState = STATE_FETCH;     // exclusion-tag: icache FETCHStatement
-                             else if(AnyMiss & LineDirty)                      NextState = STATE_WRITEBACK;
+                             else if(AnyMiss) /* & LineDirty */                NextState = STATE_WRITEBACK; // exclusion-tag: icache WRITEBACKStatement
                              else                                              NextState = STATE_READY;
       STATE_FETCH:           if(CacheBusAck)                                   NextState = STATE_WRITE_LINE;
                              else                                              NextState = STATE_FETCH;
       STATE_WRITE_LINE:                                                        NextState = STATE_READ_HOLD;
       STATE_READ_HOLD:       if(Stall)                                         NextState = STATE_READ_HOLD;
                              else                                              NextState = STATE_READY;
+      // exclusion-tag-start: icache case
       STATE_WRITEBACK:       if(CacheBusAck)                                   NextState = STATE_FETCH;
                              else                                              NextState = STATE_WRITEBACK;
       // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack.
@@ -129,13 +129,14 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
       STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag)                      NextState = STATE_FLUSH;
                              else if(CacheBusAck)                              NextState = STATE_READ_HOLD;
                              else                                              NextState = STATE_FLUSH_WRITEBACK;
+      // exclusion-tag-end: icache case
       default:                                                                 NextState = STATE_READY;
     endcase
   end
 
   // com back to CPU
   assign CacheCommitted = (CurrState != STATE_READY) & ~(READ_ONLY_CACHE & CurrState == STATE_READ_HOLD);
-  assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) | 
+  assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) | // exclusion-tag: icache StallStates
                       (CurrState == STATE_FETCH) |
                       (CurrState == STATE_WRITEBACK) |
                       (CurrState == STATE_WRITE_LINE) |  // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write.
@@ -143,12 +144,14 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
                       (CurrState == STATE_FLUSH_WRITEBACK);
   // write enables internal to cache
   assign SetValid = CurrState == STATE_WRITE_LINE;
-  assign SetDirty = (CurrState == STATE_READY & AnyUpdateHit) |
+  // coverage off -item e 1 -fecexprrow 8
-                    (CurrState == STATE_WRITE_LINE & (StoreAMO));
-  assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(StoreAMO)) |
-                      (CurrState == STATE_FLUSH & LineDirty); // This is wrong in a multicore snoop cache protocal.  Dirty must be cleared concurrently and atomically with writeback.  For single core cannot clear after writeback on bus ack and change flushadr.  Clears the wrong set.
   assign LRUWriteEn = (CurrState == STATE_READY & AnyHit) |
-                      (CurrState == STATE_WRITE_LINE);
+                      (CurrState == STATE_WRITE_LINE) & ~FlushStage;
+  // exclusion-tag-start: icache flushdirtycontrols
+  assign SetDirty = (CurrState == STATE_READY & AnyUpdateHit) |         // exclusion-tag: icache SetDirty
+                    (CurrState == STATE_WRITE_LINE & (StoreAMO));
+  assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(StoreAMO)) |   // exclusion-tag: icache ClearDirty
+                      (CurrState == STATE_FLUSH & LineDirty); // This is wrong in a multicore snoop cache protocal.  Dirty must be cleared concurrently and atomically with writeback.  For single core cannot clear after writeback on bus ack and change flushadr.  Clears the wrong set.
   // Flush and eviction controls
   assign SelWriteback = (CurrState == STATE_WRITEBACK & ~CacheBusAck) |
                     (CurrState == STATE_READY & AnyMiss & LineDirty);
@@ -156,27 +159,29 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
   assign SelFlush = (CurrState == STATE_READY & FlushCache) |
           (CurrState == STATE_FLUSH) | 
           (CurrState == STATE_FLUSH_WRITEBACK);
+  // coverage off -item e -fecexprrow 1
+  // (state is always FLUSH_WRITEBACK when FlushWayFlag & CacheBusAck)
   assign FlushAdrCntEn = (CurrState == STATE_FLUSH_WRITEBACK & FlushWayFlag & CacheBusAck) |
              (CurrState == STATE_FLUSH & FlushWayFlag & ~LineDirty);
   assign FlushWayCntEn = (CurrState == STATE_FLUSH & ~LineDirty) |
              (CurrState == STATE_FLUSH_WRITEBACK & CacheBusAck);
   assign FlushCntRst = (CurrState == STATE_FLUSH & FlushFlag & ~LineDirty) |
               (CurrState == STATE_FLUSH_WRITEBACK & FlushFlag & CacheBusAck);
+  // exclusion-tag-end: icache flushdirtycontrols
   // Bus interface controls
-  assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) | 
+  assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) | // exclusion-tag: icache CacheBusRCauses
                          (CurrState == STATE_FETCH & ~CacheBusAck) | 
                          (CurrState == STATE_WRITEBACK & CacheBusAck);
-  assign CacheBusRW[0] = (CurrState == STATE_READY & AnyMiss & LineDirty) |
+  assign CacheBusRW[0] = (CurrState == STATE_READY & AnyMiss & LineDirty) | // exclusion-tag: icache CacheBusW
                           (CurrState == STATE_WRITEBACK & ~CacheBusAck) |
                      (CurrState == STATE_FLUSH_WRITEBACK & ~CacheBusAck);
 
-  assign SelAdr = (CurrState == STATE_READY & (StoreAMO | AnyMiss)) | // changes if store delay hazard removed
+  assign SelAdr = (CurrState == STATE_READY & (StoreAMO | AnyMiss)) | // exclusion-tag: icache SelAdrCauses // changes if store delay hazard removed
                   (CurrState == STATE_FETCH) |
                   (CurrState == STATE_WRITEBACK) |
                   (CurrState == STATE_WRITE_LINE) |
                   resetDelay;
-
   assign SelFetchBuffer = CurrState == STATE_WRITE_LINE | CurrState == STATE_READ_HOLD;
-  assign CacheEn = (~Stall | FlushCache | AnyMiss) | (CurrState != STATE_READY) | reset | InvalidateCache;
+  assign CacheEn = (~Stall | FlushCache | AnyMiss) | (CurrState != STATE_READY) | reset | InvalidateCache; // exclusion-tag: dcache CacheEn
                        
 endmodule // cachefsm

src/cache/cacheway.sv

@@ -35,7 +35,7 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
   input  logic                        reset,
   input  logic                        FlushStage,     // Pipeline flush of second stage (prevent writes and bus operations)
   input  logic                        CacheEn,        // Enable the cache memory arrays.  Disable hold read data constant
-  input  logic [$clog2(NUMLINES)-1:0] CacheSet,           // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
+  input  logic [$clog2(NUMLINES)-1:0] CacheSet,       // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
   input  logic [`PA_BITS-1:0]         PAdr,           // Physical address 
   input  logic [LINELEN-1:0]          LineWriteData,  // Final data written to cache (D$ only)
   input  logic                        SetValid,       // Set the valid bit in the selected way and set
@@ -45,14 +45,14 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
   input  logic                        SelFlush,       // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr
   input  logic                        VictimWay,      // LRU selected this way as victim to evict
   input  logic                        FlushWay,       // This way is selected for flush and possible writeback if dirty
-  input  logic                        InvalidateCache,//Clear all valid bits
+  input  logic                        InvalidateCache,// Clear all valid bits
   input  logic [LINELEN/8-1:0]        LineByteMask,   // Final byte enables to cache (D$ only)
 
   output logic [LINELEN-1:0]          ReadDataLineWay,// This way's read data if valid
   output logic                        HitWay,         // This way hits
   output logic                        ValidWay,       // This way is valid
   output logic                        DirtyWay,       // This way is dirty
-  output logic [TAGLEN-1:0]           TagWay);        // THis way's tag if valid
+  output logic [TAGLEN-1:0]           TagWay);        // This way's tag if valid
 
   localparam                          WORDSPERLINE = LINELEN/`XLEN;
   localparam                          BYTESPERLINE = LINELEN/8;
@@ -97,18 +97,13 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
   /////////////////////////////////////////////////////////////////////////////////////////////
 
   assign SetValidWay = SetValid & SelData;
+  assign SetDirtyWay = SetDirty & SelData;                                 // exclusion-tag: icache SetDirtyWay
   assign ClearDirtyWay = ClearDirty & SelData;
-  if (!READ_ONLY_CACHE) begin
+  assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage;  // exclusion-tag: icache SelectedWiteWordEn
-    assign SetDirtyWay = SetDirty & SelData;
+  assign SetValidEN = SetValidWay & ~FlushStage;                           // exclusion-tag: icache SetValidEN
-    assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage;
-  end
-  else begin
-    assign SelectedWriteWordEn = SetValidWay & ~FlushStage;
-  end
 
   // If writing the whole line set all write enables to 1, else only set the correct word.
   assign FinalByteMask = SetValidWay ? '1 : LineByteMask; // OR
-  assign SetValidEN = SetValidWay & ~FlushStage;
 
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Tag Array
@@ -160,7 +155,7 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
     if (reset) ValidBits        <= #1 '0;
     if(CacheEn) begin 
     ValidWay <= #1 ValidBits[CacheSet];
-    if(InvalidateCache)                    ValidBits <= #1 '0;
+    if(InvalidateCache)                    ValidBits <= #1 '0; // exclusion-tag: dcache invalidateway
       else if (SetValidEN) ValidBits[CacheSet] <= #1 SetValidWay;
     end
   end

src/cache/subcachelineread.sv

@@ -1,11 +1,11 @@
 ///////////////////////////////////////////
-// subcachelineread
+// subcachelineread.sv
 //
 // Written: Ross Thompson ross1728@gmail.com
 // Created: 4 February 2022
 // Modified: 20 January 2023
 //
-// Purpose: Muxes the cache line downto the word size.  Also include possilbe save/restore registers/muxes.
+// Purpose: Muxes the cache line down to the word size.  Also include possible save/restore registers/muxes.
 //
 // Documentation: RISC-V System on Chip Design Chapter 7
 
@@ -31,7 +31,6 @@
 
 module subcachelineread #(parameter LINELEN, WORDLEN, 
   parameter MUXINTERVAL )(     // The number of bits between mux. Set to 16 for I$ to support compressed.  Set to `LLEN for D$
-
   input  logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr,       // Physical address 
   input  logic [LINELEN-1:0]                     ReadDataLine,// Read data of the whole cacheline
   output logic [WORDLEN-1:0]                     ReadDataWord // read data of selected word.

src/ebu/ahbcacheinterface.sv

@@ -38,27 +38,27 @@ module ahbcacheinterface #(
 )(
   input  logic                HCLK, HRESETn,
   // bus interface controls
-  input logic                 HREADY,                  // AHB peripheral ready
+  input  logic                HREADY,                  // AHB peripheral ready
   output logic [1:0]          HTRANS,                  // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
   output logic                HWRITE,                  // AHB 0: Read operation 1: Write operation 
   output logic [2:0]          HSIZE,                   // AHB transaction width
   output logic [2:0]          HBURST,                  // AHB burst length
   // bus interface buses
-  input logic [`AHBW-1:0]     HRDATA,                  // AHB read data
+  input  logic [`AHBW-1:0]    HRDATA,                  // AHB read data
   output logic [`PA_BITS-1:0] HADDR,                   // AHB address
   output logic [`AHBW-1:0]    HWDATA,                  // AHB write data
   output logic [`AHBW/8-1:0]  HWSTRB,                  // AHB byte mask
   
   // cache interface
-  input logic [`PA_BITS-1:0]  CacheBusAdr,             // Address of cache line
+  input  logic [`PA_BITS-1:0] CacheBusAdr,            // Address of cache line
-  input logic [`LLEN-1:0]     CacheReadDataWordM,      // one word of cache line during a writeback
+  input  logic [`LLEN-1:0]    CacheReadDataWordM,     // One word of cache line during a writeback
-  input logic                 CacheableOrFlushCacheM,  // Memory operation is cacheable or flushing D$
+  input  logic                CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$
-  input logic                 Cacheable,               // Memory operation is cachable
+  input  logic                Cacheable,              // Memory operation is cachable
-  input logic [1:0]           CacheBusRW,              // Cache bus operation, 01: writeback, 10: fetch
+  input  logic [1:0]          CacheBusRW,             // Cache bus operation, 01: writeback, 10: fetch
-  output logic                CacheBusAck,             // Handshack to $ indicating bus transaction completed
+  output logic                CacheBusAck,            // Handshake to $ indicating bus transaction completed
-  output logic [LINELEN-1:0]  FetchBuffer,             // Register to hold beats of cache line as the arrive from bus
+  output logic [LINELEN-1:0]  FetchBuffer,            // Register to hold beats of cache line as the arrive from bus
-  output logic [AHBWLOGBWPL-1:0] BeatCount,               // Beat position within the cache line in the Address Phase
+  output logic [AHBWLOGBWPL-1:0] BeatCount,           // Beat position within the cache line in the Address Phase
-  output logic                SelBusBeat,              // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr
+  output logic                SelBusBeat,             // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr
 
   // uncached interface 
   input logic [`PA_BITS-1:0]  PAdr,                    // Physical address of uncached memory operation
@@ -77,7 +77,7 @@ module ahbcacheinterface #(
   logic [`PA_BITS-1:0]        LocalHADDR;                             // Address after selecting between cached and uncached operation
   logic [AHBWLOGBWPL-1:0]     BeatCountDelayed;                       // Beat within the cache line in the second (Data) cache stage
   logic                       CaptureEn;                              // Enable updating the Fetch buffer with valid data from HRDATA
-  logic [`AHBW/8-1:0]         BusByteMaskM;                           // Byte enables within a word.  For cache request all 1s
+  logic [`AHBW/8-1:0]         BusByteMaskM;                           // Byte enables within a word. For cache request all 1s
   logic [`AHBW-1:0]           PreHWDATA;                              // AHB Address phase write data
 
   genvar                      index;
@@ -107,7 +107,7 @@ module ahbcacheinterface #(
   end else assign CacheReadDataWordAHB = CacheReadDataWordM[`AHBW-1:0];      
   
   mux2 #(`AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[`AHBW-1:0]),
-     .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA));
+    .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA));
   flopen #(`AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec
 
   // *** bummer need a second byte mask for bus as it is AHBW rather than LLEN.
@@ -119,5 +119,5 @@ module ahbcacheinterface #(
   buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE) AHBBuscachefsm(
     .HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat,
     .CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed,
-      .HREADY, .HTRANS, .HWRITE, .HBURST);
+    .HREADY, .HTRANS, .HWRITE, .HBURST);
 endmodule

src/ebu/ahbinterface.sv

@@ -32,21 +32,21 @@
 module ahbinterface #(
   parameter LSU = 0                                   // 1: LSU bus width is `XLEN, 0: IFU bus width is 32 bits
 )( 
-  input logic                           HCLK, HRESETn,
+  input  logic                          HCLK, HRESETn,
   // bus interface
-  input logic                           HREADY,       // AHB peripheral ready
+  input  logic                          HREADY,       // AHB peripheral ready
   output logic [1:0]                    HTRANS,       // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
   output logic                          HWRITE,       // AHB 0: Read operation 1: Write operation 
-  input logic [`XLEN-1:0]               HRDATA,       // AHB read data
+  input  logic [`XLEN-1:0]              HRDATA,       // AHB read data
   output logic [`XLEN-1:0]              HWDATA,       // AHB write data
   output logic [`XLEN/8-1:0]            HWSTRB,       // AHB byte mask
   
   // lsu/ifu interface
-  input logic                           Stall,        // Core pipeline is stalled
+  input  logic                          Stall,        // Core pipeline is stalled
-  input logic                           Flush,        // Pipeline stage flush. Prevents bus transaction from starting
+  input  logic                          Flush,        // Pipeline stage flush. Prevents bus transaction from starting
-  input logic [1:0]                     BusRW,        // Memory operation read/write control: 10: read, 01: write
+  input  logic [1:0]                    BusRW,        // Memory operation read/write control: 10: read, 01: write
-  input logic [`XLEN/8-1:0]             ByteMask,     // Bytes enables within a word
+  input  logic [`XLEN/8-1:0]            ByteMask,     // Bytes enables within a word
-  input logic [`XLEN-1:0]               WriteData,    // IEU write data for a store
+  input  logic [`XLEN-1:0]              WriteData,    // IEU write data for a store
   output logic                          BusStall,     // Bus is busy with an in flight memory operation
   output logic                          BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
   output logic [(LSU ? `XLEN : 32)-1:0] FetchBuffer   // Register to hold HRDATA after arriving from the bus

src/ebu/buscachefsm.sv

@@ -40,29 +40,29 @@ module buscachefsm #(
   input  logic                   HRESETn,
 
   // IEU interface
-  input  logic                   Stall,                   // Core pipeline is stalled
+  input  logic                   Stall,              // Core pipeline is stalled
-  input  logic                   Flush,                   // Pipeline stage flush. Prevents bus transaction from starting
+  input  logic                   Flush,              // Pipeline stage flush. Prevents bus transaction from starting
-  input  logic [1:0]             BusRW,                   // Uncached memory operation read/write control: 10: read, 01: write
+  input  logic [1:0]             BusRW,              // Uncached memory operation read/write control: 10: read, 01: write
-  output logic                   BusStall,                // Bus is busy with an in flight memory operation
+  output logic                   BusStall,           // Bus is busy with an in flight memory operation
-  output logic                   BusCommitted,            // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
+  output logic                   BusCommitted,       // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
                             
   // ahb cache interface locals.            
-  output logic                   CaptureEn,               // Enable updating the Fetch buffer with valid data from HRDATA
+  output logic                   CaptureEn,          // Enable updating the Fetch buffer with valid data from HRDATA
                             
   // cache interface                  
-  input  logic [1:0]             CacheBusRW,              // Cache bus operation, 01: writeback, 10: fetch
+  input  logic [1:0]             CacheBusRW,         // Cache bus operation, 01: writeback, 10: fetch
-  output logic                   CacheBusAck,             // Handshack to $ indicating bus transaction completed
+  output logic                   CacheBusAck,        // Handshack to $ indicating bus transaction completed
   
   // lsu interface
   output logic [AHBWLOGBWPL-1:0] BeatCount,          // Beat position within the cache line in the Address Phase
   output logic [AHBWLOGBWPL-1:0] BeatCountDelayed,   // Beat within the cache line in the second (Data) cache stage
-  output logic                   SelBusBeat,              // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr
+  output logic                   SelBusBeat,         // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr
 
   // BUS interface
-  input  logic                   HREADY,                  // AHB peripheral ready
+  input  logic                   HREADY,             // AHB peripheral ready
-  output logic [1:0]             HTRANS,                  // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
+  output logic [1:0]             HTRANS,             // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
-  output logic                   HWRITE,                  // AHB 0: Read operation 1: Write operation 
+  output logic                   HWRITE,             // AHB 0: Read operation 1: Write operation 
-  output logic [2:0]             HBURST                   // AHB burst length
+  output logic [2:0]             HBURST              // AHB burst length
 );
   
   typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3, CACHE_FETCH, CACHE_WRITEBACK}               busstatetype;
@@ -78,8 +78,8 @@ module buscachefsm #(
   logic                   CacheAccess;
   
   always_ff @(posedge HCLK)
-    if (~HRESETn | Flush)    CurrState <= #1 ADR_PHASE;
+    if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE;
-    else CurrState <= #1 NextState;  
+    else                  CurrState <= #1 NextState;  
   
   always_comb begin
       case(CurrState)

src/ebu/controllerinput.sv

@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// controller input stage
+// controllerinput.sv
 //
 // Written: Ross Thompson ross1728@gmail.com
 // Created:  August 31, 2022
@@ -36,26 +36,26 @@
 module controllerinput #(
   parameter SAVE_ENABLED = 1           // 1: Save manager inputs if Save = 1, 0: Don't save inputs
 )(
-  input logic                 HCLK, 
+  input  logic                HCLK, 
-  input logic                 HRESETn,
+  input  logic                HRESETn,
-  input logic                 Save,     // Two or more managers requesting (HTRANS != 00) at the same time.  Save the non-granted manager inputs
+  input  logic                Save,     // Two or more managers requesting (HTRANS != 00) at the same time.  Save the non-granted manager inputs
-  input logic                 Restore,  // Restore a saved manager inputs when it is finally granted
+  input  logic                Restore,  // Restore a saved manager inputs when it is finally granted
-  input logic                 Disable,  // Supress HREADY to the non-granted manager
+  input  logic                Disable,  // Suppress HREADY to the non-granted manager
   output logic                Request,  // This manager is making a request
   // controller input
-  input logic [1:0]           HTRANSIn,  // Manager input. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
+  input  logic [1:0]          HTRANSIn,  // Manager input. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
-  input logic                 HWRITEIn,  // Manager input. AHB 0: Read operation 1: Write operation 
+  input  logic                HWRITEIn,  // Manager input. AHB 0: Read operation 1: Write operation 
-  input logic [2:0]           HSIZEIn,   // Manager input. AHB transaction width
+  input  logic [2:0]          HSIZEIn,   // Manager input. AHB transaction width
-  input logic [2:0]           HBURSTIn,  // Manager input. AHB burst length
+  input  logic [2:0]          HBURSTIn,  // Manager input. AHB burst length
-  input logic [`PA_BITS-1:0]  HADDRIn,   // Manager input. AHB address
+  input  logic [`PA_BITS-1:0] HADDRIn,   // Manager input. AHB address
-  output logic                HREADYOut, // Indicate to manager the peripherial is not busy and another manager does not have priority
+  output logic                HREADYOut, // Indicate to manager the peripheral is not busy and another manager does not have priority
   // controller output
-  output logic [1:0]          HTRANSOut, // Aribrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
+  output logic [1:0]          HTRANSOut, // Arbitrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ
-  output logic                HWRITEOut, // Aribrated manager transaction. AHB 0: Read operation 1: Write operation 
+  output logic                HWRITEOut, // Arbitrated manager transaction. AHB 0: Read operation 1: Write operation 
-  output logic [2:0]          HSIZEOut,  // Aribrated manager transaction. AHB transaction width
+  output logic [2:0]          HSIZEOut,  // Arbitrated manager transaction. AHB transaction width
-  output logic [2:0]          HBURSTOut, // Aribrated manager transaction. AHB burst length 
+  output logic [2:0]          HBURSTOut, // Arbitrated manager transaction. AHB burst length 
-  output logic [`PA_BITS-1:0] HADDROut,  // Aribrated manager transaction. AHB address
+  output logic [`PA_BITS-1:0] HADDROut,  // Arbitrated manager transaction. AHB address
-  input logic                 HREADYIn   // Peripherial ready
+  input  logic                HREADYIn   // Peripheral ready
 );
 
   logic                       HWRITESave;

src/ebu/ebufsmarb.sv

@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// ebufsmarb
+// ebufsmarb.sv
 //
 // Written: Ross Thompson ross1728@gmail.com
 // Created: 23 January 2023
@@ -55,7 +55,7 @@ module ebufsmarb (
   logic              IFUReqD;                    // 1 cycle delayed IFU request. Part of arbitration
   logic              FinalBeat, FinalBeatD;      // Indicates the last beat of a burst
   logic              BeatCntEn;
-  logic [3:0]        BeatCount;   // Position within a burst transfer
+  logic [3:0]        BeatCount;                  // Position within a burst transfer
   logic              BeatCntReset;
   logic [3:0]        Threshold;                  // Number of beats derived from HBURST
 
@@ -86,7 +86,7 @@ module ebufsmarb (
   // Controller 1 (LSU)
   // When both the IFU and LSU request at the same time, the FSM will go into the arbitrate state.
   // Once the LSU request is done the fsm returns to IDLE.  To prevent the LSU from regaining
-  // priority and re issuing the same memroy operation, the delayed IFUReqD squashes the LSU request.
+  // priority and re-issuing the same memory operation, the delayed IFUReqD squashes the LSU request.
   // This is necessary because the pipeline is stalled for the entire duration of both transactions,
   // and the LSU memory request will stil be active.
   flopr #(1) ifureqreg(HCLK, ~HRESETn, IFUReq, IFUReqD);

src/fpu/fcmp.sv

@@ -71,11 +71,11 @@ module fcmp (
   //    EQ - quiet - sets invalid if signaling NaN input
   always_comb begin
     case (OpCtrl[2:0])
-        3'b110: CmpNV = EitherSNaN;//min 
+        3'b110: CmpNV = EitherSNaN; //min 
-        3'b101: CmpNV = EitherSNaN;//max
+        3'b101: CmpNV = EitherSNaN; //max
-        3'b010: CmpNV = EitherSNaN;//equal
+        3'b010: CmpNV = EitherSNaN; //equal
-        3'b001: CmpNV = EitherNaN;//less than
+        3'b001: CmpNV = EitherNaN;  //less than
-        3'b011: CmpNV = EitherNaN;//less than or equal
+        3'b011: CmpNV = EitherNaN;  //less than or equal
         default: CmpNV = 1'bx;
     endcase
   end 
@@ -137,19 +137,19 @@ module fcmp (
           if(YNaN)    CmpFpRes = NaNRes;   // X = NaN Y = NaN
           else        CmpFpRes = Y;        // X = NaN Y != NaN
         else
-          if(YNaN)    CmpFpRes = X; // X != NaN Y = NaN
+          if(YNaN)    CmpFpRes = X;        // X != NaN Y = NaN
           else // X,Y != NaN
-              if(LT)   CmpFpRes = Y; // X < Y
+              if(LT)  CmpFpRes = Y;        // X < Y
-              else     CmpFpRes = X; // X > Y
+              else    CmpFpRes = X;        // X > Y
     else  // MIN
         if(XNaN)
           if(YNaN)    CmpFpRes = NaNRes;   // X = NaN Y = NaN
           else        CmpFpRes = Y;        // X = NaN Y != NaN
         else
-          if(YNaN)    CmpFpRes = X; // X != NaN Y = NaN
+          if(YNaN)    CmpFpRes = X;        // X != NaN Y = NaN
           else // X,Y != NaN
-              if(LT)   CmpFpRes = X; // X < Y
+              if(LT)  CmpFpRes = X;        // X < Y
-              else     CmpFpRes = Y; // X > Y
+              else    CmpFpRes = Y;        // X > Y
                                   
   // LT/LE/EQ
   //    - -0 = 0

src/fpu/fctrl.sv

@@ -93,24 +93,24 @@ module fctrl (
   // FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr_FCvtInt
   always_comb
     if (STATUS_FS == 2'b00) // FPU instructions are illegal when FPU is disabled
-      ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0;
+      ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0;
     else if (OpD != 7'b0000111 & OpD != 7'b0100111 & ~SupportedFmt) 
-      ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // for anything other than loads and stores, check for supported format
+      ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0; // for anything other than loads and stores, check for supported format
     else begin 
-      ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // default: non-implemented instruction
+      ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0; // default: non-implemented instruction
       /* verilator lint_off CASEINCOMPLETE */ // default value above has priority so no other default needed
       case(OpD)
         7'b0000111: case(Funct3D)
-                      3'b010:                      ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flw
+                      3'b010:                      ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flw
-                      3'b011:  if (`D_SUPPORTED)   ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // fld
+                      3'b011:  if (`D_SUPPORTED)   ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // fld
-                      3'b100:  if (`Q_SUPPORTED)   ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flq
+                      3'b100:  if (`Q_SUPPORTED)   ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flq
-                      3'b001:  if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flh
+                      3'b001:  if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flh
                     endcase
         7'b0100111: case(Funct3D)
-                      3'b010:                      ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsw
+                      3'b010:                      ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsw
-                      3'b011:  if (`D_SUPPORTED)   ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsd
+                      3'b011:  if (`D_SUPPORTED)   ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsd
-                      3'b100:  if (`Q_SUPPORTED)   ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsq
+                      3'b100:  if (`Q_SUPPORTED)   ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsq
-                      3'b001:  if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsh
+                      3'b001:  if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsh
                     endcase
         7'b1000011:   ControlsD = `FCTRLW'b1_0_01_10_000_0_0_0; // fmadd
         7'b1000111:   ControlsD = `FCTRLW'b1_0_01_10_001_0_0_0; // fmsub
@@ -123,25 +123,25 @@ module fctrl (
                       7'b00011??: ControlsD = `FCTRLW'b1_0_01_01_xx0_1_0_0; // fdiv
                       7'b01011??: if (Rs2D == 5'b0000) ControlsD = `FCTRLW'b1_0_01_01_xx1_1_0_0; // fsqrt
                       7'b00100??: case(Funct3D)
-                                    3'b000:  ControlsD = `FCTRLW'b1_0_00_xx_000_0_0_0; // fsgnj
+                                    3'b000:  ControlsD = `FCTRLW'b1_0_00_00_000_0_0_0; // fsgnj
-                                    3'b001:  ControlsD = `FCTRLW'b1_0_00_xx_001_0_0_0; // fsgnjn
+                                    3'b001:  ControlsD = `FCTRLW'b1_0_00_00_001_0_0_0; // fsgnjn
-                                    3'b010:  ControlsD = `FCTRLW'b1_0_00_xx_010_0_0_0; // fsgnjx
+                                    3'b010:  ControlsD = `FCTRLW'b1_0_00_00_010_0_0_0; // fsgnjx
                                   endcase
                       7'b00101??: case(Funct3D)
-                                    3'b000:  ControlsD = `FCTRLW'b1_0_00_xx_110_0_0_0; // fmin
+                                    3'b000:  ControlsD = `FCTRLW'b1_0_00_00_110_0_0_0; // fmin
-                                    3'b001:  ControlsD = `FCTRLW'b1_0_00_xx_101_0_0_0; // fmax
+                                    3'b001:  ControlsD = `FCTRLW'b1_0_00_00_101_0_0_0; // fmax
                                   endcase
                       7'b10100??: case(Funct3D)
-                                    3'b010:  ControlsD = `FCTRLW'b0_1_00_xx_010_0_0_0; // feq
+                                    3'b010:  ControlsD = `FCTRLW'b0_1_00_00_010_0_0_0; // feq
-                                    3'b001:  ControlsD = `FCTRLW'b0_1_00_xx_001_0_0_0; // flt
+                                    3'b001:  ControlsD = `FCTRLW'b0_1_00_00_001_0_0_0; // flt
-                                    3'b000:  ControlsD = `FCTRLW'b0_1_00_xx_011_0_0_0; // fle
+                                    3'b000:  ControlsD = `FCTRLW'b0_1_00_00_011_0_0_0; // fle
                                   endcase
                       7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000)          
-                                                ControlsD = `FCTRLW'b0_1_10_xx_000_0_0_0; // fclass
+                                                ControlsD = `FCTRLW'b0_1_10_00_000_0_0_0; // fclass
                                   else if (Funct3D == 3'b000 & Rs2D == 5'b00000) 
-                                                ControlsD = `FCTRLW'b0_1_11_xx_000_0_0_0; // fmv.x.w / fmv.x.d to int register
+                                                ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0; // fmv.x.w / fmv.x.d to int register
                       7'b111100?: if (Funct3D == 3'b000 & Rs2D == 5'b00000) 
-                                                ControlsD = `FCTRLW'b1_0_00_xx_011_0_0_0; // fmv.w.x / fmv.d.x   to fp reg
+                                                ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0; // fmv.w.x / fmv.d.x   to fp reg
                       7'b0100000: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b00)
                                                 ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.(d/q/h)
                       7'b0100001: if (Rs2D[4:2] == 3'b000  & SupportedFmt2 & Rs2D[1:0] != 2'b01)
@@ -242,17 +242,20 @@ module fctrl (
   
   //    X - all except int->fp, store, load, mv int->fp
   assign XEnD = ~(((FResSelD==2'b10)&~FWriteIntD)|                                                 // load/store
-                  ((FResSelD==2'b11)&FRegWriteD)|                                                  // mv int to float
+                  ((FResSelD==2'b00)&FRegWriteD&(OpCtrlD==3'b011))|                                // mv int to float
                   ((FResSelD==2'b01)&(PostProcSelD==2'b00)&OpCtrlD[2]));                           // cvt int to float
 
   //    Y - all except cvt, mv, load, class, sqrt
-  assign YEnD = ~(((FResSelD==2'b10)&(FWriteIntD|FRegWriteD))|                                     // load or class
+  assign YEnD = ~(((FResSelD==2'b10)&(FWriteIntD|FRegWriteD))|                                     // load or class 
-                  (FResSelD==2'b11)|                                                               // mv both ways
+                  ((FResSelD==2'b00)&FRegWriteD&(OpCtrlD==3'b011))|                                // mv int to float as above
+                  ((FResSelD==2'b11)&(PostProcSelD==2'b00))|                                       // mv float to int 
                   ((FResSelD==2'b01)&((PostProcSelD==2'b00)|((PostProcSelD==2'b01)&OpCtrlD[0])))); // cvt both or sqrt
 
+
+
   //    Z - fma ops only
-  assign ZEnD = (PostProcSelD==2'b10)&(FResSelD==2'b01)&(~OpCtrlD[2]|OpCtrlD[1]);                  // fma, add, sub
+  assign ZEnD = (PostProcSelD==2'b10)&(~OpCtrlD[2]|OpCtrlD[1]);                                    // fma, add, sub   
-  
+
 
   //  Final Res Sel:
   //        fp      int

src/fpu/fdivsqrt/fdivsqrt.sv

@@ -57,43 +57,43 @@ module fdivsqrt(
 
   logic [`DIVb+3:0]           WS, WC;                       // Partial remainder components
   logic [`DIVb+3:0]           X;                            // Iterator Initial Value (from dividend)
-  logic [`DIVb-1:0]           DPreproc, D;                  // Iterator Divisor
+  logic [`DIVb+3:0]           D;                            // Iterator Divisor
   logic [`DIVb:0]             FirstU, FirstUM;              // Intermediate result values
   logic [`DIVb+1:0]           FirstC;                       // Step tracker
   logic                       Firstun;                      // Quotient selection
   logic                       WZeroE;                       // Early termination flag
+  logic [`DURLEN-1:0]         cycles;                       // FSM cycles
   logic                       SpecialCaseM;                 // Divide by zero, square root of negative, etc.
   logic                       DivStartE;                    // Enable signal for flops during stall
                                                             
   // Integer div/rem signals                                
   logic                       BZeroM;                       // Denominator is zero
   logic                       IntDivM;                      // Integer operation
-  logic [`DIVBLEN:0]          nE, nM, mM;                   // Shift amounts
+  logic [`DIVBLEN:0]          nM, mM;                       // Shift amounts
   logic                       NegQuotM, ALTBM, AsM, W64M;   // Special handling for postprocessor
   logic [`XLEN-1:0]           AM;                           // Original Numerator for postprocessor
   logic                       ISpecialCaseE;                // Integer div/remainder special cases
 
-  fdivsqrtpreproc fdivsqrtpreproc(                        // Preprocessor
+  fdivsqrtpreproc fdivsqrtpreproc(                          // Preprocessor
-    .clk, .IFDivStartE, .Xm(XmE), .Ym(YmE), .Xe(XeE), .Ye(YeE), 
+    .clk, .IFDivStartE, .Xm(XmE), .Ym(YmE), .Xe(XeE), .Ye(YeE),
-    .Fmt(FmtE), .Sqrt(SqrtE), .XZeroE, .Funct3E, 
+    .FmtE, .SqrtE, .XZeroE, .Funct3E, .QeM, .X, .D, .cycles,
-    .QeM, .X, .DPreproc, 
     // Int-specific 
     .ForwardedSrcAE, .ForwardedSrcBE, .IntDivE, .W64E, .ISpecialCaseE,
-    .nE, .BZeroM, .nM, .mM, .AM, 
+    .BZeroM, .nM, .mM, .AM, 
     .IntDivM, .W64M, .NegQuotM, .ALTBM, .AsM);
 
-  fdivsqrtfsm fdivsqrtfsm(                                // FSM
+  fdivsqrtfsm fdivsqrtfsm(                                  // FSM
-    .clk, .reset, .FmtE, .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, 
+    .clk, .reset, .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, 
     .FDivStartE, .XsE, .SqrtE, .WZeroE, .FlushE, .StallM, 
-    .FDivBusyE, .IFDivStartE, .FDivDoneE, .SpecialCaseM, 
+    .FDivBusyE, .IFDivStartE, .FDivDoneE, .SpecialCaseM, .cycles,
     // Int-specific 
-    .IDivStartE, .ISpecialCaseE, .nE, .IntDivE);
+    .IDivStartE, .ISpecialCaseE, .IntDivE);
 
-  fdivsqrtiter fdivsqrtiter(                              // CSA Iterator
+  fdivsqrtiter fdivsqrtiter(                                // CSA Iterator
-    .clk, .IFDivStartE, .FDivBusyE, .SqrtE, .X, .DPreproc, 
+    .clk, .IFDivStartE, .FDivBusyE, .SqrtE, .X, .D, 
-    .D, .FirstU, .FirstUM, .FirstC, .Firstun, .FirstWS(WS), .FirstWC(WC));
+    .FirstU, .FirstUM, .FirstC, .Firstun, .FirstWS(WS), .FirstWC(WC));
 
-  fdivsqrtpostproc fdivsqrtpostproc(                      // Postprocessor
+  fdivsqrtpostproc fdivsqrtpostproc(                        // Postprocessor
     .clk, .reset, .StallM, .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, 
     .SqrtE, .Firstun, .SqrtM, .SpecialCaseM, 
     .QmM, .WZeroE, .DivStickyM, 

src/fpu/fdivsqrt/fdivsqrtcycles.sv

@@ -0,0 +1,76 @@
+///////////////////////////////////////////
+// fdivsqrt.sv
+//
+// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu, amaiuolo@hmc.edu
+// Modified: 18 April 2022
+//
+// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
+// 
+// Documentation: RISC-V System on Chip Design Chapter 13
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module fdivsqrtcycles(
+  input  logic [`FMTBITS-1:0] FmtE,
+  input  logic                SqrtE,
+  input  logic                IntDivE,
+  input  logic [`DIVBLEN:0]   nE,
+  output logic [`DURLEN-1:0]  cycles
+);
+  logic [`DURLEN+1:0] Nf, fbits; // number of fractional bits
+  // DIVN = `NF+3
+  // NS = NF + 1
+  // N = NS or NS+2 for div/sqrt.
+
+  /* verilator lint_off WIDTH */
+  if (`FPSIZES == 1)
+    assign Nf = `NF;
+  else if (`FPSIZES == 2)
+    always_comb
+      case (FmtE)
+        1'b0: Nf = `NF1;
+        1'b1: Nf = `NF;
+      endcase
+  else if (`FPSIZES == 3)
+    always_comb
+      case (FmtE)
+        `FMT:  Nf = `NF;
+        `FMT1: Nf = `NF1;
+        `FMT2: Nf = `NF2; 
+      endcase
+  else if (`FPSIZES == 4)  
+    always_comb
+      case(FmtE)
+        `S_FMT: Nf = `S_NF;
+        `D_FMT: Nf = `D_NF;
+        `H_FMT: Nf = `H_NF;
+        `Q_FMT: Nf = `Q_NF;
+      endcase 
+
+  always_comb begin 
+    if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2
+    else       fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
+    if (`IDIV_ON_FPU) cycles =  IntDivE ? ((nE + 1)/`DIVCOPIES) : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
+    else              cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
+  end 
+  /* verilator lint_on WIDTH */
+
+endmodule

src/fpu/fdivsqrt/fdivsqrtexpcalc.sv

@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// fdivsqrtpreproc.sv
+// fdivsqrtexpcalc.sv
 //
 // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
 // Modified:13 January 2022
@@ -30,11 +30,11 @@
 
 module fdivsqrtexpcalc(
   input  logic [`FMTBITS-1:0] Fmt,
-  input  logic [`NE-1:0] Xe, Ye,
+  input  logic [`NE-1:0]      Xe, Ye,
-  input  logic Sqrt,
+  input  logic                Sqrt,
-  input  logic XZero, 
+  input  logic                XZero, 
-  input  logic [`DIVBLEN:0] ell, m,
+  input  logic [`DIVBLEN:0]   ell, m,
-  output logic [`NE+1:0] Qe
+  output logic [`NE+1:0]      Qe
   );
   logic [`NE-2:0] Bias;
   logic [`NE+1:0] SXExp;
@@ -42,28 +42,28 @@ module fdivsqrtexpcalc(
   logic [`NE+1:0] DExp;
   
   if (`FPSIZES == 1) begin
-      assign Bias = (`NE-1)'(`BIAS); 
+    assign Bias = (`NE-1)'(`BIAS); 
 
   end else if (`FPSIZES == 2) begin
-      assign Bias = Fmt ? (`NE-1)'(`BIAS) : (`NE-1)'(`BIAS1); 
+    assign Bias = Fmt ? (`NE-1)'(`BIAS) : (`NE-1)'(`BIAS1); 
 
   end else if (`FPSIZES == 3) begin
-      always_comb
+    always_comb
-          case (Fmt)
+      case (Fmt)
-              `FMT: Bias  =  (`NE-1)'(`BIAS);
+        `FMT: Bias  =  (`NE-1)'(`BIAS);
-              `FMT1: Bias = (`NE-1)'(`BIAS1);
+        `FMT1: Bias = (`NE-1)'(`BIAS1);
-              `FMT2: Bias = (`NE-1)'(`BIAS2);
+        `FMT2: Bias = (`NE-1)'(`BIAS2);
-              default: Bias = 'x;
+        default: Bias = 'x;
-          endcase
+      endcase
 
   end else if (`FPSIZES == 4) begin        
-    always_comb
+  always_comb
-        case (Fmt)
+    case (Fmt)
-            2'h3: Bias =  (`NE-1)'(`Q_BIAS);
+      2'h3: Bias =  (`NE-1)'(`Q_BIAS);
-            2'h1: Bias =  (`NE-1)'(`D_BIAS);
+      2'h1: Bias =  (`NE-1)'(`D_BIAS);
-            2'h0: Bias =  (`NE-1)'(`S_BIAS);
+      2'h0: Bias =  (`NE-1)'(`S_BIAS);
-            2'h2: Bias =  (`NE-1)'(`H_BIAS);
+      2'h2: Bias =  (`NE-1)'(`H_BIAS);
-        endcase
+    endcase
   end
   assign SXExp = {2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - (`NE+2)'(`BIAS);
   assign SExp  = {SXExp[`NE+1], SXExp[`NE+1:1]} + {2'b0, Bias};

src/fpu/fdivsqrt/fdivsqrtfgen2.sv

@@ -29,7 +29,7 @@
 `include "wally-config.vh"
 
 module fdivsqrtfgen2 (
-  input  logic up, uz,
+  input  logic             up, uz,
   input  logic [`DIVb+3:0] C, U, UM,
   output logic [`DIVb+3:0] F
 );

src/fpu/fdivsqrt/fdivsqrtfgen4.sv

@@ -29,7 +29,7 @@
 `include "wally-config.vh"
 
 module fdivsqrtfgen4 (
-  input  logic [3:0] udigit,
+  input  logic [3:0]       udigit,
   input  logic [`DIVb+3:0] C, U, UM,
   output logic [`DIVb+3:0] F
 );

src/fpu/fdivsqrt/fdivsqrtfsm.sv

@@ -29,32 +29,27 @@
 `include "wally-config.vh"
 
 module fdivsqrtfsm(
-  input  logic clk, 
+  input  logic               clk, reset, 
-  input  logic reset, 
+  input  logic               XInfE, YInfE, 
-  input  logic [`FMTBITS-1:0] FmtE,
+  input  logic               XZeroE, YZeroE, 
-  input  logic XInfE, YInfE, 
+  input  logic               XNaNE, YNaNE, 
-  input  logic XZeroE, YZeroE, 
+  input  logic               FDivStartE, IDivStartE,
-  input  logic XNaNE, YNaNE, 
+  input  logic               XsE, WZeroE,
-  input  logic FDivStartE, IDivStartE,
+  input  logic               SqrtE,
-  input  logic XsE,
+  input  logic               StallM, FlushE,
-  input  logic SqrtE,
+  input  logic               IntDivE,
-  input  logic StallM,
+  input  logic               ISpecialCaseE,
-  input  logic FlushE,
+  input  logic [`DURLEN-1:0] cycles,
-  input  logic WZeroE,
+  output logic               IFDivStartE,
-  input  logic IntDivE,
+  output logic               FDivBusyE, FDivDoneE,
-  input  logic [`DIVBLEN:0] nE,
+  output logic               SpecialCaseM
-  input  logic ISpecialCaseE,
-  output logic IFDivStartE,
-  output logic FDivBusyE, FDivDoneE,
-  output logic SpecialCaseM
 );
   
   typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype;
   statetype state;
 
-  logic [`DURLEN-1:0] step;
-  logic [`DURLEN-1:0] cycles;
   logic SpecialCaseE, FSpecialCaseE;
+  logic [`DURLEN-1:0] step;
 
   // FDivStartE and IDivStartE come from fctrl, reflecitng the start of floating-point and possibly integer division
   assign IFDivStartE = (FDivStartE | (IDivStartE & `IDIV_ON_FPU)) & (state == IDLE) & ~StallM;
@@ -67,50 +62,11 @@ module fdivsqrtfsm(
   else              assign SpecialCaseE = FSpecialCaseE;
   flopenr #(1) SpecialCaseReg(clk, reset, IFDivStartE, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc
 
-// DIVN = `NF+3
-// NS = NF + 1
-// N = NS or NS+2 for div/sqrt.  
-
-/* verilator lint_off WIDTH */
-  logic [`DURLEN+1:0] Nf, fbits; // number of fractional bits
-  if (`FPSIZES == 1)
-    assign Nf = `NF;
-  else if (`FPSIZES == 2)
-    always_comb
-      case (FmtE)
-        1'b0: Nf = `NF1;
-        1'b1: Nf = `NF;
-      endcase
-  else if (`FPSIZES == 3)
-    always_comb
-      case (FmtE)
-        `FMT: Nf = `NF;
-        `FMT1: Nf = `NF1;
-        `FMT2: Nf = `NF2; 
-      endcase
-  else if (`FPSIZES == 4)  
-    always_comb
-      case(FmtE)
-        `S_FMT: Nf = `S_NF;
-        `D_FMT: Nf = `D_NF;
-        `H_FMT: Nf = `H_NF;
-        `Q_FMT: Nf = `Q_NF;
-      endcase 
-
-
-  always_comb begin 
-    if (SqrtE) fbits = Nf + 2 + 2; // Nf + two fractional bits for round/guard + 2 for right shift by up to 2
-    else       fbits = Nf + 2 + `LOGR; // Nf + two fractional bits for round/guard + integer bits - try this when placing results in msbs
-    if (`IDIV_ON_FPU) cycles =  IntDivE ? ((nE + 1)/`DIVCOPIES) : (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
-    else              cycles = (fbits + (`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES);
-  end 
-
-  /* verilator lint_on WIDTH */
-
   always_ff @(posedge clk) begin
       if (reset | FlushE) begin
           state <= #1 IDLE; 
-      end else if (IFDivStartE) begin 
+      end else if (IFDivStartE) begin // IFDivStartE implies stat is IDLE
+//       end else if ((state == IDLE) & IFDivStartE) begin // IFDivStartE implies stat is IDLE
           step <= cycles; 
           if (SpecialCaseE) state <= #1 DONE;
           else              state <= #1 BUSY;

src/fpu/fdivsqrt/fdivsqrtiter.sv

@@ -29,13 +29,11 @@
 `include "wally-config.vh"
 
 module fdivsqrtiter(
-  input  logic clk,
+  input  logic             clk,
-  input  logic IFDivStartE, 
+  input  logic             IFDivStartE, 
-  input  logic FDivBusyE, 
+  input  logic             FDivBusyE, 
-  input  logic SqrtE,
+  input  logic             SqrtE,
-  input  logic [`DIVb+3:0] X,
+  input  logic [`DIVb+3:0] X, D,
-  input  logic [`DIVb-1:0] DPreproc,
-  output logic [`DIVb-1:0] D,
   output logic [`DIVb:0]   FirstU, FirstUM,
   output logic [`DIVb+1:0] FirstC,
   output logic             Firstun,
@@ -79,8 +77,8 @@ module fdivsqrtiter(
   assign initUM = {~SqrtE, {(`DIVb){1'b0}}};
   mux2   #(`DIVb+1)  Umux(UNext[`DIVCOPIES-1],  initU,  IFDivStartE, UMux);
   mux2   #(`DIVb+1) UMmux(UMNext[`DIVCOPIES-1], initUM, IFDivStartE, UMMux);
-  flopen #(`DIVb+1)  UReg(clk, IFDivStartE|FDivBusyE, UMux,  U[0]);
+  flopen #(`DIVb+1)  UReg(clk, FDivBusyE, UMux,  U[0]);
-  flopen #(`DIVb+1) UMReg(clk, IFDivStartE|FDivBusyE, UMMux, UM[0]);
+  flopen #(`DIVb+1) UMReg(clk, FDivBusyE, UMMux, UM[0]);
 
   // C register/initialization mux
   // Initialize C to -1 for sqrt and -R for division
@@ -93,18 +91,13 @@ module fdivsqrtiter(
   
   assign initC = {initCUpper, {`DIVb{1'b0}}};
   mux2   #(`DIVb+2) cmux(C[`DIVCOPIES], initC, IFDivStartE, NextC); 
-  flopen #(`DIVb+2) creg(clk, IFDivStartE|FDivBusyE, NextC, C[0]);
+  flopen #(`DIVb+2) creg(clk, FDivBusyE, NextC, C[0]);
-
-   // Divisior register
-  flopen #(`DIVb) dreg(clk, IFDivStartE, DPreproc, D);
 
   // Divisor Selections
-  //  - choose the negitive version of what's being selected
+  assign DBar    = ~D;        // for -D
-  //  - D is a 0.b mantissa
-  assign DBar    = {3'b111, 1'b0, ~D};
   if(`RADIX == 4) begin : d2
-    assign DBar2 = {2'b11, 1'b0, ~D, 1'b1};
+    assign D2    = D << 1;    // for 2D,  only used in R4
-    assign D2    = {2'b0, 1'b1, D, 1'b0};
+    assign DBar2 = ~D2;       // for -2D, only used in R4
   end
 
   // k=DIVCOPIES of the recurrence logic

src/fpu/fdivsqrt/fdivsqrtpostproc.sv

@@ -32,7 +32,7 @@ module fdivsqrtpostproc(
   input  logic              clk, reset,
   input  logic              StallM,
   input  logic [`DIVb+3:0]  WS, WC,
-  input  logic [`DIVb-1:0]  D, 
+  input  logic [`DIVb+3:0]  D, 
   input  logic [`DIVb:0]    FirstU, FirstUM, 
   input  logic [`DIVb+1:0]  FirstC,
   input  logic              SqrtE,
@@ -46,7 +46,7 @@ module fdivsqrtpostproc(
   output logic [`XLEN-1:0]  FIntDivResultM
 );
   
-  logic [`DIVb+3:0]         W, Sum, DM;
+  logic [`DIVb+3:0]         W, Sum;
   logic [`DIVb:0]           PreQmM;
   logic                     NegStickyM;
   logic                     weq0E, WZeroM;
@@ -67,7 +67,7 @@ module fdivsqrtpostproc(
 
     assign FirstK = ({1'b1, FirstC} & ~({1'b1, FirstC} << 1));
     assign FZeroSqrtE = {FirstUM[`DIVb], FirstUM, 2'b0} | {FirstK,1'b0};    // F for square root
-    assign FZeroDivE =  {3'b001,D,1'b0};                                    // F for divide
+    assign FZeroDivE =  D << 1;                                    // F for divide
     mux2 #(`DIVb+4) fzeromux(FZeroDivE, FZeroSqrtE, SqrtE, FZeroE);
     csa #(`DIVb+4) fadd(WS, WC, FZeroE, 1'b0, WSF, WCF); // compute {WCF, WSF} = {WS + WC + FZero};
     aplusbeq0 #(`DIVb+4) wcfpluswsfeq0(WCF, WSF, wfeq0E);
@@ -102,17 +102,16 @@ module fdivsqrtpostproc(
     logic signed [`DIVb+3:0] PreResultM, PreIntResultM;
 
     assign W = $signed(Sum) >>> `LOGR;
-    assign DM = {4'b0001, D};
     assign UnsignedQuotM = {3'b000, PreQmM};
 
     // Integer remainder: sticky and sign correction muxes
-    mux2 #(`DIVb+4) normremdmux(W, W+DM, NegStickyM, NormRemDM);
+    mux2 #(`DIVb+4) normremdmux(W, W+D, NegStickyM, NormRemDM);
     mux2 #(`DIVb+4) normremsmux(NormRemDM, -NormRemDM, AsM, NormRemM);
     mux2 #(`DIVb+4) quotresmux(UnsignedQuotM, -UnsignedQuotM, NegQuotM, NormQuotM);
 
     // Select quotient or remainder and do normalization shift
     mux2 #(`DIVBLEN+1) normshiftmux(((`DIVBLEN+1)'(`DIVb) - (nM * (`DIVBLEN+1)'(`LOGR))), (mM + (`DIVBLEN+1)'(`DIVa)), RemOpM, NormShiftM);
-    mux2 #(`DIVb+4)   presresultmux(NormQuotM, NormRemM, RemOpM, PreResultM);
+    mux2 #(`DIVb+4)    presresultmux(NormQuotM, NormRemM, RemOpM, PreResultM);
     assign PreIntResultM = $signed(PreResultM >>> NormShiftM); 
 
     // special case logic

src/fpu/fdivsqrt/fdivsqrtpreproc.sv

@@ -33,29 +33,29 @@ module fdivsqrtpreproc (
   input  logic                IFDivStartE, 
   input  logic [`NF:0]        Xm, Ym,
   input  logic [`NE-1:0]      Xe, Ye,
-  input  logic [`FMTBITS-1:0] Fmt,
+  input  logic [`FMTBITS-1:0] FmtE,
-  input  logic                Sqrt,
+  input  logic                SqrtE,
   input  logic                XZeroE,
   input  logic [2:0]          Funct3E,
   output logic [`NE+1:0]      QeM,
-  output logic [`DIVb+3:0]    X,
+  output logic [`DIVb+3:0]    X, D,
-  output logic [`DIVb-1:0]    DPreproc,
   // Int-specific
   input  logic [`XLEN-1:0]    ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
   input  logic                IntDivE, W64E,
   output logic                ISpecialCaseE,
-  output logic [`DIVBLEN:0]   nE, nM, mM,
+  output logic [`DURLEN-1:0]  cycles,
+  output logic [`DIVBLEN:0]   nM, mM,
   output logic                NegQuotM, ALTBM, IntDivM, W64M,
   output logic                AsM, BZeroM,
   output logic [`XLEN-1:0]    AM
 );
 
-  logic [`DIVb-1:0]           XPreproc;
+  logic [`DIVb-1:0]           XPreproc, DPreproc;
   logic [`DIVb:0]             PreSqrtX;
   logic [`DIVb+3:0]           DivX, DivXShifted, SqrtX, PreShiftX; // Variations of dividend, to be muxed
   logic [`NE+1:0]             QeE;                                 // Quotient Exponent (FP only)
   logic [`DIVb-1:0]           IFX, IFD;                            // Correctly-sized inputs for iterator, selected from int or fp input
-  logic [`DIVBLEN:0]          mE, ell;                             // Leading zeros of inputs
+  logic [`DIVBLEN:0]          mE, nE, ell;                             // Leading zeros of inputs
   logic                       NumerZeroE;                          // Numerator is zero (X or A)
   logic                       AZeroE, BZeroE;                      // A or B is Zero for integer division
   logic                       signedDiv;                           // signed division
@@ -101,17 +101,21 @@ module fdivsqrtpreproc (
   lzc #(`DIVb) lzcX (IFX, ell);
   lzc #(`DIVb) lzcY (IFD, mE);
 
-  // Normalization shift
+  // Normalization shift: shift off leading one
-  assign XPreproc = IFX << (ell + {{`DIVBLEN{1'b0}}, 1'b1}); // *** try to remove this +1
+  assign XPreproc = (IFX << ell) << 1;
-  assign DPreproc = IFD << (mE + {{`DIVBLEN{1'b0}}, 1'b1}); 
+  assign DPreproc = (IFD << mE)  << 1; 
 
-  // append leading 1 (for normal inputs)
+  // append leading 1 (for nonzero inputs)
   // shift square root to be in range [1/4, 1)
   // Normalized numbers are shifted right by 1 if the exponent is odd
   // Denormalized numbers have Xe = 0 and an unbiased exponent of 1-BIAS.  They are shifted right if the number of leading zeros is odd.
   mux2 #(`DIVb+1) sqrtxmux({~XZeroE, XPreproc}, {1'b0, ~XZeroE, XPreproc[`DIVb-1:1]}, (Xe[0] ^ ell[0]), PreSqrtX);
   assign DivX = {3'b000, ~NumerZeroE, XPreproc};
 
+   // Divisior register
+  flopen #(`DIVb+4) dreg(clk, IFDivStartE, {4'b0001, DPreproc}, D);
+
+  // ***CT: factor out fdivsqrtcycles
   if (`IDIV_ON_FPU) begin:intrightshift // Int Supported
     logic [`DIVBLEN:0] ZeroDiff, p;
     logic  ALTBE;
@@ -119,7 +123,7 @@ module fdivsqrtpreproc (
     // calculate number of fractional bits p
     assign ZeroDiff = mE - ell;         // Difference in number of leading zeros
     assign ALTBE = ZeroDiff[`DIVBLEN];  // A less than B (A has more leading zeros)
-    mux2 #(`DIVBLEN+1) pmux(ZeroDiff, {(`DIVBLEN+1){1'b0}}, ALTBE, p);            // *** is there a more graceful way to write these constants    
+    mux2 #(`DIVBLEN+1) pmux(ZeroDiff, '0, ALTBE, p);              
 
     // Integer special cases (terminate immediately)
     assign ISpecialCaseE = BZeroE | ALTBE;
@@ -166,10 +170,13 @@ module fdivsqrtpreproc (
   // Sqrt is initialized on step one as R(X-1), so depends on Radix
   if (`RADIX == 2)  assign SqrtX = {3'b111, PreSqrtX};
   else              assign SqrtX = {2'b11, PreSqrtX, 1'b0};
-  mux2 #(`DIVb+4) prexmux(DivX, SqrtX, Sqrt, PreShiftX);
+  mux2 #(`DIVb+4) prexmux(DivX, SqrtX, SqrtE, PreShiftX);
  
   // Floating-point exponent
-  fdivsqrtexpcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZero(XZeroE), .ell, .m(mE), .Qe(QeE));
+  fdivsqrtexpcalc expcalc(.Fmt(FmtE), .Xe, .Ye, .Sqrt(SqrtE), .XZero(XZeroE), .ell, .m(mE), .Qe(QeE));
   flopen #(`NE+2) expreg(clk, IFDivStartE, QeE, QeM);
+
+  // Number of FSM cycles (to FSM)
+  fdivsqrtcycles cyclecalc(.FmtE, .SqrtE, .IntDivE, .nE, .cycles);
 endmodule
 

src/fpu/fdivsqrt/fdivsqrtqsel2.sv

@@ -30,7 +30,7 @@
 
 module fdivsqrtqsel2 ( 
   input  logic [3:0] ps, pc, 
-  output logic  up, uz, un
+  output logic       up, uz, un
 );
  
   logic [3:0]  p, g;

src/fpu/fdivsqrt/fdivsqrtstage2.sv

@@ -30,8 +30,7 @@
 
 /* verilator lint_off UNOPTFLAT */
 module fdivsqrtstage2 (
-  input  logic [`DIVb-1:0] D,
+  input  logic [`DIVb+3:0] D, DBar, 
-  input  logic [`DIVb+3:0] DBar, 
   input  logic [`DIVb:0]   U, UM,
   input  logic [`DIVb+3:0] WS, WC,
   input  logic [`DIVb+1:0] C,
@@ -66,7 +65,7 @@ module fdivsqrtstage2 (
   always_comb
     if      (up) Dsel = DBar;
     else if (uz) Dsel = '0;
-    else         Dsel = {4'b0001, D}; // un
+    else         Dsel = D; // un
 
   // Partial Product Generation
   //  WSA, WCA = WS + WC - qD

src/fpu/fdivsqrt/fdivsqrtstage4.sv

@@ -29,9 +29,8 @@
 `include "wally-config.vh"
 
 module fdivsqrtstage4 (
-  input  logic [`DIVb-1:0] D,
+  input  logic [`DIVb+3:0] D, DBar, D2, DBar2,
-  input  logic [`DIVb+3:0] DBar, D2, DBar2,
+  input  logic [`DIVb:0]   U,UM,
-  input  logic [`DIVb:0] U,UM,
   input  logic [`DIVb+3:0] WS, WC,
   input  logic [`DIVb+1:0] C,
   input  logic             SqrtE, j1,
@@ -58,8 +57,8 @@ module fdivsqrtstage4 (
   // 0000 =  0
   // 0010 = -1
   // 0001 = -2
-  assign Smsbs = U[`DIVb:`DIVb-4];
+  assign Smsbs  = U[`DIVb:`DIVb-4];
-  assign Dmsbs = D[`DIVb-1:`DIVb-3];
+  assign Dmsbs  = D[`DIVb-1:`DIVb-3];
   assign WCmsbs = WC[`DIVb+3:`DIVb-4];
   assign WSmsbs = WS[`DIVb+3:`DIVb-4];
 
@@ -75,7 +74,7 @@ module fdivsqrtstage4 (
       4'b1000: Dsel = DBar2;
       4'b0100: Dsel = DBar;
       4'b0000: Dsel = '0;
-      4'b0010: Dsel = {3'b0, 1'b1, D};
+      4'b0010: Dsel = D;
       4'b0001: Dsel = D2;
       default: Dsel = 'x;
     endcase

src/fpu/fdivsqrt/fdivsqrtuotfc2.sv

@@ -32,10 +32,10 @@
 // Unified OTFC, Radix 2 //
 ///////////////////////////////
 module fdivsqrtuotfc2(
-  input  logic         up, un,
+  input  logic             up, un,
   input  logic [`DIVb+1:0] C,
-  input logic [`DIVb:0] U, UM,
+  input  logic [`DIVb:0]   U, UM,
-  output logic [`DIVb:0] UNext, UMNext
+  output logic [`DIVb:0]   UNext, UMNext
 );
   //  The on-the-fly converter transfers the divsqrt
   //  bits to the quotient as they come.

src/fpu/fdivsqrt/fdivsqrtuotfc4.sv

@@ -29,7 +29,7 @@
 `include "wally-config.vh"
 
 module fdivsqrtuotfc4(
-  input  logic [3:0]   udigit,
+  input  logic [3:0]     udigit,
   input  logic [`DIVb:0] U, UM,
   input  logic [`DIVb:0] C,
   output logic [`DIVb:0] UNext, UMNext

src/fpu/fsgninj.sv

@@ -48,7 +48,7 @@ module fsgninj (
   
   // format final result based on precision
   //    - uses NaN-blocking format
-  //        - if there are any unsused bits the most significant bits are filled with 1s
+  //        - if there are any unused bits the most significant bits are filled with 1s
   
   if (`FPSIZES == 1)
     assign SgnRes = {ResSgn, X[`FLEN-2:0]};

src/fpu/postproc/round.sv

@@ -111,7 +111,7 @@ module round(
 
 
   // determine what format the final result is in: int or fp
-  assign IntRes = CvtOp & ToInt;
+  assign IntRes = ToInt;
   assign FpRes = ~IntRes;
 
   // sticky bit calculation
@@ -328,4 +328,4 @@ module round(
   assign Re = FullRe[`NE-1:0];
 
 
-endmodule
+endmodule

src/generic/lzc.sv

@@ -24,7 +24,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module lzc #(parameter WIDTH = 1) (
-  input logic  [WIDTH-1:0]            num,    // number to count the leading zeroes of
+  input  logic [WIDTH-1:0]            num,    // number to count the leading zeroes of
   output logic [$clog2(WIDTH+1)-1:0]  ZeroCnt // the number of leading zeroes
 );
 

src/generic/mux.sv

@@ -40,7 +40,7 @@ module mux3 #(parameter WIDTH = 8) (
   input  logic [1:0]       s, 
   output logic [WIDTH-1:0] y);
 
-  assign y = s[1] ? d2 : (s[0] ? d1 : d0); 
+  assign y = s[1] ? d2 : (s[0] ? d1 : d0); // exclusion-tag: mux3
 endmodule
 
 module mux4 #(parameter WIDTH = 8) (

src/generic/onehotdecoder.sv

@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// oneHotDecoder.sv
+// onehotdecoder.sv
 //
 // Written: ross1728@gmail.com July 09, 2021
 // Modified: 

src/hazard/hazard.sv

@@ -30,13 +30,13 @@
 
 module hazard (
   // Detect hazards
-  input logic  BPWrongE, CSRWriteFenceM, RetM, TrapM,   
+  input  logic  BPWrongE, CSRWriteFenceM, RetM, TrapM,   
-  input logic  LoadStallD, StoreStallD, MDUStallD, CSRRdStallD,
+  input  logic  LoadStallD, StoreStallD, MDUStallD, CSRRdStallD,
-  input logic  LSUStallM, IFUStallF,
+  input  logic  LSUStallM, IFUStallF,
-  input logic  FCvtIntStallD, FPUStallD,
+  input  logic  FCvtIntStallD, FPUStallD,
-  input logic  DivBusyE, FDivBusyE,
+  input  logic  DivBusyE, FDivBusyE,
-  input logic  EcallFaultM, BreakpointFaultM,
+  input  logic  EcallFaultM, BreakpointFaultM,
-  input logic  wfiM, IntPendingM,
+  input  logic  wfiM, IntPendingM,
   // Stall & flush outputs
   output logic StallF, StallD, StallE, StallM, StallW,
   output logic FlushD, FlushE, FlushM, FlushW

src/ieu/bmu/byte.sv

@@ -31,7 +31,7 @@
 
 module byteUnit #(parameter WIDTH=32) (
   input  logic [WIDTH-1:0] A,             // Operands
-  input  logic ByteSelect,                // LSB of Immediate
+  input  logic             ByteSelect,    // LSB of Immediate
   output logic [WIDTH-1:0] ByteResult);   // rev8, orcb result
 
   logic [WIDTH-1:0] OrcBResult, Rev8Result;

src/ieu/bmu/cnt.sv

@@ -32,8 +32,8 @@
 
 module cnt #(parameter WIDTH = 32) (
   input  logic [WIDTH-1:0] A, RevA,    // Operands
-  input  logic [1:0] B,                // Last 2 bits of immediate
+  input  logic [1:0]       B,          // Last 2 bits of immediate
-  input  logic W64,                    // Indicates word operation
+  input  logic             W64,        // Indicates word operation
   output logic [WIDTH-1:0] CntResult   // count result
 );
 

src/ieu/bmu/ext.sv

@@ -32,7 +32,7 @@
 
 module ext #(parameter WIDTH = 32) (
   input  logic [WIDTH-1:0] A,            // Operands
-  input  logic [1:0] ExtSelect,          // B[2], B[0] of immediate
+  input  logic [1:0]       ExtSelect,    // B[2], B[0] of immediate
   output logic [WIDTH-1:0] ExtResult);   // Extend Result
 
   logic [WIDTH-1:0] sexthResult, zexthResult, sextbResult;

src/ieu/bmu/popcnt.sv

@@ -27,7 +27,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 module popcnt #(parameter WIDTH = 32) (
-  input logic  [WIDTH-1:0]            num,    // number to count total ones
+  input  logic [WIDTH-1:0]        num,    // number to count total ones
   output logic [$clog2(WIDTH):0]  PopCnt  // the total number of ones
 );
 

src/ieu/controller.sv

@@ -300,7 +300,7 @@ module controller(
     assign FlushDCacheD = 0;
   end
  
-  // Decocde stage pipeline control register
+  // Decode stage pipeline control register
   flopenrc #(1)  controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD);
 
   // Execute stage pipeline control register and logic

src/ieu/datapath.sv

@@ -138,7 +138,8 @@ module datapath (
       assign MulDivResultW = MDUResultW;
     end
   end else begin:fpmux
-    assign IFResultM = IEUResultM; assign IFCvtResultW = IFResultW;
+    assign IFResultM = IEUResultM; 
+    assign IFCvtResultW = IFResultW;
     assign MulDivResultW = MDUResultW;
   end
   mux5  #(`XLEN)  resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, ResultW); 

src/ieu/ieu.sv

@@ -29,7 +29,7 @@
 `include "wally-config.vh"
 
 module ieu (
-  input  logic               clk, reset,
+  input  logic              clk, reset,
   // Decode stage signals
   input  logic [31:0]       InstrD,                          // Instruction
   input  logic              IllegalIEUFPUInstrD,             // Illegal instruction

src/ieu/regfile.sv

@@ -32,7 +32,7 @@
 module regfile (
   input  logic             clk, reset,
   input  logic             we3,                 // Write enable
-  input  logic [ 4:0]      a1, a2, a3,          // Source registers to read (a1, a2), destination register to write (a3)
+  input  logic [4:0]       a1, a2, a3,          // Source registers to read (a1, a2), destination register to write (a3)
   input  logic [`XLEN-1:0] wd3,                 // Write data for port 3
   output logic [`XLEN-1:0] rd1, rd2);           // Read data for ports 1, 2
 

src/ieu/shifter.sv

@@ -32,12 +32,12 @@
 module shifter (
   input  logic [`XLEN-1:0]     A,                             // shift Source
   input  logic [`LOG_XLEN-1:0] Amt,                           // Shift amount
-  input  logic                 Right, Rotate, W64, SubArith, // Shift right, rotate, W64-type operation, arithmetic shift
+  input  logic                 Right, Rotate, W64, SubArith,  // Shift right, rotate, W64-type operation, arithmetic shift
   output logic [`XLEN-1:0]     Y);                            // Shifted result
 
-  logic [2*`XLEN-2:0]      Z, ZShift;                         // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits
+  logic [2*`XLEN-2:0]          Z, ZShift;                     // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits
-  logic [`LOG_XLEN-1:0]    TruncAmt, Offset;                  // Shift amount adjusted for RV64, right-shift amount
+  logic [`LOG_XLEN-1:0]        TruncAmt, Offset;              // Shift amount adjusted for RV64, right-shift amount
-  logic                    Sign;                              // Sign bit for sign extension
+  logic                        Sign;                          // Sign bit for sign extension
 
   assign Sign = A[`XLEN-1] & SubArith;  // sign bit for sign extension
   if (`XLEN==32) begin // rv32

src/ifu/bpred/bpred.sv

@@ -48,25 +48,25 @@ module bpred (
   input  logic [`XLEN-1:0] PCE,                       // Execution stage instruction address
   input  logic [`XLEN-1:0] PCM,                       // Memory stage instruction address
 
-  input logic [31:0]       PostSpillInstrRawF,        // Instruction
+  input  logic [31:0]      PostSpillInstrRawF,        // Instruction
 
   // Branch and jump outcome
-  input logic              InstrValidD, InstrValidE,
+  input  logic             InstrValidD, InstrValidE,
   input  logic             BranchD, BranchE,
   input  logic             JumpD, JumpE,
-  input logic              PCSrcE,                    // Executation stage branch is taken
+  input  logic             PCSrcE,                    // Executation stage branch is taken
-  input logic [`XLEN-1:0]  IEUAdrE,                   // The branch/jump target address
+  input  logic [`XLEN-1:0] IEUAdrE,                   // The branch/jump target address
-  input logic [`XLEN-1:0]  IEUAdrM,                   // The branch/jump target address
+  input  logic [`XLEN-1:0] IEUAdrM,                   // The branch/jump target address
-  input logic [`XLEN-1:0]  PCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
+  input  logic [`XLEN-1:0] PCLinkE,                   // The address following the branch instruction. (AKA Fall through address)
   output logic [3:0]       InstrClassM,               // The valid instruction class. 1-hot encoded as call, return, jr (not return), j, br
 
   // Report branch prediction status
-  output logic             BPWrongE,              // Prediction is wrong
+  output logic             BPWrongE,                  // Prediction is wrong
-  output logic             BPWrongM,              // Prediction is wrong
+  output logic             BPWrongM,                  // Prediction is wrong
   output logic             BPDirPredWrongM,           // Prediction direction is wrong
-  output logic             BTAWrongM,           // Prediction target wrong
+  output logic             BTAWrongM,                 // Prediction target wrong
   output logic             RASPredPCWrongM,           // RAS prediction is wrong
-  output logic             IClassWrongM // Class prediction is wrong
+  output logic             IClassWrongM               // Class prediction is wrong
   );
 
   logic [1:0]              BPDirPredF;
@@ -187,7 +187,7 @@ module bpred (
   // Correct branch/jump target.
   mux2 #(`XLEN) pccorrectemux(PCLinkE, IEUAdrE, PCSrcE, PCCorrectE);
   
-  // If the fence/csrw was predicted as a taken branch then we select PCF, rather PCE.
+  // If the fence/csrw was predicted as a taken branch then we select PCF, rather than PCE.
   // Effectively this is PCM+4 or the non-existant PCLinkM
   if(`INSTR_CLASS_PRED) mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPWrongM, NextValidPCE);
   else  assign NextValidPCE = PCE;
@@ -201,11 +201,11 @@ module bpred (
     // 3. target ras    (ras target wrong / class[2])
     // 4. direction     (br dir wrong / class[0])
 
-    // Unforuantely we can't use PCD to infer the correctness of the BTB or RAS because the class prediction 
+    // Unfortunately we can't use PCD to infer the correctness of the BTB or RAS because the class prediction 
     // could be wrong or the fall through address selected for branch predict not taken.
     // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of
     // both without the above inaccuracies.
-  // **** use BPBTAWrongM from BTB.
+    // **** use BPBTAWrongM from BTB.
     assign BTAWrongE = (BPBTAE != IEUAdrE) & (BranchE | JumpE & ~ReturnE) & PCSrcE;
     assign RASPredPCWrongE = (RASPCE != IEUAdrE) & ReturnE & PCSrcE;
 

src/ifu/bpred/btb.sv

@@ -1,7 +1,7 @@
 ///////////////////////////////////////////
 // btb.sv
 //
-// Written: Ross Thomposn ross1728@gmail.com
+// Written: Ross Thompson ross1728@gmail.com
 // Created: February 15, 2021
 // Modified: 24 January 2023 
 //
@@ -34,19 +34,19 @@ module btb #(parameter Depth = 10 ) (
   input  logic             clk,
   input  logic             reset,
   input  logic             StallF, StallD, StallE, StallM, StallW, FlushD, FlushE, FlushM, FlushW,
-  input  logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,// PC at various stages
+  input  logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, // PC at various stages
-  output logic [`XLEN-1:0] BPBTAF, // BTB's guess at PC
+  output logic [`XLEN-1:0] BPBTAF,                      // BTB's guess at PC
   output logic [`XLEN-1:0] BPBTAD,
   output logic [`XLEN-1:0] BPBTAE,
-  output logic [3:0]       BTBIClassF, // BTB's guess at instruction class
+  output logic [3:0]       BTBIClassF,                  // BTB's guess at instruction class
   // update
-  input  logic             IClassWrongM, // BTB's instruction class guess was wrong
+  input  logic             IClassWrongM,                // BTB's instruction class guess was wrong
   input  logic             IClassWrongE,
-  input  logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb
+  input  logic [`XLEN-1:0] IEUAdrE,                     // Branch/jump target address to insert into btb
-  input  logic [`XLEN-1:0] IEUAdrM, // Branch/jump target address to insert into btb
+  input  logic [`XLEN-1:0] IEUAdrM,                     // Branch/jump target address to insert into btb
-  input  logic [3:0]       InstrClassD, // Instruction class to insert into btb
+  input  logic [3:0]       InstrClassD,                 // Instruction class to insert into btb
-  input  logic [3:0]       InstrClassE, // Instruction class to insert into btb
+  input  logic [3:0]       InstrClassE,                 // Instruction class to insert into btb
-  input  logic [3:0]       InstrClassM,                            // Instruction class to insert into btb
+  input  logic [3:0]       InstrClassM,                 // Instruction class to insert into btb
   input  logic [3:0]       InstrClassW
 );
 
@@ -73,7 +73,7 @@ module btb #(parameter Depth = 10 ) (
 
   // must output a valid PC and valid bit during reset.  Because only PCF, not PCNextF is reset, PCNextF is invalid
   // during reset.  The BTB must produce a non X PC1NextF to allow the simulation to run.
-  // While thie mux could be included in IFU it is not necessary for the IROM/I$/bus.
+  // While the mux could be included in IFU it is not necessary for the IROM/I$/bus.
   // For now it is optimal to leave it here.
   assign ResetPC = `RESET_VECTOR;
   assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; 

src/ifu/decompress.sv

@@ -44,7 +44,7 @@ module decompress (
   logic [5:0]         immSH;
   logic [1:0]         op;
     
-  // Extrac op and register source/destination fields
+  // Extract op and register source/destination fields
   assign instr16 = InstrRawD[15:0]; // instruction is already aligned
   assign op = instr16[1:0];
   assign rds1 = instr16[11:7];

src/ifu/ifu.sv

@@ -4,7 +4,7 @@
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified:
 //
-// Purpose: Instrunction Fetch Unit
+// Purpose: Instruction Fetch Unit
 //           PC, branch prediction, instruction cache
 // 
 // A component of the CORE-V-WALLY configurable RISC-V project.
@@ -362,7 +362,7 @@ module ifu (
   assign IllegalIEUFPUInstrD = IllegalIEUInstrD & IllegalFPUInstrD;
 
   // Misaligned PC logic
-  // Instruction address misalignement only from br/jal(r) instructions.
+  // Instruction address misalignment only from br/jal(r) instructions.
   // instruction address misalignment is generated by the target of control flow instructions, not
   // the fetch itself.
   // xret and Traps both cannot produce instruction misaligned.
@@ -372,7 +372,7 @@ module ifu (
   // Spec 3.1.14
   // Traps: Can’t happen.  The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4.  See 3.1.7 of the privileged spec.
   assign BranchMisalignedFaultE = (IEUAdrE[1] & ~`C_SUPPORTED) & PCSrcE;
-  flopenr #(1) InstrMisalginedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
+  flopenr #(1) InstrMisalignedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
 
   // Instruction and PC/PCLink pipeline registers
   // Cannot use flopenrc for Instr(E/M) as it resets to NOP not 0.

src/mdu/mdu.sv

@@ -69,8 +69,8 @@ module mdu(
       3'b001: PrelimResultM = ProdM[`XLEN*2-1:`XLEN];    // mulh
       3'b010: PrelimResultM = ProdM[`XLEN*2-1:`XLEN];    // mulhsu
       3'b011: PrelimResultM = ProdM[`XLEN*2-1:`XLEN];    // mulhu
-      3'b100: PrelimResultM = QuotM;                    // div
+      3'b100: PrelimResultM = QuotM;                     // div
-      3'b101: PrelimResultM = QuotM;                    // divu
+      3'b101: PrelimResultM = QuotM;                     // divu
       3'b110: PrelimResultM = RemM;                      // rem
       3'b111: PrelimResultM = RemM;                      // remu
     endcase 

src/mmu/mmu.sv

@@ -49,14 +49,14 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) (
   output logic                Idempotent,         // PMA indicates memory address is idempotent
   output logic                SelTIM,             // Select a tightly integrated memory
   // Faults
-  output logic                InstrAccessFaultF, LoadAccessFaultM, StoreAmoAccessFaultM,  // access fault sources
+  output logic                InstrAccessFaultF, LoadAccessFaultM, StoreAmoAccessFaultM, // access fault sources
-  output logic                InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM,        // page fault sources
+  output logic                InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM,       // page fault sources
-  output logic                UpdateDA,                                                // page fault due to setting dirty or access bit
+  output logic                UpdateDA,                                                  // page fault due to setting dirty or access bit
-  output logic                LoadMisalignedFaultM, StoreAmoMisalignedFaultM,             // misaligned fault sources
+  output logic                LoadMisalignedFaultM, StoreAmoMisalignedFaultM,            // misaligned fault sources
   // PMA checker signals
-  input  logic                 AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,  // access type
+  input  logic                AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,  // access type
-  input var logic [7:0]       PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],                        // PMP configuration
+  input var logic [7:0]       PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],                       // PMP configuration
-  input var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0]                        // PMP addresses
+  input var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0]                    // PMP addresses
 );
 
   logic [`PA_BITS-1:0]        TLBPAdr;                  // physical address for TLB                   
@@ -86,7 +86,7 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) (
           .DisableTranslation, .PTE, .PageTypeWriteVal,
           .TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss, .TLBHit, 
           .Translate, .TLBPageFault, .UpdateDA);
-  end else begin:tlb// just pass address through as physical
+  end else begin:tlb // just pass address through as physical
     assign Translate = 0;
     assign TLBMiss = 0;
     assign TLBHit = 1; // *** is this necessary

src/privileged/csrc.sv

@@ -117,7 +117,10 @@ module csrc #(parameter
     assign CounterEvent[21] = sfencevmaM & InstrValidNotFlushedM;                       // sfence.vma
     assign CounterEvent[22] = InterruptM;                                               // interrupt, InstrValidNotFlushedM will be low
     assign CounterEvent[23] = ExceptionM;                                               // exceptions, InstrValidNotFlushedM will be low
+    // coverage off
+    // DivBusyE will never be assert high since this configuration uses the FPU to do integer division
     assign CounterEvent[24] = DivBusyE | FDivBusyE;                                     // division cycles *** RT: might need to be delay until the next cycle
+    // coverage on
     assign CounterEvent[`COUNTERS-1:25] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
   end
   

src/privileged/csrsr.sv

@@ -93,7 +93,7 @@ module csrsr (
 
   // harwired STATUS bits
   assign STATUS_TSR = `S_SUPPORTED & STATUS_TSR_INT; // override reigster with 0 if supervisor mode not supported
-  assign STATUS_TW = (`S_SUPPORTED | `U_SUPPORTED) & STATUS_TW_INT; // override reigster with 0 if only machine mode supported
+  assign STATUS_TW = (`S_SUPPORTED | `U_SUPPORTED) & STATUS_TW_INT; // override register with 0 if only machine mode supported
   assign STATUS_TVM = `S_SUPPORTED & STATUS_TVM_INT; // override reigster with 0 if supervisor mode not supported
   assign STATUS_MXR = `S_SUPPORTED & STATUS_MXR_INT; // override reigster with 0 if supervisor mode not supported
 /*  assign STATUS_UBE = 0; // little-endian
@@ -198,9 +198,12 @@ module csrsr (
         STATUS_UBE <= #1 CSRWriteValM[6]  & `U_SUPPORTED & `BIGENDIAN_SUPPORTED;
         STATUS_MBE <= #1 nextMBE;
         STATUS_SBE <= #1 nextSBE;
+      // coverage off
+      // MSTATUSH only exists in 32-bit configurations, will not be hit on rv64gc
       end else if (WriteMSTATUSHM) begin
         STATUS_MBE <= #1 CSRWriteValM[5] & `BIGENDIAN_SUPPORTED;
         STATUS_SBE <= #1 CSRWriteValM[4] & `S_SUPPORTED & `BIGENDIAN_SUPPORTED;
+      // coverage on
       end else if (WriteSSTATUSM) begin // write a subset of the STATUS bits
         STATUS_MXR_INT <= #1 CSRWriteValM[19];
         STATUS_SUM_INT <= #1 CSRWriteValM[18];

src/privileged/trap.sv

@@ -81,11 +81,14 @@ module trap (
   ///////////////////////////////////////////
   
   assign BothInstrAccessFaultM = InstrAccessFaultM | HPTWInstrAccessFaultM;
+  // coverage off -item e 1 -fecexprrow 2
+  // excludes InstrMisalignedFaultM from coverage of this line, since misaligned instructions cannot occur in rv64gc.
   assign ExceptionM = InstrMisalignedFaultM | BothInstrAccessFaultM | IllegalInstrFaultM |
                       LoadMisalignedFaultM | StoreAmoMisalignedFaultM |
                       InstrPageFaultM | LoadPageFaultM | StoreAmoPageFaultM |
                       BreakpointFaultM | EcallFaultM |
                       LoadAccessFaultM | StoreAmoAccessFaultM;
+  // coverage on
   assign TrapM = ExceptionM | InterruptM; 
   assign RetM = mretM | sretM;
 
@@ -105,7 +108,10 @@ module trap (
     else if (InstrPageFaultM)          CauseM = 12;
     else if (BothInstrAccessFaultM)    CauseM = 1;
     else if (IllegalInstrFaultM)       CauseM = 2;
+    // coverage off
+    // Misaligned instructions cannot occur in rv64gc
     else if (InstrMisalignedFaultM)    CauseM = 0;
+    // coverage on
     else if (BreakpointFaultM)         CauseM = 3;
     else if (EcallFaultM)              CauseM = {2'b10, PrivilegeModeW};
     else if (LoadMisalignedFaultM)     CauseM = 4;

testbench/testbench-fp.sv

@@ -1,4 +1,4 @@
-<///////////////////////////////////////////
+///////////////////////////////////////////
 //
 // Written: me@KatherineParry.com
 // Modified: 7/5/2022
@@ -26,32 +26,29 @@
 `include "wally-config.vh"
 `include "tests-fp.vh"
 
-// steps to run FMA Tests
-//    1) create test vectors in riscv-wally/Tests/fp with: ./run-all.sh
-//    2) go to cvw/testbench/fp/Tests
-//    3) run ./sim-fma-batch
 module testbenchfp;
   parameter TEST="none";
 
-  string                       Tests[];        // list of tests to be run
+  string                       Tests[];                    // list of tests to be run
-  logic [2:0]                  OpCtrl[];       // list of op controls
+  logic [2:0]                  OpCtrl[];                   // list of op controls
-  logic [2:0]                  Unit[];         // list of units being tested
+  logic [2:0]                  Unit[];                     // list of units being tested
-  logic                        WriteInt[];           // Is being written to integer resgiter
+  logic                        WriteInt[];                 // Is being written to integer resgiter
   logic [2:0]                  Frm[4:0] = {3'b100, 3'b010, 3'b011, 3'b001, 3'b000}; // rounding modes: rne-000, rz-001, ru-011, rd-010, rnm-100
-  logic [1:0]                  Fmt[];          // list of formats for the other units  
+  logic [1:0]                  Fmt[];                      // list of formats for the other units  
 
   logic                        clk=0;
-  logic [31:0]                 TestNum=0;    // index for the test
+  logic [31:0]                 TestNum=0;                  // index for the test
-  logic [31:0]                 OpCtrlNum=0;  // index for OpCtrl
+  logic [31:0]                 OpCtrlNum=0;                // index for OpCtrl
-  logic [31:0]                 errors=0;     // how many errors
+  logic [31:0]                 errors=0;                   // how many errors
-  logic [31:0]                 VectorNum=0;  // index for test vector
+  logic [31:0]                 VectorNum=0;                // index for test vector
-  logic [31:0]                 FrmNum=0;     // index for rounding mode
+  logic [31:0]                 FrmNum=0;                   // index for rounding mode
   logic [`FLEN*4+7:0]          TestVectors[8388609:0];     // list of test vectors
 
-  logic [1:0]                  FmtVal;          // value of the current Fmt
+  logic [1:0]                  FmtVal;                     // value of the current Fmt
   logic [2:0]                  UnitVal, OpCtrlVal, FrmVal; // value of the currnet Unit/OpCtrl/FrmVal
   logic                        WriteIntVal;                // value of the current WriteInt
   logic [`FLEN-1:0]            X, Y, Z;                    // inputs read from TestFloat
+  logic [`FLEN-1:0] 	       XPostBox;                   // inputs read from TestFloat
   logic [`XLEN-1:0]            SrcA;                       // integer input
   logic [`FLEN-1:0]	       Ans;                        // correct answer from TestFloat
   logic [`FLEN-1:0]	       Res;                        // result from other units
@@ -67,15 +64,15 @@ module testbenchfp;
   logic [`NF:0]                Xm, Ym, Zm;                 // mantissas of the inputs
   logic                        XNaN, YNaN, ZNaN;           // is the input NaN
   logic                        XSNaN, YSNaN, ZSNaN;        // is the input a signaling NaN
-  logic                        XSubnorm, ZSubnorm;           // is the input denormalized
+  logic                        XSubnorm, ZSubnorm;         // is the input denormalized
   logic                        XInf, YInf, ZInf;           // is the input infinity
   logic                        XZero, YZero, ZZero;        // is the input zero
   logic                        XExpMax, YExpMax, ZExpMax;  // is the input's exponent all ones  
   logic  [`CVTLEN-1:0]         CvtLzcInE;                  // input to the Leading Zero Counter (priority encoder)
   logic                        IntZero;
   logic                        CvtResSgnE;
-  logic [`NE:0]                CvtCalcExpE;    // the calculated expoent
+  logic [`NE:0]                CvtCalcExpE;                // the calculated expoent
-  logic [`LOGCVTLEN-1:0]       CvtShiftAmtE;  // how much to shift by
+  logic [`LOGCVTLEN-1:0]       CvtShiftAmtE;               // how much to shift by
   logic [`DIVb:0]              Quot;
   logic                        CvtResSubnormUfE;
   logic                        DivStart, FDivBusyE, OldFDivBusyE;
@@ -102,6 +99,15 @@ module testbenchfp;
   logic [`NE+1:0]              DivCalcExp;
   logic                        divsqrtop;
 
+   // Missing logic vectors fdivsqrt
+   logic [2:0]                 Funct3E;
+   logic [2:0]                 Funct3M;
+   logic                       FlushE;
+   logic                       IFDivStartE, FDivDoneE;
+   logic [`NE+1:0]             QeM;
+   logic [`DIVb:0]             QmM;
+   logic [`XLEN-1:0]           FIntDivResultM;   
+
 
   ///////////////////////////////////////////////////////////////////////////////////////////////
 
@@ -147,8 +153,9 @@ module testbenchfp;
                Fmt = {Fmt, 2'b11};
             end
          end
-      end
+      end 
-      if (TEST === "cvtfp" | TEST === "all") begin  // if the floating-point conversions are being tested
+      // if the floating-point conversions are being tested          
+      if (TEST === "cvtfp" | TEST === "all") begin  
         if(`D_SUPPORTED) begin // if double precision is supported
           // add the 128 <-> 64 bit conversions to the to-be-tested list
           Tests = {Tests, f128f64cvt};
@@ -571,38 +578,23 @@ module testbenchfp;
       end
       if (TEST === "div"   | TEST === "all") begin // if division is being tested
         // add the correct tests/op-ctrls/unit/fmt to their lists
-        Tests = {f16div, Tests};
+        Tests = {Tests, f16div};
-        OpCtrl = {`DIV_OPCTRL, OpCtrl};
-        WriteInt = {1'b0, WriteInt};
-        for(int i = 0; i<5; i++) begin
-          Unit = {`DIVUNIT, Unit};
-          Fmt = {2'b10, Fmt};
-        end
-        /* Tests = {Tests, f16div};
         OpCtrl = {OpCtrl, `DIV_OPCTRL};
         WriteInt = {WriteInt, 1'b0};
         for(int i = 0; i<5; i++) begin
           Unit = {Unit, `DIVUNIT};
           Fmt = {Fmt, 2'b10};
-        end */
+        end
       end
       if (TEST === "sqrt"  | TEST === "all") begin // if sqrt is being tested
         // add the correct tests/op-ctrls/unit/fmt to their lists
-        // reverse order
+        Tests = {Tests, f16sqrt};
-        Tests = {f16sqrt, Tests};
-        OpCtrl = {`SQRT_OPCTRL, OpCtrl};
-        WriteInt = {1'b0, WriteInt};
-        for(int i = 0; i<5; i++) begin
-          Unit = {`DIVUNIT, Unit};
-          Fmt = {2'b10, Fmt};
-        end
-/*        Tests = {Tests, f16sqrt};
         OpCtrl = {OpCtrl, `SQRT_OPCTRL};
         WriteInt = {WriteInt, 1'b0};
         for(int i = 0; i<5; i++) begin
           Unit = {Unit, `DIVUNIT};
           Fmt = {Fmt, 2'b10};
-        end */
+        end 
       end
       if (TEST === "fma"   | TEST === "all") begin // if fma is being tested
         Tests = {Tests, f16fma};
@@ -656,18 +648,17 @@ module testbenchfp;
   end
 
   // extract the inputs (X, Y, Z, SrcA) and the output (Ans, AnsFlg) from the current test vector
-  readvectors readvectors          (.clk, .Fmt(FmtVal), .ModFmt, .TestVector(TestVectors[VectorNum]), 
+  readvectors readvectors (.clk, .Fmt(FmtVal), .ModFmt, .TestVector(TestVectors[VectorNum]), 
-                                    .VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA, 
+                           .VectorNum, .Ans(Ans), .AnsFlg(AnsFlg), .SrcA, 
-                                    .Xs, .Ys, .Zs, .Unit(UnitVal),
+                           .Xs, .Ys, .Zs, .Unit(UnitVal),
-                                    .Xe, .Ye, .Ze, .TestNum, .OpCtrl(OpCtrlVal),
+                           .Xe, .Ye, .Ze, .TestNum, .OpCtrl(OpCtrlVal),
-                                    .Xm, .Ym, .Zm, .DivStart,
+                           .Xm, .Ym, .Zm, .DivStart,
-                                    .XNaN, .YNaN, .ZNaN,
+                           .XNaN, .YNaN, .ZNaN,
-                                    .XSNaN, .YSNaN, .ZSNaN, 
+                           .XSNaN, .YSNaN, .ZSNaN, 
-                                    .XSubnorm, .ZSubnorm, 
+                           .XSubnorm, .ZSubnorm, 
-                                    .XZero, .YZero, .ZZero,
+                           .XZero, .YZero, .ZZero,
-                                    .XInf, .YInf, .ZInf, .XExpMax,
+                           .XInf, .YInf, .ZInf, .XExpMax,
-                                    .X, .Y, .Z);
+                           .X, .Y, .Z, .XPostBox);
-
 
 
   ///////////////////////////////////////////////////////////////////////////////////////////////
@@ -713,11 +704,16 @@ module testbenchfp;
                 .XNaN, .YNaN, .XSNaN, .YSNaN, .X, .Y, .CmpNV(CmpFlg[4]), .CmpFpRes(FpCmpRes));
   end
   if (TEST === "div" | TEST === "sqrt" | TEST === "all") begin: fdivsqrt
-    fdivsqrt fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]),
+     fdivsqrt fdivsqrt(.clk, .reset, .XsE(Xs), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym), 
-                    .XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), .XNaNE(XNaN), .YNaNE(YNaN), 
+		       .XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal[0]), .SqrtM(OpCtrlVal[0]),
-                    .FDivStartE(DivStart), .IDivStartE(1'b0), .MDUE(1'b0), .W64E(1'b0),
+                       .XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero), 
-                    .StallM(1'b0), .DivSM(DivSticky), .FDivBusyE, .QeM(DivCalcExp),
+		       .XNaNE(XNaN), .YNaNE(YNaN), 
-                    .QmM(Quot));
+                       .FDivStartE(DivStart), .IDivStartE(1'b0), .W64E(1'b0),
+                       .StallM(1'b0), .DivStickyM(DivSticky), .FDivBusyE, .QeM(DivCalcExp),
+                       .QmM(Quot),
+                       .FlushE(1'b0), .ForwardedSrcAE('0), .ForwardedSrcBE('0), .Funct3M(Funct3M),
+                       .Funct3E(Funct3E), .IntDivE(1'b0), .FIntDivResultM(FIntDivResultM),
+                       .FDivDoneE(FDivDoneE), .IFDivStartE(IFDivStartE));
   end
 
   assign CmpFlg[3:0] = 0;
@@ -726,6 +722,16 @@ module testbenchfp;
   always begin
     clk = 1; #5; clk = 0; #5;
   end
+
+  // Provide reset for divsqrt to reset state to IDLE
+  // Previous version did not initiate a divide due to missing state
+  // information.  This starts the FSM by putting the fdivsqrt into
+  // the IDLE state.
+  initial
+  begin
+    #0 reset = 1'b1;
+    #25 reset = 1'b0;     
+  end  
   
 ///////////////////////////////////////////////////////////////////////////////////////////////
 
@@ -738,7 +744,7 @@ module testbenchfp;
 
 ///////////////////////////////////////////////////////////////////////////////////////////////
 
-  //Check if the correct answer and result is a NaN
+  // Check if the correct answer and result is a NaN
   always_comb begin
     if(UnitVal === `CVTINTUNIT | UnitVal === `CMPUNIT) begin
       // an integer output can't be a NaN
@@ -809,7 +815,7 @@ end
   logic ResMatch, FlagMatch, CheckNow;
 
 always @(posedge clk) 
-  OldFDivBusyE = FDivBusyE;
+  OldFDivBusyE = FDivDoneE;
 
 // check results on falling edge of clk
 always @(negedge clk) begin
@@ -912,9 +918,15 @@ always @(negedge clk) begin
       $stop;
     end
 
-    if(~(FDivBusyE|DivStart)|(UnitVal != `DIVUNIT)) VectorNum += 1; // increment the vector
+    // Add extra clock cycles in beginning for fdivsqrt to adequate reset state
-
+    if(~(FDivBusyE|DivStart)|(UnitVal != `DIVUNIT)) begin
-    if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the end of file
+       repeat (12)
+	 @(posedge clk);
+       if (reset != 1'b1)
+	 VectorNum += 1; // increment the vector
+    end
+   
+    if (TestVectors[VectorNum][0] === 1'bx & Tests[TestNum] !== "") begin // if reached the eof
 
       // increment the test
       TestNum += 1;
@@ -944,31 +956,29 @@ always @(negedge clk) begin
 endmodule
 
 
-
-
 module readvectors (
-  input logic clk,
+  input logic                clk,
-  input logic [`FLEN*4+7:0] TestVector,
+  input logic [`FLEN*4+7:0]  TestVector,
   input logic [`FMTBITS-1:0] ModFmt,
-  input logic [1:0] Fmt,
+  input logic [1:0]          Fmt,
-  input logic [2:0] Unit,
+  input logic [2:0]          Unit,
-  input logic [31:0] VectorNum,
+  input logic [31:0]         VectorNum,
-  input logic [31:0] TestNum,
+  input logic [31:0]         TestNum,
-  input logic [2:0] OpCtrl,
+  input logic [2:0]          OpCtrl,
-  output logic [`FLEN-1:0] Ans,
+  output logic [`FLEN-1:0]   Ans,
-  output logic [`XLEN-1:0] SrcA,
+  output logic [`XLEN-1:0]   SrcA,
-  output logic [4:0] AnsFlg,
+  output logic [4:0]         AnsFlg,
-  output logic                    Xs, Ys, Zs,    // sign bits of XYZ
+  output logic               Xs, Ys, Zs, // sign bits of XYZ
-  output logic [`NE-1:0]          Xe, Ye, Ze,    // exponents of XYZ (converted to largest supported precision)
+  output logic [`NE-1:0]     Xe, Ye, Ze, // exponents of XYZ (converted to largest supported precision)
-  output logic [`NF:0]            Xm, Ym, Zm,    // mantissas of XYZ (converted to largest supported precision)
+  output logic [`NF:0]       Xm, Ym, Zm, // mantissas of XYZ (converted to largest supported precision)
-  output logic                    XNaN, YNaN, ZNaN,    // is XYZ a NaN
+  output logic               XNaN, YNaN, ZNaN, // is XYZ a NaN
-  output logic                    XSNaN, YSNaN, ZSNaN, // is XYZ a signaling NaN
+  output logic               XSNaN, YSNaN, ZSNaN, // is XYZ a signaling NaN
-  output logic                    XSubnorm, ZSubnorm,   // is XYZ denormalized
+  output logic               XSubnorm, ZSubnorm,  // is XYZ denormalized
-  output logic                    XZero, YZero, ZZero,         // is XYZ zero
+  output logic               XZero, YZero, ZZero, // is XYZ zero
-  output logic                    XInf, YInf, ZInf,            // is XYZ infinity
+  output logic               XInf, YInf, ZInf,    // is XYZ infinity
-  output logic                    XExpMax,
+  output logic               XExpMax,
-  output logic                    DivStart,
+  output logic               DivStart,
-  output logic [`FLEN-1:0] X, Y, Z
+  output logic [`FLEN-1:0]   X, Y, Z, XPostBox
 );
   logic XEn, YEn, ZEn;
 
@@ -1331,5 +1341,5 @@ module readvectors (
   unpack unpack(.X, .Y, .Z, .Fmt(ModFmt), .Xs, .Ys, .Zs, .Xe, .Ye, .Ze,
                 .Xm, .Ym, .Zm, .XNaN, .YNaN, .ZNaN, .XSNaN, .YSNaN, .ZSNaN,
                 .XSubnorm, .XZero, .YZero, .ZZero, .XInf, .YInf, .ZInf,
-                .XEn, .YEn, .ZEn, .XExpMax);
+                .XEn, .YEn, .ZEn, .XExpMax, .XPostBox);
 endmodule

testbench/testbench.sv

@@ -49,32 +49,32 @@ module testbench;
   string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
   logic [31:0] InstrW;
 
-string tests[];
+  string tests[];
-logic [3:0] dummy;
+  logic [3:0] dummy;
 
-  logic [`AHBW-1:0] HRDATAEXT;
+  logic [`AHBW-1:0]    HRDATAEXT;
-  logic             HREADYEXT, HRESPEXT;
+  logic                HREADYEXT, HRESPEXT;
   logic [`PA_BITS-1:0] HADDR;
-  logic [`AHBW-1:0] HWDATA;
+  logic [`AHBW-1:0]    HWDATA;
-  logic [`XLEN/8-1:0] HWSTRB;
+  logic [`XLEN/8-1:0]  HWSTRB;
-  logic             HWRITE;
+  logic                HWRITE;
-  logic [2:0]       HSIZE;
+  logic [2:0]          HSIZE;
-  logic [2:0]       HBURST;
+  logic [2:0]          HBURST;
-  logic [3:0]       HPROT;
+  logic [3:0]          HPROT;
-  logic [1:0]       HTRANS;
+  logic [1:0]          HTRANS;
-  logic             HMASTLOCK;
+  logic                HMASTLOCK;
-  logic             HCLK, HRESETn;
+  logic                HCLK, HRESETn;
-  logic [`XLEN-1:0] PCW;
+  logic [`XLEN-1:0]    PCW;
 
-  string ProgramAddrMapFile, ProgramLabelMapFile;
+  string  ProgramAddrMapFile, ProgramLabelMapFile;
-  integer   	ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 };
+  integer ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 };
 
-  logic 	    DCacheFlushDone, DCacheFlushStart;
+  logic DCacheFlushDone, DCacheFlushStart;
   logic riscofTest; 
   logic StartSample, EndSample;
     
   flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW);
-  flopenr  #(32)   InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW,  dut.core.ifu.InstrM, InstrW);
+  flopenr #(32)    InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW,  dut.core.ifu.InstrM, InstrW);
 
   // check assertions for a legal configuration
   riscvassertions riscvassertions();
@@ -85,62 +85,62 @@ logic [3:0] dummy;
     //tests = '{};
     if (`XLEN == 64) begin // RV64
       case (TEST)
-        "arch64i":                        tests = arch64i;
+        "arch64i":                               tests = arch64i;
-        "arch64priv":                     tests = arch64priv;
+        "arch64priv":                            tests = arch64priv;
         "arch64c":      if (`C_SUPPORTED) 
-                          if (`ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv};
+                          if (`ZICSR_SUPPORTED)  tests = {arch64c, arch64cpriv};
-                          else                  tests = {arch64c};
+                          else                   tests = {arch64c};
-        "arch64m":      if (`M_SUPPORTED) tests = arch64m;
+        "arch64m":      if (`M_SUPPORTED)        tests = arch64m;
-        "arch64f":      if (`F_SUPPORTED) tests = arch64f;
+        "arch64f":      if (`F_SUPPORTED)        tests = arch64f;
-        "arch64d":      if (`D_SUPPORTED) tests = arch64d;  
+        "arch64d":      if (`D_SUPPORTED)        tests = arch64d;  
         "arch64zi":     if (`ZIFENCEI_SUPPORTED) tests = arch64zi;
-        "imperas64i":                     tests = imperas64i;
+        "imperas64i":                            tests = imperas64i;
-        "imperas64f":   if (`F_SUPPORTED) tests = imperas64f;
+        "imperas64f":   if (`F_SUPPORTED)        tests = imperas64f;
-        "imperas64d":   if (`D_SUPPORTED) tests = imperas64d;
+        "imperas64d":   if (`D_SUPPORTED)        tests = imperas64d;
-        "imperas64m":   if (`M_SUPPORTED) tests = imperas64m;
+        "imperas64m":   if (`M_SUPPORTED)        tests = imperas64m;
-        "wally64a":     if (`A_SUPPORTED) tests = wally64a;
+        "wally64a":     if (`A_SUPPORTED)        tests = wally64a;
-        "imperas64c":   if (`C_SUPPORTED) tests = imperas64c;
+        "imperas64c":   if (`C_SUPPORTED)        tests = imperas64c;
-                        else              tests = imperas64iNOc;
+                        else                     tests = imperas64iNOc;
-        "custom":                         tests = custom;
+        "custom":                                tests = custom;
-        "wally64i":                       tests = wally64i; 
+        "wally64i":                              tests = wally64i; 
-        "wally64priv":                    tests = wally64priv;
+        "wally64priv":                           tests = wally64priv;
-        "wally64periph":                  tests = wally64periph;
+        "wally64periph":                         tests = wally64periph;
-        "coremark":                       tests = coremark;
+        "coremark":                              tests = coremark;
-        "fpga":                           tests = fpga;
+        "fpga":                                  tests = fpga;
-        "ahb" :                           tests = ahb;
+        "ahb" :                                  tests = ahb;
-        "coverage64gc" :                  tests = coverage64gc;
+        "coverage64gc" :                         tests = coverage64gc;
-        "arch64zba":     if (`ZBA_SUPPORTED) tests = arch64zba;
+        "arch64zba":     if (`ZBA_SUPPORTED)     tests = arch64zba;
-        "arch64zbb":     if (`ZBB_SUPPORTED) tests = arch64zbb;
+        "arch64zbb":     if (`ZBB_SUPPORTED)     tests = arch64zbb;
-        "arch64zbc":     if (`ZBC_SUPPORTED) tests = arch64zbc;
+        "arch64zbc":     if (`ZBC_SUPPORTED)     tests = arch64zbc;
-        "arch64zbs":     if (`ZBS_SUPPORTED) tests = arch64zbs;
+        "arch64zbs":     if (`ZBS_SUPPORTED)     tests = arch64zbs;
       endcase 
     end else begin // RV32
       case (TEST)
-        "arch32i":                        tests = arch32i;
+        "arch32i":                               tests = arch32i;
-        "arch32priv":                     tests = arch32priv;
+        "arch32priv":                            tests = arch32priv;
         "arch32c":      if (`C_SUPPORTED) 
-                          if (`ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv};
+                          if (`ZICSR_SUPPORTED)  tests = {arch32c, arch32cpriv};
-                          else                  tests = {arch32c};
+                          else                   tests = {arch32c};
-        "arch32m":      if (`M_SUPPORTED) tests = arch32m;
+        "arch32m":      if (`M_SUPPORTED)        tests = arch32m;
-        "arch32f":      if (`F_SUPPORTED) tests = arch32f;
+        "arch32f":      if (`F_SUPPORTED)        tests = arch32f;
-        "arch32d":      if (`D_SUPPORTED) tests = arch32d;
+        "arch32d":      if (`D_SUPPORTED)        tests = arch32d;
         "arch32zi":     if (`ZIFENCEI_SUPPORTED) tests = arch32zi;
-        "imperas32i":                     tests = imperas32i;
+        "imperas32i":                            tests = imperas32i;
-        "imperas32f":   if (`F_SUPPORTED) tests = imperas32f;
+        "imperas32f":   if (`F_SUPPORTED)        tests = imperas32f;
-        "imperas32m":   if (`M_SUPPORTED) tests = imperas32m;
+        "imperas32m":   if (`M_SUPPORTED)        tests = imperas32m;
-        "wally32a":     if (`A_SUPPORTED) tests = wally32a;
+        "wally32a":     if (`A_SUPPORTED)        tests = wally32a;
-        "imperas32c":   if (`C_SUPPORTED) tests = imperas32c;
+        "imperas32c":   if (`C_SUPPORTED)        tests = imperas32c;
-                        else              tests = imperas32iNOc;
+                        else                     tests = imperas32iNOc;
-        "wally32i":                       tests = wally32i; 
+        "wally32i":                              tests = wally32i; 
-        "wally32e":                       tests = wally32e; 
+        "wally32e":                              tests = wally32e; 
-        "wally32priv":                    tests = wally32priv;
+        "wally32priv":                           tests = wally32priv;
-        "wally32periph":                   tests = wally32periph;
+        "wally32periph":                         tests = wally32periph;
-        "embench":                        tests = embench;
+        "embench":                               tests = embench;
-        "coremark":                       tests = coremark;
+        "coremark":                              tests = coremark;
-        "arch32zba":     if (`ZBA_SUPPORTED) tests = arch32zba;
+        "arch32zba":     if (`ZBA_SUPPORTED)     tests = arch32zba;
-        "arch32zbb":     if (`ZBB_SUPPORTED) tests = arch32zbb;
+        "arch32zbb":     if (`ZBB_SUPPORTED)     tests = arch32zbb;
-        "arch32zbc":     if (`ZBC_SUPPORTED) tests = arch32zbc;
+        "arch32zbc":     if (`ZBC_SUPPORTED)     tests = arch32zbc;
-        "arch32zbs":     if (`ZBS_SUPPORTED) tests = arch32zbs;
+        "arch32zbs":     if (`ZBS_SUPPORTED)     tests = arch32zbs;
       endcase
     end
     if (tests.size() == 0) begin
@@ -149,7 +149,7 @@ logic [3:0] dummy;
     end
   end
 
-  string signame, memfilename, pathname, objdumpfilename, adrstr, outputfile;
+  string  signame, memfilename, pathname, objdumpfilename, adrstr, outputfile;
   integer outputFilePointer;
 
   logic [31:0] GPIOIN, GPIOOUT, GPIOEN;
@@ -160,16 +160,16 @@ logic [3:0] dummy;
   logic        SDCCmdOut;
   logic        SDCCmdOE;
   logic [3:0]  SDCDatIn;
-  tri1 [3:0]   SDCDat;
+  tri1  [3:0]  SDCDat;
   tri1         SDCCmd;
 
   logic        HREADY;
   logic        HSELEXT;
   
-  logic 	   InitializingMemories;
+  logic        InitializingMemories;
-  integer 	   ResetCount, ResetThreshold;
+  integer      ResetCount, ResetThreshold;
-  logic 	   InReset;
+  logic        InReset;
-  logic        Begin;
+  logic        BeginSample;
   
   // instantiate device to be tested
   assign GPIOIN = 0;
@@ -225,13 +225,14 @@ logic [3:0] dummy;
       totalerrors = 0;
       testadr = 0;
       testadrNoBase = 0;
-      // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests and  tests[0] == "2" refers to WallyRiscvArchTests 
+      // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests 
+      // and tests[0] == "2" refers to WallyRiscvArchTests 
       riscofTest = tests[0] == "1" | tests[0] == "2"; 
       // fill memory with defined values to reduce Xs in simulation
       // Quick note the memory will need to be initialized.  The C library does not
-      //  guarantee the  initialized reads.  For example a strcmp can read 6 byte
+      // guarantee the  initialized reads.  For example a strcmp can read 6 byte
-      //  strings, but uses a load double to read them in.  If the last 2 bytes are
+      // strings, but uses a load double to read them in.  If the last 2 bytes are
-      //  not initialized the compare results in an 'x' which propagates through 
+      // not initialized the compare results in an 'x' which propagates through 
       // the design.
       if (TEST == "coremark") 
         for (i=MemStartAddr; i<MemEndAddr; i = i+1) 
@@ -243,7 +244,7 @@ logic [3:0] dummy;
        pathname = tvpaths[0];
        else pathname = tvpaths[1]; */
       if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
-      else memfilename = {pathname, tests[test], ".elf.memfile"};
+      else            memfilename = {pathname, tests[test], ".elf.memfile"};
       if (`FPGA) begin
         string romfilename, sdcfilename;
         romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
@@ -253,9 +254,9 @@ logic [3:0] dummy;
         // force sdc timers
         force dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
       end else begin
-        if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
+        if (`IROM_SUPPORTED)     $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
         else if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
-        if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
+        if (`DTIM_SUPPORTED)     $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
       end
 
       if (riscofTest) begin
@@ -265,8 +266,9 @@ logic [3:0] dummy;
         ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
         ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
       end
-      // declare memory labels that interest us, the updateProgramAddrLabelArray task will find the addr of each label and fill the array
+      // declare memory labels that interest us, the updateProgramAddrLabelArray task will find 
-      // to expand, add more elements to this array and initialize them to zero (also initilaize them to zero at the start of the next test)
+      // the addr of each label and fill the array. To expand, add more elements to this array 
+      // and initialize them to zero (also initilaize them to zero at the start of the next test)
       if(!`FPGA) begin
         updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
         $display("Read memfile %s", memfilename);
@@ -294,99 +296,99 @@ logic [3:0] dummy;
           ResetCount = 0;
         end
       end else begin
-		if (TEST == "coremark")
+        if (TEST == "coremark")
           if (dut.core.priv.priv.EcallFaultM) begin
-			$display("Benchmark: coremark is done.");
+            $display("Benchmark: coremark is done.");
-			$stop;
+            $stop;
           end
-		// Termination condition (i.e. we finished running current test) 
+        // Termination condition (i.e. we finished running current test) 
-		if (DCacheFlushDone) begin
+        if (DCacheFlushDone) begin
           integer begin_signature_addr;
           InReset = 1;
           begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
           if (!begin_signature_addr)
-			$display("begin_signature addr not found in %s", ProgramLabelMapFile);
+            $display("begin_signature addr not found in %s", ProgramLabelMapFile);
           testadr = ($unsigned(begin_signature_addr))/(`XLEN/8);
           testadrNoBase = (begin_signature_addr - `UNCORE_RAM_BASE)/(`XLEN/8);
           #600; // give time for instructions in pipeline to finish
           if (TEST == "embench") begin
             // Writes contents of begin_signature to .sim.output file
-            // this contains instret and cycles for start and end of test run, used by embench python speed script to calculate embench speed score
+            // this contains instret and cycles for start and end of test run, used by embench 
-            // also begin_signature contains the results of the self checking mechanism, which will be read by the python script for error checking
+            // python speed script to calculate embench speed score. 
+            // also, begin_signature contains the results of the self checking mechanism, 
+            // which will be read by the python script for error checking
             $display("Embench Benchmark: %s is done.", tests[test]);
             if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
             else outputfile = {pathname, tests[test], ".sim.output"};
             outputFilePointer = $fopen(outputfile);
             i = 0;
             while ($unsigned(i) < $unsigned(5'd5)) begin
-                    $fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
+              $fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
-                    i = i + 1;
+              i = i + 1;
             end
             $fclose(outputFilePointer);
             $display("Embench Benchmark: created output file: %s", outputfile);
           end else if (TEST == "coverage64gc") begin
             $display("Coverage tests don't get checked");
           end else begin 
-			// for tests with no self checking mechanism, read .signature.output file and compare to check for errors
+            // for tests with no self checking mechanism, read .signature.output file and compare to check for errors
-			// clear signature to prevent contamination from previous tests
+            // clear signature to prevent contamination from previous tests
-			for(i=0; i<SIGNATURESIZE; i=i+1) begin
+            for(i=0; i<SIGNATURESIZE; i=i+1) begin
               sig32[i] = 'bx;
-			end
+            end
-			if (riscofTest) signame = {pathname, tests[test], "/ref/Reference-sail_c_simulator.signature"};
+            if (riscofTest) signame = {pathname, tests[test], "/ref/Reference-sail_c_simulator.signature"};
-			else signame = {pathname, tests[test], ".signature.output"};
+            else signame = {pathname, tests[test], ".signature.output"};
-			// read signature, reformat in 64 bits if necessary
+            // read signature, reformat in 64 bits if necessary
-			$readmemh(signame, sig32);
+            $readmemh(signame, sig32);
-			i = 0;
+            i = 0;
-			while (i < SIGNATURESIZE) begin
+            while (i < SIGNATURESIZE) begin
               if (`XLEN == 32) begin
-				signature[i] = sig32[i];
+                signature[i] = sig32[i];
-				i = i+1;
+                i = i+1;
               end else begin
-				signature[i/2] = {sig32[i+1], sig32[i]};
+                signature[i/2] = {sig32[i+1], sig32[i]};
-				i = i + 2;
+                i = i + 2;
               end
               if (i >= 4 & sig32[i-4] === 'bx) begin
-				if (i == 4) begin
+                if (i == 4) begin
                   i = SIGNATURESIZE+1; // flag empty file
                   $display("  Error: empty test file");
-				end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
+                end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
               end
-			end
+            end
 
-			// Check errors
+            // Check errors
-			errors = (i == SIGNATURESIZE+1); // error if file is empty
+            errors = (i == SIGNATURESIZE+1); // error if file is empty
-			i = 0;
+            i = 0;
-			/* verilator lint_off INFINITELOOP */
+            /* verilator lint_off INFINITELOOP */
-			while (signature[i] !== 'bx) begin
+            while (signature[i] !== 'bx) begin
               logic [`XLEN-1:0] sig;
               if (`DTIM_SUPPORTED) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
               else if (`UNCORE_RAM_SUPPORTED) sig = dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
               //$display("signature[%h] = %h sig = %h", i, signature[i], sig);
               if (signature[i] !== sig & (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin  
-				errors = errors+1;
+                errors = errors+1;
-				$display("  Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", 
+                $display("  Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", 
-						 tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
+						    tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
-				$stop;//***debug
+                $stop; //***debug
               end
               i = i + 1;
-			end
+            end
-			/* verilator lint_on INFINITELOOP */
+            /* verilator lint_on INFINITELOOP */
-			if (errors == 0) begin
+            if (errors == 0) begin
               $display("%s succeeded.  Brilliant!!!", tests[test]);
-			end
+            end else begin
-			else begin
               $display("%s failed with %d errors. :(", tests[test], errors);
               totalerrors = totalerrors+1;
-			end
+            end
           end
           // move onto the next test, check to see if we're done
           test = test + 1;
           if (test == tests.size()) begin
-			if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
+          if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
-			else $display("FAIL: %d test programs had errors", totalerrors);
+          else $display("FAIL: %d test programs had errors", totalerrors);
-			$stop;
+          $stop;
-          end
+          end else begin
-          else begin
             InitializingMemories = 1;
             // If there are still additional tests to run, read in information for the next test
             //pathname = tvpaths[tests[0]];
@@ -394,7 +396,7 @@ logic [3:0] dummy;
             else memfilename = {pathname, tests[test], ".elf.memfile"};
             //$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
             if (`IROM_SUPPORTED)               $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
-            else if (`UNCORE_RAM_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
+            else if (`UNCORE_RAM_SUPPORTED)    $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
             if (`DTIM_SUPPORTED)               $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
 
             if (riscofTest) begin
@@ -405,22 +407,22 @@ logic [3:0] dummy;
               ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
             end
             ProgramAddrLabelArray = '{ "begin_signature" : 0, "tohost" : 0 };
-			if(!`FPGA) begin
+            if(!`FPGA) begin
               updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
               $display("Read memfile %s", memfilename);
-			end
+            end
           end
-		end // if (DCacheFlushDone)
+        end // if (DCacheFlushDone)
       end
     end // always @ (negedge clk)
 
 
   if(`PrintHPMCounters & `ZICOUNTERS_SUPPORTED) begin : HPMCSample
-    integer HPMCindex;
+    integer           HPMCindex;
-	logic 	StartSampleFirst;
+    logic             StartSampleFirst;
-	logic 	StartSampleDelayed, BeginDelayed;
+    logic             StartSampleDelayed, BeginDelayed;
-	logic 	EndSampleFirst, EndSampleDelayed;
+    logic             EndSampleFirst, EndSampleDelayed;
-	logic [`XLEN-1:0] InitialHPMCOUNTERH[`COUNTERS-1:0];
+    logic [`XLEN-1:0] InitialHPMCOUNTERH[`COUNTERS-1:0];
 
     string  HPMCnames[] = '{"Mcycle",
                             "------",
@@ -433,8 +435,8 @@ logic [3:0] dummy;
                             "BP Target Wrong",
                             "RAS Wrong",
                             "Instr Class Wrong",
-							"Load Stall",
+                            "Load Stall",
-							"Store Stall",
+                            "Store Stall",
                             "D Cache Access",
                             "D Cache Miss",
                             "D Cache Cycles",
@@ -447,56 +449,55 @@ logic [3:0] dummy;
                             "Interrupt",
                             "Exception",
                             "Divide Cycles"
-							};
+                          };
 
-	if(TEST == "embench") begin
+    if(TEST == "embench") begin
-	  // embench runs warmup then runs start_trigger
+      // embench runs warmup then runs start_trigger
-	  // embench end with stop_trigger.
+      // embench end with stop_trigger.
-	  assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
+      assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
-	  flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
+      flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
-	  assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
+      assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
 
-	  assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger";
+      assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger";
-	  flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
+      flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
-	  assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
+      assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
 
-	end else if(TEST == "coremark") begin
+    end else if(TEST == "coremark") begin
-	  // embench runs warmup then runs start_trigger
+      // embench runs warmup then runs start_trigger
-	  // embench end with stop_trigger.
+	    // embench end with stop_trigger.
-	  assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time";
+      assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time";
-	  flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
+      flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
-	  assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
+      assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
 
-	  assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time";
+      assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time";
-	  flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
+      flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
-	  assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
+      assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
 
-	end else begin
+    end else begin
-	  // default start condiction is reset
+      // default start condiction is reset
-	  // default end condiction is end of test (DCacheFlushDone)
+      // default end condiction is end of test (DCacheFlushDone)
-	  assign StartSampleFirst = InReset;
+      assign StartSampleFirst = InReset;
-	  flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
+      flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
-	  assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
+      assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
-	  assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
+      assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
 
-	  flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed);
+      flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed);
-	  assign Begin = StartSampleFirst & ~BeginDelayed;
+      assign BeginSample = StartSampleFirst & ~BeginDelayed;
 
-	end
+    end
-	
     always @(negedge clk) begin
-	  if(StartSample) begin
+      if(StartSample) begin
-		for(HPMCindex = 0; HPMCindex < 32; HPMCindex += 1) begin
+        for(HPMCindex = 0; HPMCindex < 32; HPMCindex += 1) begin
-		  InitialHPMCOUNTERH[HPMCindex] <= dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex];
+          InitialHPMCOUNTERH[HPMCindex] <= dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex];
-		end
+        end
-	  end
+      end
       if(EndSample) begin
         for(HPMCindex = 0; HPMCindex < HPMCnames.size(); HPMCindex += 1) begin
           // unlikely to have more than 10M in any counter.
           $display("Cnt[%2d] = %7d %s", HPMCindex, dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex] - InitialHPMCOUNTERH[HPMCindex], HPMCnames[HPMCindex]);
-		end
+        end
-	  end
+      end
-	end
+    end
   end
   
 
@@ -535,67 +536,72 @@ logic [3:0] dummy;
   if (`BPRED_SUPPORTED) begin
     integer adrindex;
 
-	always @(*) begin
+    always @(*) begin
-	  if(reset) begin
+      if(reset) begin
-		for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
+        for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
-		  force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
+          force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
-		end
+        end
-		for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
+        for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
-		  force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
+          force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
-		end
+        end
-        #1;
+          #1;
-		for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
+        for(adrindex = 0; adrindex < 2**`BTB_SIZE; adrindex++) begin
-		  release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
+          release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
-		end 
+        end 
-		for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
+        for(adrindex = 0; adrindex < 2**`BPRED_SIZE; adrindex++) begin
-		  release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
+          release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
-		end
+        end
-	  end
+      end
-	end
+    end
-end
+  end
 
 
   if (`ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin : ICacheLogger
     int    file;
-	string LogFile;
+    string LogFile;
-	logic  resetD, resetEdge;
+    logic  resetD, resetEdge;
     logic  Enable;
-    // assign Enable = ~dut.core.StallD & ~dut.core.FlushD & dut.core.ifu.bus.icache.CacheRWF[1] & ~reset;
+    logic  InvalDelayed, InvalEdge;
     
-    // this version of Enable allows for accurate eviction logging.
+    assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn & 
-    // Likely needs further improvement.
+                    dut.core.ifu.immu.immu.pmachecker.Cacheable &
-    assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn & ~reset;
+                    ~dut.core.ifu.bus.icache.icache.cachefsm.FlushStage &
-	flop #(1) ResetDReg(clk, reset, resetD);
+                    ~reset;
-	assign resetEdge = ~reset & resetD;
+    flop #(1) ResetDReg(clk, reset, resetD);
+    assign resetEdge = ~reset & resetD;
+
+    flop #(1) InvalReg(clk, dut.core.ifu.InvalidateICacheM, InvalDelayed);
+    assign InvalEdge = dut.core.ifu.InvalidateICacheM & ~InvalDelayed;
+
     initial begin
-	  LogFile = $psprintf("ICache.log");
+      LogFile = $psprintf("ICache.log");
       file = $fopen(LogFile, "w");
-	  $fwrite(file, "BEGIN %s\n", memfilename);
+      $fwrite(file, "BEGIN %s\n", memfilename);
-	end
+    end
     string AccessTypeString, HitMissString;
     assign HitMissString = dut.core.ifu.bus.icache.icache.CacheHit ? "H" :
                            dut.core.ifu.bus.icache.icache.vict.cacheLRU.AllValid ? "E" : "M";
-    assign AccessTypeString = dut.core.ifu.InvalidateICacheM ? "I" : "R";
     always @(posedge clk) begin
-	  if(resetEdge) $fwrite(file, "TRAIN\n");
+    if(resetEdge) $fwrite(file, "TRAIN\n");
-	  if(Begin) $fwrite(file, "BEGIN %s\n", memfilename);
+    if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename);
-	  if(Enable) begin  // only log i cache reads
+    if(Enable) begin  // only log i cache reads
-	    $fwrite(file, "%h %s %s\n", dut.core.ifu.PCPF, AccessTypeString, HitMissString);
+      $fwrite(file, "%h R %s\n", dut.core.ifu.PCPF, HitMissString);
-	  end
+    end
-	  if(EndSample) $fwrite(file, "END %s\n", memfilename);
+    if(InvalEdge) $fwrite(file, "0 I X\n");
+    if(EndSample) $fwrite(file, "END %s\n", memfilename);
     end
   end
 
 
   if (`DCACHE_SUPPORTED && `D_CACHE_ADDR_LOGGER) begin : DCacheLogger
     int    file;
-	string LogFile;
+    string LogFile;
-	logic  resetD, resetEdge;
+    logic  resetD, resetEdge;
     logic  Enabled;
     string AccessTypeString, HitMissString;
 
-	flop #(1) ResetDReg(clk, reset, resetD);
+    flop #(1) ResetDReg(clk, reset, resetD);
-	assign resetEdge = ~reset & resetD;
+    assign resetEdge = ~reset & resetD;
     assign HitMissString = dut.core.lsu.bus.dcache.dcache.CacheHit ? "H" :
                            (!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" :
                            dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E";
@@ -604,28 +610,25 @@ end
                               dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" : 
                               dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" :
                               "NULL";
-    // assign Enabled = (dut.core.lsu.bus.dcache.dcache.cachefsm.CurrState == 0) &
+    
-    //                  ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage &
-    //                  (AccessTypeString != "NULL");
-
-    // This version of enable allows for accurate eviction logging. 
-    // Likely needs further improvement.
     assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn &
                      ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage &
+                     dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable &
                      (AccessTypeString != "NULL");
 
     initial begin
-	    LogFile = $psprintf("DCache.log");
+      LogFile = $psprintf("DCache.log");
       file = $fopen(LogFile, "w");
-	    $fwrite(file, "BEGIN %s\n", memfilename);
+      $fwrite(file, "BEGIN %s\n", memfilename);
-	  end
+    end
     always @(posedge clk) begin
-	  if(resetEdge) $fwrite(file, "TRAIN\n");
+      if(resetEdge) $fwrite(file, "TRAIN\n");
-	  if(Begin) $fwrite(file, "BEGIN %s\n", memfilename);
+      if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename);
-	  if(Enabled) begin
+      if(Enabled) begin
-	    $fwrite(file, "%h %s %s\n", dut.core.lsu.PAdrM, AccessTypeString, HitMissString);
+        $fwrite(file, "%h %s %s\n", dut.core.lsu.PAdrM, AccessTypeString, HitMissString);
-	  end
+      end
-	  if(EndSample) $fwrite(file, "END %s\n", memfilename);
+      if(dut.core.lsu.bus.dcache.dcache.cachefsm.FlushFlag) $fwrite(file, "0 F X\n");
+      if(EndSample) $fwrite(file, "END %s\n", memfilename);
     end
   end
 
@@ -633,45 +636,45 @@ end
     if (`BPRED_LOGGER) begin
       string direction;
       int    file;
-	  logic  PCSrcM;
+      logic  PCSrcM;
-	  string LogFile;
+      string LogFile;
-	  logic  resetD, resetEdge;
+      logic  resetD, resetEdge;
-	  flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM);
+      flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM);
-	  flop #(1) ResetDReg(clk, reset, resetD);
+      flop #(1) ResetDReg(clk, reset, resetD);
-	  assign resetEdge = ~reset & resetD;
+      assign resetEdge = ~reset & resetD;
       initial begin
-		LogFile = $psprintf("branch_%s%0d.log", `BPRED_TYPE, `BPRED_SIZE);
+        LogFile = $psprintf("branch_%s%0d.log", `BPRED_TYPE, `BPRED_SIZE);
         file = $fopen(LogFile, "w");
-	  end
+      end
       always @(posedge clk) begin
-		if(resetEdge) $fwrite(file, "TRAIN\n");
+        if(resetEdge) $fwrite(file, "TRAIN\n");
-		if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename);
+        if(StartSample) $fwrite(file, "BEGIN %s\n", memfilename);
-		if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
+        if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
-		  direction = PCSrcM ? "t" : "n";
+          direction = PCSrcM ? "t" : "n";
-		  $fwrite(file, "%h %s\n", dut.core.PCM, direction);
+          $fwrite(file, "%h %s\n", dut.core.PCM, direction);
-		end
+        end
-		if(EndSample) $fwrite(file, "END %s\n", memfilename);
+        if(EndSample) $fwrite(file, "END %s\n", memfilename);
-	  end
+      end
     end
   end
 
-  // check for hange up.
+  // check for hang up.
   logic [`XLEN-1:0] OldPCW;
-  integer 			WatchDogTimerCount;
+  integer           WatchDogTimerCount;
-  localparam WatchDogTimerThreshold = 1000000;
+  localparam        WatchDogTimerThreshold = 1000000;
-  logic 			WatchDogTimeOut;
+  logic             WatchDogTimeOut;
   always_ff @(posedge clk) begin
-	OldPCW <= PCW;
+    OldPCW <= PCW;
-	if(OldPCW == PCW) WatchDogTimerCount = WatchDogTimerCount + 1'b1;
+    if(OldPCW == PCW) WatchDogTimerCount = WatchDogTimerCount + 1'b1;
-	else WatchDogTimerCount = '0;
+    else WatchDogTimerCount = '0;
   end
 
   always_comb begin
-	WatchDogTimeOut = WatchDogTimerCount >= WatchDogTimerThreshold;
+    WatchDogTimeOut = WatchDogTimerCount >= WatchDogTimerThreshold;
-	if(WatchDogTimeOut) begin
+    if(WatchDogTimeOut) begin
-	  $display("FAILURE: Watch Dog Time Out triggered. PCW stuck at %x for more than %d cycles", PCW, WatchDogTimerCount);
+      $display("FAILURE: Watch Dog Time Out triggered. PCW stuck at %x for more than %d cycles", PCW, WatchDogTimerCount);
-	  $stop;
+      $stop;
-	end
+	  end
   end
   
 endmodule
@@ -689,34 +692,34 @@ module DCacheFlushFSM
 
   logic [`XLEN-1:0] ShadowRAM[`UNCORE_RAM_BASE>>(1+`XLEN/32):(`UNCORE_RAM_RANGE+`UNCORE_RAM_BASE)>>1+(`XLEN/32)];
   
-	if(`DCACHE_SUPPORTED) begin
+  if(`DCACHE_SUPPORTED) begin
-	  localparam numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
+    localparam numlines       = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
-	  localparam numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
+    localparam numways        = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
-	  localparam linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
+    localparam linebytelen    = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
-	  localparam linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN;
+    localparam linelen        = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN;
-	  localparam sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;            
+    localparam sramlen        = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;            
-	  localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
+    localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
-	  localparam numwords = sramlen/`XLEN;
+    localparam numwords       = sramlen/`XLEN;
-    localparam lognumlines = $clog2(numlines);
+    localparam lognumlines    = $clog2(numlines);
-	  localparam loglinebytelen = $clog2(linebytelen);
+    localparam loglinebytelen = $clog2(linebytelen);
-	  localparam lognumways = $clog2(numways);
+    localparam lognumways     = $clog2(numways);
-	  localparam tagstart = lognumlines + loglinebytelen;
+    localparam tagstart       = lognumlines + loglinebytelen;
 
 
 
-	  genvar 			 index, way, cacheWord;
+    genvar               index, way, cacheWord;
-	  logic [sramlen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
+    logic [sramlen-1:0]  CacheData  [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
-    logic [sramlen-1:0] cacheline;
+    logic [sramlen-1:0]  cacheline;
-	  logic [`XLEN-1:0]  CacheTag [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
+    logic [`XLEN-1:0]    CacheTag   [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
-	  logic 			 CacheValid  [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
+    logic                CacheValid [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
-	  logic 			 CacheDirty  [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
+    logic                CacheDirty [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
-	  logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
+    logic [`PA_BITS-1:0] CacheAdr   [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
     for(index = 0; index < numlines; index++) begin
-		  for(way = 0; way < numways; way++) begin
+      for(way = 0; way < numways; way++) begin
-		    for(cacheWord = 0; cacheWord < cachesramwords; cacheWord++) begin
+        for(cacheWord = 0; cacheWord < cachesramwords; cacheWord++) begin
-			    copyShadow #(.tagstart(tagstart),
+          copyShadow #(.tagstart(tagstart),
-					.loglinebytelen(loglinebytelen), .sramlen(sramlen))
+          .loglinebytelen(loglinebytelen), .sramlen(sramlen))
-			    copyShadow(.clk,
+          copyShadow(.clk,
           .start,
           .tag(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].CacheTagMem.RAM[index][`PA_BITS-1-tagstart:0]),
           .valid(testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[way].ValidBits[index]),
@@ -765,18 +768,18 @@ endmodule
 
 module copyShadow
   #(parameter tagstart, loglinebytelen, sramlen)
-  (input logic clk,
+  (input  logic                       clk,
-   input logic 			     start,
+   input  logic                       start,
-   input logic [`PA_BITS-1:tagstart] tag,
+   input  logic [`PA_BITS-1:tagstart] tag,
-   input logic 			     valid, dirty,
+   input  logic                       valid, dirty,
-   input logic [sramlen-1:0] 	     data,
+   input  logic [sramlen-1:0]         data,
-   input logic [32-1:0] 	     index,
+   input  logic [32-1:0]              index,
-   input logic [32-1:0] 	     cacheWord,
+   input  logic [32-1:0]              cacheWord,
-   output logic [sramlen-1:0] 	     CacheData,
+   output logic [sramlen-1:0]         CacheData,
-   output logic [`PA_BITS-1:0] 	     CacheAdr,
+   output logic [`PA_BITS-1:0]        CacheAdr,
-   output logic [`XLEN-1:0] 	     CacheTag,
+   output logic [`XLEN-1:0]           CacheTag,
-   output logic 		     CacheValid,
+   output logic                       CacheValid,
-   output logic 		     CacheDirty);
+   output logic                       CacheDirty);
   
 
   always_ff @(posedge clk) begin
@@ -805,8 +808,7 @@ task automatic updateProgramAddrLabelArray;
       integer returncode;
       returncode = $fscanf(ProgramLabelMapFP, "%s\n", label);
       returncode = $fscanf(ProgramAddrMapFP, "%s\n", adrstr);
-      if (ProgramAddrLabelArray.exists(label)) 
+      if (ProgramAddrLabelArray.exists(label)) ProgramAddrLabelArray[label] = adrstr.atohex();
-        ProgramAddrLabelArray[label] = adrstr.atohex();
     end
   end
   $fclose(ProgramLabelMapFP);

testbench/tests-fp.vh

@@ -25,15 +25,15 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `define PATH "../tests/fp/vectors/"
-`define ADD_OPCTRL 3'b110
+`define ADD_OPCTRL     3'b110
-`define MUL_OPCTRL 3'b100
+`define MUL_OPCTRL     3'b100
-`define SUB_OPCTRL 3'b111
+`define SUB_OPCTRL     3'b111
-`define FMA_OPCTRL 3'b000
+`define FMA_OPCTRL     3'b000
-`define DIV_OPCTRL 3'b000
+`define DIV_OPCTRL     3'b000
-`define SQRT_OPCTRL 3'b001
+`define SQRT_OPCTRL    3'b001
-`define LE_OPCTRL 3'b011
+`define LE_OPCTRL      3'b011
-`define LT_OPCTRL 3'b001
+`define LT_OPCTRL      3'b001
-`define EQ_OPCTRL 3'b010
+`define EQ_OPCTRL      3'b010
 `define TO_UI_OPCTRL   3'b000
 `define TO_I_OPCTRL    3'b001
 `define TO_UL_OPCTRL   3'b010
@@ -42,16 +42,16 @@
 `define FROM_I_OPCTRL  3'b101
 `define FROM_UL_OPCTRL 3'b110
 `define FROM_L_OPCTRL  3'b111
-`define RNE 3'b000
+`define RNE            3'b000
-`define RZ  3'b001
+`define RZ             3'b001
-`define RU  3'b011
+`define RU             3'b011
-`define RD  3'b010
+`define RD             3'b010
-`define RNM 3'b100
+`define RNM            3'b100
-`define FMAUNIT 2
+`define FMAUNIT        2
-`define DIVUNIT 1
+`define DIVUNIT        1
-`define CVTINTUNIT 0
+`define CVTINTUNIT     0
-`define CVTFPUNIT 4
+`define CVTFPUNIT      4
-`define CMPUNIT 3
+`define CMPUNIT        3
 
 string f16rv32cvtint[] = '{
 	"ui32_to_f16_rne.tv",
@@ -238,7 +238,6 @@ string f128rv32cvtint[] = '{
 	"f128_to_i32_rnm.tv"
 };
 
-
 string f32f16cvt[] = '{
 	"f32_to_f16_rne.tv",
 	"f32_to_f16_rz.tv",
@@ -291,7 +290,6 @@ string f64f32cvt[] = '{
 	"f32_to_f64_rnm.tv"
 };
 
-
 string f128f32cvt[] = '{
 	"f128_to_f32_rne.tv",
 	"f128_to_f32_rz.tv",
@@ -305,7 +303,6 @@ string f128f32cvt[] = '{
 	"f32_to_f128_rnm.tv"
 };
 
-
 string f128f64cvt[] = '{
 	"f128_to_f64_rne.tv",
 	"f128_to_f64_rz.tv",

testbench/tests.vh

@@ -51,7 +51,19 @@ string tvpaths[] = '{
     "ifu",
     "fpu",
     "lsu",
-    "vm64check"
+    "vm64check",
+    "pmp",
+    "dcache1",
+    "dcache2",
+    "pmpcfg",
+    "pmpcfg1",
+    "pmpcfg2",
+    "tlbKP",
+    "tlbMP",
+    "tlbM3",
+    "tlbASID",
+    "tlbGLB",
+    "ifuCamlineWrite"
   };
 
   string coremark[] = '{
@@ -1906,8 +1918,10 @@ string arch64zbs[] = '{
     "rv64i_m/privilege/src/WALLY-mie-01.S",
     "rv64i_m/privilege/src/WALLY-minfo-01.S",
     "rv64i_m/privilege/src/WALLY-misa-01.S",
-    "rv64i_m/privilege/src/WALLY-mmu-sv39-01.S",
+//    "rv64i_m/privilege/src/WALLY-mmu-sv39-01.S",  // run this if SVADU_SUPPORTED = 0
-    "rv64i_m/privilege/src/WALLY-mmu-sv48-01.S",
+//    "rv64i_m/privilege/src/WALLY-mmu-sv48-01.S",  // run this if SVADU_SUPPORTED = 0
+    "rv64i_m/privilege/src/WALLY-mmu-sv39-svadu-01.S",  // run this if SVADU_SUPPORTED = 1
+    "rv64i_m/privilege/src/WALLY-mmu-sv48-svadu-01.S",  // run this if SVADU_SUPPORTED = 1
     "rv64i_m/privilege/src/WALLY-mtvec-01.S",
     "rv64i_m/privilege/src/WALLY-pma-01.S",
     "rv64i_m/privilege/src/WALLY-pmp-01.S",
@@ -1995,7 +2009,8 @@ string arch64zbs[] = '{
     "rv32i_m/privilege/src/WALLY-mie-01.S",
     "rv32i_m/privilege/src/WALLY-minfo-01.S",
     "rv32i_m/privilege/src/WALLY-misa-01.S",
-    "rv32i_m/privilege/src/WALLY-mmu-sv32-01.S",
+//    "rv32i_m/privilege/src/WALLY-mmu-sv32-01.S",
+    "rv32i_m/privilege/src/WALLY-mmu-sv32-svadu-01.S",
     "rv32i_m/privilege/src/WALLY-mtvec-01.S",
     "rv32i_m/privilege/src/WALLY-pma-01.S",
     "rv32i_m/privilege/src/WALLY-pmp-01.S",

tests/coverage/WALLY-init-lib.h

@@ -66,8 +66,7 @@ interrupt:              # must be a timer interrupt
     j trap_return       # clean up and return
 
 exception:
-    li t0, 2
+    csrr t0, mcause
-    csrr t1, mcause
     li t1, 8            # is it an ecall trap?
     andi t0, t0, 0xFC # if CAUSE = 8, 9, or 11
     bne t0, t1, trap_return # ignore other exceptions

tests/coverage/dcache1.S

@@ -0,0 +1,83 @@
+      #include "WALLY-init-lib.h"
+main:
+      // start way test #1
+      li t0, 0x80100000
+.align 6
+      // i$ boundary, way test #1
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      sd zero, 0(t0)
+      sd zero, 0(t0)
+      .word 0x00000013
+      .word 0x00000013
+      // start way test #2
+      li t0, 0x80101000
+.align 6
+      // i$ boundary, way test #2
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      sd zero, 0(t0)
+      sd zero, 0(t0)
+      .word 0x00000013
+      .word 0x00000013
+      // start way test #3
+      li t0, 0x80102000
+.align 6
+      // i$ boundary, way test #3
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      sd zero, 0(t0)
+      sd zero, 0(t0)
+      .word 0x00000013
+      .word 0x00000013
+      // start way test #4
+      li t0, 0x80103000
+.align 6
+      // i$ boundary, way test #4
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      .word 0x00000013
+      sd zero, 0(t0)
+      sd zero, 0(t0)
+      .word 0x00000013
+      .word 0x00000013
+      j done

tests/coverage/dcache1.py

@@ -0,0 +1,86 @@
+####################
+# dcache1.py
+#
+# Written: avercruysse@hmc.edu 18 April 2023
+#
+# Purpose: Test Coverage for D$
+#          (For each way, trigger a CacheDataMem write enable while chip enable is low)        
+#
+# A component of the CORE-V-WALLY configurable RISC-V project.
+# 
+# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+#
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+#
+# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+# except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+# may obtain a copy of the License at
+#
+# https://solderpad.org/licenses/SHL-2.1/
+#
+# Unless required by applicable law or agreed to in writing, any work distributed under the 
+# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+# either express or implied. See the License for the specific language governing permissions 
+# and limitations under the License.
+################################################
+
+import os
+
+test_name = "dcache1.S"
+dcache_num_ways = 4
+dcache_way_size_in_bytes = 4096 
+# warning i$ line size is not currently parameterized.
+
+# arbitrary start location of where I send stores to.
+mem_start_addr = 0x80100000
+
+# pointer to the start of unused memory (strictly increasing)
+mem_addr = mem_start_addr
+
+
+def wl(line="", comment=None, fname=test_name):
+    with open(fname, "a") as f:
+        instr = False if (":" in line or
+                          ".align" in line or
+                          "# include" in line) else True
+        indent = 6 if instr else 0
+        comment = "// " + comment if comment is not None else ""
+        to_write = " " * indent + line + comment + "\n"
+        f.write(to_write)
+
+    
+def write_repro_instrs():
+    """
+    Assumes that the store location has been fetched to d$, and is in t0.
+    """
+    for i in range(16): # write a whole cache set.
+        if i == 12:
+            wl('sd zero, 0(t0)') # D$ write to set PCM = PCF + 8 for proper alignment (stallD will happen).
+        elif i == 13:
+            # the store in question happens here, at adresses 0x34, 0x74
+            wl('sd zero, 0(t0)') # it should hit this time
+        else:
+            # can't be a NOP or anything else that is encoded as compressed.
+            # this is because the branch predictor will use the wrong address
+            # so the IFU cache miss will come late.
+            wl('.word 0x00000013') # addi x0, x0, 0 (canonical NOP, uncompressed).
+
+if __name__ == "__main__":
+    if os.path.exists(test_name):
+        os.remove(test_name)
+        # os.rename(test_name, test_name + ".old")
+    wl(comment="This file is generated by dcache1.py (run that script manually)")
+    wl('#include "WALLY-init-lib.h"')
+    wl('main:')
+    
+    # excercise all 4 D$ ways. If they're not all full, it uses the first empty.
+    # So we are sure all 4 ways are exercised.
+    for i in range(dcache_num_ways):
+        wl(comment=f"start way test #{i+1}")
+        wl(f'li t0, {hex(mem_addr)}')
+        wl(f'.align 6')                # start at i$ set boundary. 6 lsb bits are zero.
+        wl(comment=f"i$ boundary, way test #{i+1}")
+        write_repro_instrs()
+        mem_addr += dcache_way_size_in_bytes  # so that we excercise a new D$ way.
+    
+    wl("j done")

tests/coverage/dcache2.S

@@ -0,0 +1,49 @@
+///////////////////////////////////////////
+// dcache2.S
+//
+// Written: avercruysse@hmc.edu 18 April 2023
+//
+// Purpose: Test Coverage for D$
+//          (for all 4 cache ways, trigger a FlushStage while SetDirtyWay=1)        
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+#include "WALLY-init-lib.h"
+main:
+        // way 0 
+        li t0, 0x80100770
+        sd zero, 0(t0)
+        sd zero, 1(t0)
+
+        // way 1 
+        li t0, 0x80101770
+        sd zero, 0(t0)
+        sd zero, 1(t0)
+
+        // way 2 
+        li t0, 0x80102770
+        sd zero, 0(t0)        
+        sd zero, 1(t0)
+
+        // way 3
+        li t0, 0x80103770
+        sd zero, 0(t0)
+        sd zero, 1(t0)
+        
+        j done

tests/coverage/fpu.S

@@ -31,6 +31,44 @@ main:
     #bseti t0, zero, 14  # turn on FPU
     csrs mstatus, t0
 
+    #Pull denormalized FP number from memory and pass it to fclass.S for coverage
+    la t0, TestData1
+    flw ft0, 0(t0)
+    fclass.s t1, ft0
+
+    #Result Sign Test Coverage
+    la t0, TestData2
+    flw ft0, 0(t0)
+    flw ft1, 4(t0)
+    fadd.s ft2, ft0, ft1 #Adds coverage for inf as arg for FADD
+
+    flw ft2, 4(t0)
+    fmsub.s ft3, ft0, ft1, ft2 #Adds coverage for fmaAs or Z Sign Bit
+
+    #Adds Coverage for Flag fmaAs, fmaPs, YSNaN, ZSNaN
+    fmadd.s ft3, ft0, ft1, ft2
+
+    flw ft0, 8(t0)
+    fmadd.s ft3, ft0, ft1, ft2
+
+    flw ft1, 12(t0)
+    fmadd.s ft3, ft0, ft1, ft2
+
+    flw ft2, 12(t0)
+    flw ft1, 4(t0)
+    fmadd.s ft3, ft0, ft1, ft2
+
+    #Add Coverage for round lsbRes
+    flw ft0, 16(t0)
+    flw ft1, 4(t0)
+    fmadd.s ft3, ft0, ft1, ft2
+
+    #Fix BadNaNBox test on unpackinput Z
+    la t0, TestData2
+    flw ft3, 0(t0)
+    flw ft4, 0(t0)
+    fadd.s ft5, ft3, ft4
+
     # Test legal instructions not covered elsewhere
     flq ft0, 0(a0)
     flh ft0, 8(a0)
@@ -79,6 +117,10 @@ main:
     .word 0xc5000007    // Attempting to toggle (Op7 != 7) to 0 on line 97 in fctrl, not sure what instruction this works out to
     .word 0xe0101053    // toggling (Rs2D == 0) to 0 on line 139 in fctrl. Illegal Intsr (like fclass but incorrect rs2)
     .word 0xe0100053    // toggling (Rs2D == 0) to 0 on line 141 in fctrl. Illegal Intsr (like fmv but incorrect rs2)
+    .word 0x40500053    // toggling (Rs2D[4:2] == 0) to 0 on line 145 in fctrl. 
+    .word 0x40300053    // toggling SupportFmt2 to 0 on line 145 in fctrl.
+    .word 0x42100053    // toggling (Rs2D[1:0] != 1) to 0 on line 147 in fctrl. Illegal Instr
+    .word 0xf0100053    // toggling (Rs2D == 0) to 0 on line 143 in fctrl. Illegal Instr
 
     # Test illegal instructions are detected
     .word 0x00000007 // illegal floating-point load (bad Funct3)
@@ -94,3 +136,13 @@ main:
 
     j done
 
+.section .data
+.align 3
+TestData1:
+.int 0x00100000 #Denormalized FP number
+TestData2:
+.int 0x3f800000 #FP 1.0
+.word 0x7f800000 #INF
+.int 0xbf800000 #FP -1.0
+.int 0x7fa00000 #SNaN
+.int 0x3fffffff #OverFlow Test

tests/coverage/ifuCamlineWrite.S

@@ -0,0 +1,146 @@
+///////////////////////////////////////////
+// ifuCamlineWrite.S
+//
+// Written: Miles Cook <mdcook@g.hmc.edu> and Kevin Box <kbox@g.hmc.edu> 4/17
+// 
+// Acknowledgements: The pagetable and outline for this test was written by Manuel Mendoza 
+//                   and Noah Limpert. 
+//
+// Purpose: Test coverage for TLBCamlines in IFU 
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// load code to initalize stack, handle interrupts, terminate
+
+#include "WALLY-init-lib.h"
+
+# run-elf.bash find this in project description
+main:
+    # Page table root address at 0x80010000
+    li t5, 0x9000000000080010
+    csrw satp, t5
+
+    # switch to supervisor mode
+    li a0, 1   
+    ecall
+
+    li t0, 0x80015000 # base addr 
+
+    li t2, 0       # i = 0
+    li t3, 33     # Max amount of Loops = 32
+
+loop: bge t2, t3, finished   # exit loop if i >= loops
+    li t4, 0x1000
+    li t1, 0x00008067 # load in jalr
+    sw t1, 0 (t0)  
+    fence.I
+    jalr t0   
+    add t0, t0, t4
+    addi t2, t2, 1
+    j loop
+
+finished:
+    j done
+
+.data
+
+.align 16
+# Page table situated at 0x80010000
+pagetable: 
+    .8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong
+
+.align 12
+    .8byte 0x0000000000000000
+    .8byte 0x00000000200048C1
+    .8byte 0x00000000200048C1
+    
+
+.align 12
+    .8byte 0x0000000020004CC1
+    //.8byte 0x00000200800CF// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed?
+
+.align 12
+    #80000000
+    .8byte 0x200000CF
+    .8byte 0x200004CF
+    .8byte 0x200008CF
+    .8byte 0x20000CCF
+
+    .8byte 0x200010CF
+    .8byte 0x200014CF
+    .8byte 0x200018CF
+    .8byte 0x20001CCF
+
+    .8byte 0x200020CF
+    .8byte 0x200024CF
+    .8byte 0x200028CF
+    .8byte 0x20002CCF
+
+    .8byte 0x200030CF
+    .8byte 0x200034CF
+    .8byte 0x200038CF
+    .8byte 0x20003CCF
+
+    .8byte 0x200040CF
+    .8byte 0x200044CF
+    .8byte 0x200048CF
+    .8byte 0x20004CCF
+
+    .8byte 0x200050CF
+    .8byte 0x200054CF
+    .8byte 0x200058CF
+    .8byte 0x20005CCF
+
+    .8byte 0x200060CF
+    .8byte 0x200064CF
+    .8byte 0x200068CF
+    .8byte 0x20006CCF
+
+    .8byte 0x200070CF
+    .8byte 0x200074CF
+    .8byte 0x200078CF
+    .8byte 0x20007CCF
+    
+    .8byte 0x200080CF
+    .8byte 0x200084CF
+    .8byte 0x200088CF
+    .8byte 0x20008CCF
+
+    .8byte 0x200090CF
+    .8byte 0x200094CF
+    .8byte 0x200098CF
+    .8byte 0x20009CCF
+
+    .8byte 0x200100CF
+    .8byte 0x200104CF
+    .8byte 0x200108CF
+    .8byte 0x20010CCF
+
+    .8byte 0x200110CF
+    .8byte 0x200114CF
+    .8byte 0x200118CF
+    .8byte 0x20011CCF
+
+    .8byte 0x200120CF
+    .8byte 0x200124CF
+    .8byte 0x200128CF
+    .8byte 0x20012CCF
+
+    .8byte 0x200130CF
+    .8byte 0x200134CF

tests/coverage/lsu.S

@@ -30,4 +30,4 @@ main:
 
     sfence.vma x0, x0 // sfence.vma to assert TLBFlush
 
-    j done
+    j done

tests/coverage/pmpcfg.S

@@ -0,0 +1,81 @@
+// pmpcfg part 1
+// Kevin Wan, kewan@hmc.edu, 4/18/2023
+// Liam Chalk, lchalk@hmc.edu, 4/19/2023
+// locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR. 
+// See the next part in pmpcfg1.S
+
+#include "WALLY-init-lib.h" 
+main: 
+
+    li t0, 0x90000000
+    csrw pmpaddr0, t0
+    li t0, 0x00000017
+    csrw pmpcfg0, t0
+
+    li t0, 0x90000000
+    csrw pmpaddr2, t0
+    li t0, 0x00000017
+    csrw pmpcfg2, t0
+
+    li t0, 0x90000000
+    csrw pmpaddr0, t0
+    li t0, 0x00000017
+    csrw pmpcfg1, t0
+
+    li t0, 0x90000000
+    csrw pmpaddr0, t0
+    li t0, 0x00000017
+    csrw pmpcfg2, t0
+
+    li t0, 0x90000000
+    csrw pmpaddr0, t0
+    li t0, 0x00000017
+    csrw pmpcfg3, t0
+
+    li t0, 0x90000000
+    csrw pmpaddr1, t0
+    li t0, 0x00000017
+    csrw pmpcfg1, t0
+
+    li t0, 0x90000000
+    csrw pmpaddr1, t0
+    li t0, 0x00000017
+    csrw pmpcfg2, t0
+
+    li t0, 0x90000000
+    csrw pmpaddr1, t0
+    li t0, 0x00000017
+    csrw pmpcfg3, t0
+
+    li t0, 0x8800000000000000
+    csrw pmpcfg2, t0
+    li t0, 0x88000000000000
+    csrw pmpcfg2, t0
+    li t0, 0x880000000000
+    csrw pmpcfg2, t0
+    li t0, 0x8800000000
+    csrw pmpcfg2, t0
+    li t0, 0x88000000
+    csrw pmpcfg2, t0
+    li t0, 0x880000
+    csrw pmpcfg2, t0
+    li t0, 0x8800
+    csrw pmpcfg2, t0
+    li t0, 0x88
+    csrw pmpcfg2, t0
+    li t0, 0x8800000000000000
+    csrw pmpcfg0, t0
+    li t0, 0x88000000000000
+    csrw pmpcfg0, t0
+    li t0, 0x880000000000
+    csrw pmpcfg0, t0
+    li t0, 0x8800000000
+    csrw pmpcfg0, t0
+    li t0, 0x88000000
+    csrw pmpcfg0, t0
+    li t0, 0x880000
+    csrw pmpcfg0, t0
+    li t0, 0x8800
+    csrw pmpcfg0, t0
+
+    j done

tests/coverage/pmpcfg1.S

@@ -0,0 +1,48 @@
+// another set of pmpcfg tests. A new file is made because pmpcfg register fields are 
+// locked forever after writing 1 to the lock bit for the first time. 
+
+// Kevin Wan, kewan@hmc.edu, 4/13/2023
+// This set tests locking the pmpXcfg fields in descending order again, without setting the TOR bits. 
+// for the other part of the tests, see pmpcfg.S
+
+#include "WALLY-init-lib.h" 
+main: 
+    li t0, 0x800
+    csrw pmpcfg0, t0
+    li t0, 0x8000000
+    csrw pmpcfg0, t0
+
+    li t0, 0x8000000000000000
+    csrw pmpcfg2, t0
+    li t0, 0x80000000000000
+    csrw pmpcfg2, t0
+    li t0, 0x800000000000
+    csrw pmpcfg2, t0
+    li t0, 0x8000000000
+    csrw pmpcfg2, t0
+    li t0, 0x80000000
+    csrw pmpcfg2, t0
+    li t0, 0x800000
+    csrw pmpcfg2, t0
+    li t0, 0x8000
+    csrw pmpcfg2, t0
+    li t0, 0x80
+    csrw pmpcfg2, t0
+    li t0, 0x8000000000000000
+    csrw pmpcfg0, t0
+    li t0, 0x80000000000000
+    csrw pmpcfg0, t0
+    li t0, 0x800000000000
+    csrw pmpcfg0, t0
+    li t0, 0x8000000000
+    csrw pmpcfg0, t0
+    li t0, 0x80000000
+    csrw pmpcfg0, t0
+    li t0, 0x800000
+    csrw pmpcfg0, t0
+    li t0, 0x8000
+    csrw pmpcfg0, t0
+
+
+
+    j done

tests/coverage/pmpcfg2.S

@@ -0,0 +1,12 @@
+// pmpcfg part 3
+// Kevin Wan, kewan@hmc.edu, 4/18/2023
+// locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR. 
+// See the next part in pmpcfg1.S
+
+#include "WALLY-init-lib.h" 
+main: 
+    li t0, 0x80
+    csrw pmpcfg0, t0
+
+
+    j done

tests/coverage/priv.S

@@ -142,6 +142,66 @@ main:
     # Test writes to floating point CSRs
     csrw frm, t0
     csrw fflags, t0
+    
+    # CSRC MCOUNTEREN Register
+    # Go to machine mode
+    li a0, 3
+    ecall
+    # Activate HPM3
+    li t0, -1
+    csrw mcounteren, t0
+    csrw scounteren, t0
+
+    # Go to supervisor
+    li a0, 1
+    ecall
+    #try to write to HPMs
+    csrw 333, t0
+    #go to user mode
+    li a0, 0
+    ecall
+    csrr t0, hpmcounter22
+
+    # setting registers bits to 0
+    li a0, 3 # back to machine mode
+    ecall
+    li t0, 0
+    csrw mcounteren, t0
+    csrw scounteren, t0
+
+    # Write to satp when status.TVM is 1 from machine mode
+    bseti t0, zero, 20 
+    csrs mstatus, t0
+
+    csrw satp, t0
+
+
+
+    # Test checking privilege for reading counters (using counter 22 as an example)
+
+    # Go to machine mode
+    li a0, 3
+    ecall
+
+    # Set SCOUNTEREN to all 0s, MCOUNTEREN to all 1s
+    li t0, 0
+    csrw scounteren, t0
+    li t1, -1
+    csrw mcounteren, t1
+
+
+    # Go to supervisor mode
+    li a0, 1
+    ecall
+
+    # try to read from HPM22
+    csrr t0, hpmcounter22
+
+    # go to user mode
+    li a0, 0
+    ecall
+
+    csrr t0, hpmcounter22
 
     j done
 

tests/coverage/tlbASID.S

@@ -0,0 +1,133 @@
+///////////////////////////////////////////
+// tlbASID.S
+//
+// Written: mmendozamanriquez@hmc.edu 4 April 2023
+//          nlimpert@hmc.edu
+//
+// Purpose: Test coverage for LSU
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// load code to initalize stack, handle interrupts, terminate
+
+#include "WALLY-init-lib.h"
+
+# run-elf.bash find this in project description
+main:
+    # Page table root address at 0x80010000
+    li t5, 0x9000000000080080 // try making asid = 0. 
+    csrw satp, t5
+
+    # sfence.vma x0, x0
+
+    # switch to supervisor mode
+    li a0, 1   
+    ecall
+
+    li t0, 0xC0000000
+
+    li t2, 0             # i = 0
+    li t5, 0            # j = 0 // now use as a counter for new asid loop 
+    li t3, 32     # Max amount of Loops = 32
+
+loop: bge t2, t3, nASID   # exit loop if i >= loops
+    lw t1, 0(t0)
+    li t4, 0x1000
+    add t0, t0, t4
+    addi t2, t2, 1
+    j loop
+
+nASID: bne t5, zero, finished
+    li a0, 3   // go
+    ecall
+    li t5, 0x9000100000080080 // try making asid = 1 
+    csrw satp, t5
+    li a0, 1   
+    ecall
+    li t2, 0
+    li t0, 0xC0000000
+    li t5, 1 // make this not zero. 
+    j loop
+
+
+finished:
+    j done
+
+.data
+.align 19
+# level 3 Page table situated at 0x8008 0000, should point to 8008,1000
+pagetable: 
+    .8byte 0x200204C1
+    
+.align 12 // level 2 page table, contains direction to a gigapageg
+    .8byte 0x0
+    .8byte 0x0
+    .8byte 0x200000CF // gigapage that starts at 8000 0000 goes to C000 0000
+    .8byte 0x200208C1 // pointer to next page table entry at 8008 2000
+
+.align 12 // level 1 page table, points to level 0 page table
+    .8byte 0x20020CC1
+
+.align 12 // level 0 page table, points to address C000 0000 // FOR NOW ALL OF THESE GO TO 8 instead of C cause they start with 2
+    .8byte 0x200000CF // access xC000 0000
+    .8byte 0x200004CF // access xC000 1000
+    .8byte 0x200008CF // access xC000 2000
+    .8byte 0x20000CCF // access xC000 3000
+
+    .8byte 0x200010CF // access xC000 4000
+    .8byte 0x200014CF
+    .8byte 0x200018CF
+    .8byte 0x20001CCF
+
+    .8byte 0x200020CF // access xC000 8000
+    .8byte 0x200024CF
+    .8byte 0x200028CF
+    .8byte 0x20002CCF
+
+    .8byte 0x200030CF // access xC000 C000
+    .8byte 0x200034CF
+    .8byte 0x200038CF
+    .8byte 0x20003CCF
+
+    .8byte 0x200040CF // access xC001 0000
+    .8byte 0x200044CF
+    .8byte 0x200048CF
+    .8byte 0x20004CCF
+
+    .8byte 0x200050CF // access xC001 4000
+    .8byte 0x200054CF
+    .8byte 0x200058CF
+    .8byte 0x20005CCF
+
+    .8byte 0x200060CF // access xC001 8000
+    .8byte 0x200064CF
+    .8byte 0x200068CF
+    .8byte 0x20006CCF
+
+    .8byte 0x200070CF // access xC001 C000
+    .8byte 0x200074CF
+    .8byte 0x200078CF
+    .8byte 0x20007CCF
+
+    .8byte 0x200080CF // access xC002 0000
+    .8byte 0x200084CF
+    .8byte 0x200088CF
+    .8byte 0x20008CCF
+
+    

tests/coverage/tlbGLB.S

@@ -0,0 +1,134 @@
+///////////////////////////////////////////
+// tlbGLB.S
+//
+// Written: mmendozamanriquez@hmc.edu 4 April 2023
+//          nlimpert@hmc.edu
+//
+// Purpose: coverage for the global check. 
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+
+// load code to initalize stack, handle interrupts, terminate
+
+#include "WALLY-init-lib.h"
+
+# run-elf.bash find this in project description
+main:
+    # Page table root address at 0x80010000
+    li t5, 0x9000000000080080 // try making asid = 0. 
+    csrw satp, t5
+
+    # sfence.vma x0, x0
+
+    # switch to supervisor mode
+    li a0, 1   
+    ecall
+
+    li t0, 0xC0000000
+
+    li t2, 0             # i = 0
+    li t5, 0            # j = 0 // now use as a counter for new asid loop 
+    li t3, 32     # Max amount of Loops = 32
+
+loop: bge t2, t3, nASID   # exit loop if i >= loops
+    lw t1, 0(t0)
+    li t4, 0x1000
+    add t0, t0, t4
+    addi t2, t2, 1
+    j loop
+
+nASID: bne t5, zero, finished
+    li a0, 3   // go
+    ecall
+    li t5, 0x9000100000080080 // try making asid = 1 
+    csrw satp, t5
+    li a0, 1   
+    ecall
+    li t2, 0
+    li t0, 0xC0000000
+    li t5, 1 // make this not zero. 
+    j loop
+
+
+finished:
+    j done
+
+.data
+.align 19
+# level 3 Page table situated at 0x8008 0000, should point to 8008,1000
+pagetable: 
+    .8byte 0x200204C1
+    
+.align 12 // level 2 page table, contains direction to a gigapageg
+    .8byte 0x0
+    .8byte 0x0
+    .8byte 0x200000CF // gigapage that starts at 8000 0000 goes to C000 0000
+    .8byte 0x200208C1 // pointer to next page table entry at 8008 2000
+
+.align 12 // level 1 page table, points to level 0 page table
+    .8byte 0x20020CE1
+
+.align 12 // level 0 page table, points to address C000 0000 // FOR NOW ALL OF THESE GO TO 8 instead of C cause they start with 2
+    .8byte 0x200000CF // access xC000 0000
+    .8byte 0x200004CF // access xC000 1000
+    .8byte 0x200008CF // access xC000 2000
+    .8byte 0x20000CCF // access xC000 3000
+
+    .8byte 0x200010EF // access xC000 4000
+    .8byte 0x200014EF
+    .8byte 0x200018EF
+    .8byte 0x20001CEF
+
+    .8byte 0x200020EF // access xC000 8000
+    .8byte 0x200024EF
+    .8byte 0x200028EF
+    .8byte 0x20002CEF
+
+    .8byte 0x200030EF // access xC000 C000
+    .8byte 0x200034EF
+    .8byte 0x200038EF
+    .8byte 0x20003CEF
+
+    .8byte 0x200040EF // access xC001 0000
+    .8byte 0x200044EF
+    .8byte 0x200048EF
+    .8byte 0x20004CEF
+
+    .8byte 0x200050EF // access xC001 4000
+    .8byte 0x200054EF
+    .8byte 0x200058EF
+    .8byte 0x20005CEF
+
+    .8byte 0x200060EF // access xC001 8000
+    .8byte 0x200064EF
+    .8byte 0x200068EF
+    .8byte 0x20006CEF
+
+    .8byte 0x200070EF // access xC001 C000
+    .8byte 0x200074eF
+    .8byte 0x200078EF
+    .8byte 0x20007CEF
+
+    .8byte 0x200080EF // access xC002 0000
+    .8byte 0x200084EF
+    .8byte 0x200088EF
+    .8byte 0x20008CEF
+
+    

tests/coverage/tlbKP.S

@@ -0,0 +1,143 @@
+///////////////////////////////////////////
+// lsu_test.S
+//
+// Written: mmendozamanriquez@hmc.edu 4 April 2023
+//          nlimpert@hmc.edu
+//
+// Purpose: Test coverage for LSU
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// load code to initalize stack, handle interrupts, terminate
+
+#include "WALLY-init-lib.h"
+
+# run-elf.bash find this in project description
+main:
+    # Page table root address at 0x80010000
+    li t5, 0x9000000000080010
+    csrw satp, t5
+
+    # sfence.vma x0, x0
+
+    # switch to supervisor mode
+    li a0, 1   
+    ecall
+
+    li t0, 0x80015000
+
+    li t2, 0             # i = 0
+    li t3, 33     # Max amount of Loops = 32
+
+loop: bge t2, t3, finished   # exit loop if i >= loops
+    lw t1, 0(t0)
+    li t4, 0x1000
+    add t0, t0, t4
+    addi t2, t2, 1
+    j loop
+
+finished:
+    j done
+
+.data
+
+.align 16
+# Page table situated at 0x80010000
+pagetable: 
+    .8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong
+
+.align 12
+    .8byte 0x0000000000000000
+    .8byte 0x00000000200048C1
+    .8byte 0x00000000200048C1
+    
+
+.align 12
+    .8byte 0x0000000020004CC1
+    //.8byte 0x00000200800CF// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed?
+
+.align 12
+    #80000000
+    .8byte 0x200000CF
+    .8byte 0x200004CF
+    .8byte 0x200008CF
+    .8byte 0x20000CCF
+
+    .8byte 0x200010CF
+    .8byte 0x200014CF
+    .8byte 0x200018CF
+    .8byte 0x20001CCF
+
+    .8byte 0x200020CF
+    .8byte 0x200024CF
+    .8byte 0x200028CF
+    .8byte 0x20002CCF
+
+    .8byte 0x200030CF
+    .8byte 0x200034CF
+    .8byte 0x200038CF
+    .8byte 0x20003CCF
+
+    .8byte 0x200040CF
+    .8byte 0x200044CF
+    .8byte 0x200048CF
+    .8byte 0x20004CCF
+
+    .8byte 0x200050CF
+    .8byte 0x200054CF
+    .8byte 0x200058CF
+    .8byte 0x20005CCF
+
+    .8byte 0x200060CF
+    .8byte 0x200064CF
+    .8byte 0x200068CF
+    .8byte 0x20006CCF
+
+    .8byte 0x200070CF
+    .8byte 0x200074CF
+    .8byte 0x200078CF
+    .8byte 0x20007CCF
+    
+    .8byte 0x200080CF
+    .8byte 0x200084CF
+    .8byte 0x200088CF
+    .8byte 0x20008CCF
+
+    .8byte 0x200090CF
+    .8byte 0x200094CF
+    .8byte 0x200098CF
+    .8byte 0x20009CCF
+
+    .8byte 0x200100CF
+    .8byte 0x200104CF
+    .8byte 0x200108CF
+    .8byte 0x20010CCF
+
+    .8byte 0x200110CF
+    .8byte 0x200114CF
+    .8byte 0x200118CF
+    .8byte 0x20011CCF
+
+    .8byte 0x200120CF
+    .8byte 0x200124CF
+    .8byte 0x200128CF
+    .8byte 0x20012CCF
+
+    .8byte 0x200130CF
+    .8byte 0x200134CF

tests/coverage/tlbM3.S

@@ -0,0 +1,155 @@
+///////////////////////////////////////////
+// tlbKP.S
+//
+// Written: mmendozamanriquez@hmc.edu 4 April 2023
+//          nlimpert@hmc.edu
+//
+// Purpose: Test coverage for LSU
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// load code to initalize stack, handle interrupts, terminate
+
+#include "WALLY-init-lib.h"
+
+# run-elf.bash find this in project description
+main:
+    # Page table root address at 0x80010000
+    li t5, 0x9000000000080010
+    csrw satp, t5
+
+    # sfence.vma x0, x0
+
+    # switch to supervisor mode
+    li a0, 1   
+    ecall
+
+    li t0, 0x1000
+
+    li t2, 0             # i = 0
+    li t3, 64     # Max amount of Loops = 32
+    li t4, 0x1000
+
+loop: bge t2, t3, interim  # exit loop if i >= loops
+    lw t1, 0(t0)
+    # sfence.vma x0, x0
+    add t0, t0, t4
+    addi t2, t2, 1
+    j loop
+
+interim:
+    li t0, 0xFFFFFFFF000
+    li t2, 0             # i = 0
+     
+
+loop2:bge t2, t3, finished  # exit loop if i >= loops
+    lw t1, 0(t0)
+    add t0, t0, t4
+    addi t2, t2, 1
+    j loop2
+
+finished:
+    j done
+
+.data
+
+.align 16
+# Page table situated at 0x80010000
+pagetable: 
+    .8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong
+
+.align 12
+    .8byte 0x00000000200048C1
+    .8byte 0x00000000200048C1
+    .8byte 0x00000000200048C1
+    
+
+.align 12
+    .8byte 0x0000000020004CC1
+    //.8byte 0x00000200800CF// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed?
+
+.align 12
+    #80000000
+    .8byte 0x200000CF
+    .8byte 0x200004CF
+    .8byte 0x200008CF
+    .8byte 0x20000CCF
+
+    .8byte 0x200010CF
+    .8byte 0x200014CF
+    .8byte 0x200018CF
+    .8byte 0x20001CCF
+
+    .8byte 0x200020CF
+    .8byte 0x200024CF
+    .8byte 0x200028CF
+    .8byte 0x20002CCF
+
+    .8byte 0x200030CF
+    .8byte 0x200034CF
+    .8byte 0x200038CF
+    .8byte 0x20003CCF
+
+    .8byte 0x200040CF
+    .8byte 0x200044CF
+    .8byte 0x200048CF
+    .8byte 0x20004CCF
+
+    .8byte 0x200050CF
+    .8byte 0x200054CF
+    .8byte 0x200058CF
+    .8byte 0x20005CCF
+
+    .8byte 0x200060CF
+    .8byte 0x200064CF
+    .8byte 0x200068CF
+    .8byte 0x20006CCF
+
+    .8byte 0x200070CF
+    .8byte 0x200074CF
+    .8byte 0x200078CF
+    .8byte 0x20007CCF
+    
+    .8byte 0x200080CF
+    .8byte 0x200084CF
+    .8byte 0x200088CF
+    .8byte 0x20008CCF
+
+    .8byte 0x200090CF
+    .8byte 0x200094CF
+    .8byte 0x200098CF
+    .8byte 0x20009CCF
+
+    .8byte 0x2000A0CF
+    .8byte 0x2000A4CF
+    .8byte 0x2000A8CF
+    .8byte 0x2000ACCF
+
+    .8byte 0x2000B0CF
+    .8byte 0x2000B4CF
+    .8byte 0x2000B8CF
+    .8byte 0x2000BCCF
+
+    .8byte 0x2000C0CF
+    .8byte 0x2000C4CF
+    .8byte 0x2000C8CF
+    .8byte 0x2000CCCF
+
+    .8byte 0x2000D0CF
+    .8byte 0x2000D4CF

tests/coverage/tlbMP.S

@@ -0,0 +1,163 @@
+///////////////////////////////////////////
+// tlbMP.S
+//
+// Written: mmendozamanriquez@hmc.edu 4 April 2023
+//          nlimpert@hmc.edu
+//
+// Purpose: Test coverage for LSU
+//
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+// load code to initalize stack, handle interrupts, terminate
+
+#include "WALLY-init-lib.h"
+
+# run-elf.bash find this in project description
+main:
+    # Page table root address at 0x80010000
+    li t5, 0x9000000000080010
+    csrw satp, t5
+
+    # sfence.vma x0, x0
+
+    # switch to supervisor mode
+    li a0, 1   
+    ecall
+    li t5, 0 
+    li t0, 0x84000000 // go to first megapage
+    li t4, 0x1000 // put this outside the loop.
+    li t2, 0      # i = 0
+    li t3, 32     # Max amount of Loops = 16
+
+loop: bge t2, t3, lKP   # exit loop if i >= loops
+    lw t1, 0(t0)
+    add t0, t0, t4
+    addi t2, t2, 1
+    j loop
+
+lKP: bne t5, zero, finished
+    li t0, 0x80000000 
+    slli t4, t4, 9
+    addi t5, t5, 1
+    li t2, 0
+    j loop
+
+finished:
+    j done
+
+.data
+
+.align 16
+# Page table situated at 0x80010000
+pagetable: 
+    .8byte 0x200044C1
+
+.align 12
+    .8byte 0x00000000200048C1
+    .8byte 0x00000000200048C1
+    .8byte 0x00000000200048C1
+    
+
+.align 12 // megapages starting at 8000 0000 going to 8480 0000  (32*2 MiB beyond that)
+
+    .8byte 0x200000CF // access 8000,0000
+    .8byte 0x200800CF // access 8020,0000 
+    .8byte 0x201000CF // acesss 8040,0000
+    .8byte 0x201800CF // acesss 8060,0000
+
+    .8byte 0x202000CF // access 8080,0000
+    .8byte 0x202800CF // access 80A0,0000
+    .8byte 0x203000CF // access 80C0,0000
+    .8byte 0x203800CF // access 80E0,0000
+
+    .8byte 0x204000CF // access 8100,0000
+    .8byte 0x204800CF 
+    .8byte 0x205000CF 
+    .8byte 0x205800CF 
+
+    .8byte 0x206000CF // access 8180,0000
+    .8byte 0x206800CF 
+    .8byte 0x207000CF 
+    .8byte 0x207800CF 
+
+    .8byte 0x208000CF // access 8200,0000
+    .8byte 0x208800CF 
+    .8byte 0x209000CF 
+    .8byte 0x209800CF 
+
+    .8byte 0x20A000CF // access 8280,0000
+    .8byte 0x20A800CF 
+    .8byte 0x20B000CF 
+    .8byte 0x20B800CF 
+
+    .8byte 0x20C000CF // access 8300,0000
+    .8byte 0x20C800CF 
+    .8byte 0x20D000CF 
+    .8byte 0x20D800CF
+
+    .8byte 0x20E000CF // access 8380,0000
+    .8byte 0x20E800CF 
+    .8byte 0x20F000CF 
+    .8byte 0x20F800CF
+
+    .8byte 0x20004CC1
+     // Kilopage entry, for addresses from 8400, 0000 to 841F, FFFF
+                      // point to ... 
+
+.align 12 // should start at 84000000 
+    .8byte 0x210000CF
+    .8byte 0x210004CF
+    .8byte 0x210008CF
+    .8byte 0x21000CCF
+
+    .8byte 0x210010CF
+    .8byte 0x210014CF
+    .8byte 0x210018CF
+    .8byte 0x21001CCF
+
+    .8byte 0x210020CF
+    .8byte 0x210024CF
+    .8byte 0x210028CF
+    .8byte 0x21002CCF
+
+    .8byte 0x210030CF
+    .8byte 0x210034CF
+    .8byte 0x210038CF
+    .8byte 0x21003CCF
+
+    .8byte 0x210040CF
+    .8byte 0x210044CF
+    .8byte 0x210048CF
+    .8byte 0x21004CCF
+
+    .8byte 0x210050CF
+    .8byte 0x210054CF
+    .8byte 0x210058CF
+    .8byte 0x21005CCF
+
+    .8byte 0x210060CF
+    .8byte 0x210064CF
+    .8byte 0x210068CF
+    .8byte 0x21006CCF
+
+    .8byte 0x210070CF
+    .8byte 0x210074CF
+    .8byte 0x210078CF
+    .8byte 0x21007CCF
+

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-csr-permission-s-01.reference_output

@@ -384,641 +384,3 @@
 00000002 # S mode read from mhpmevent31 with illegal instruction
 00000bad
 00000009 # ecall from terminating tess from S mode
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-csr-permission-u-01.reference_output

@@ -315,710 +315,3 @@
 00000002 # U mode read from mhpmevent31 with illegal instruction
 00000bad
 00000008 # ecall from terminating tests in U mode
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mmu-sv32-01.reference_output

@@ -49,976 +49,3 @@ beef0099 # Read success from translated address when mprv=1, mpp=S and priv mode
 00000009 # ecall from going straight back to m mode to access mstatus
 00000000 # previous zeroed out value of mprv
 0000000b # ecall from terminating tests in m mode
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-mmu-sv32-svadu-01.reference_output

@@ -0,0 +1,47 @@
+0000000b
+beef0055
+beef0033
+beef0077
+beef0099
+beef0440
+11100393
+00008067
+beef0055
+beef0099
+0000000d
+00000bad
+0000000f
+0000000d
+00000bad
+0000000d
+00000bad
+00000111
+00000009
+0000000d
+00000bad
+0000000c
+00000bad
+beef0033
+00000008
+beef0077
+0000000c
+00000bad
+0000000d
+00000bad
+0000000d
+00000bad
+beef0440
+beef0110
+0000000f
+0000000c
+00000bad
+beef0770 # Test 8.3.1.3.5: check successful read/write when A=0 and SVADU=1
+beef0aa0 # Test 8.3.1.3.6: check successful read/write when D=0 and SVADU=1
+beef0077 # Test 12.3.1.4.1: successful read back of saved value with new memory mapping
+00000009 # Test 12.3.1.5.1: ecall from going to m mode from s mode
+00000000 # previous value of mprv before being set
+beef0099 # Read success from translated address when mprv=1, mpp=S and priv mode = m
+0000000b # Test 12.3.1.5.2: ecall from going to S mode from m mode
+00000009 # ecall from going straight back to m mode to access mstatus
+00000000 # previous zeroed out value of mprv
+0000000b # ecall from terminating tests in m mode

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pma-01.reference_output

@@ -61,964 +61,3 @@ beef00c1
 00000001
 00000bad
 0000000b
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef

tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-pmp-01.reference_output

@@ -27,998 +27,3 @@
 00000bad
 00000111
 00000009
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef