From 356254272856af6829f45dd2ab97b8e06bf33b35 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 21 Dec 2022 12:39:09 -0800
Subject: [PATCH 1/3] comment cleanup

---
 pipelined/src/privileged/csrs.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/pipelined/src/privileged/csrs.sv b/pipelined/src/privileged/csrs.sv
index cf1a4d2f3..7d3aeeb94 100644
--- a/pipelined/src/privileged/csrs.sv
+++ b/pipelined/src/privileged/csrs.sv
@@ -102,7 +102,7 @@ module csrs #(parameter
       case (CSRAdrM) 
         SSTATUS:   CSRSReadValM = SSTATUS_REGW;
         STVEC:     CSRSReadValM = STVEC_REGW;
-        SIP:       CSRSReadValM = {{(`XLEN-12){1'b0}}, MIP_REGW & 12'h222 & MIDELEG_REGW}; // only read supervisor fields  // *** and with MIDELEG instead of 222
+        SIP:       CSRSReadValM = {{(`XLEN-12){1'b0}}, MIP_REGW & 12'h222 & MIDELEG_REGW}; // only read supervisor fields  
         SIE:       CSRSReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW & 12'h222}; // only read supervisor fields
         SSCRATCH:  CSRSReadValM = SSCRATCH_REGW;
         SEPC:      CSRSReadValM = SEPC_REGW;

From a5dc09c97f42ae89c98f2cb1b006cedf715fa475 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 21 Dec 2022 13:57:28 -0800
Subject: [PATCH 2/3] Added assertion about atomics needing caches

---
 pipelined/testbench/testbench.sv | 1 +
 1 file changed, 1 insertion(+)

diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv
index 030f348d5..e67ab1d32 100644
--- a/pipelined/testbench/testbench.sv
+++ b/pipelined/testbench/testbench.sv
@@ -484,6 +484,7 @@ module riscvassertions;
     assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS) else $error("Dcache and Icache requires DBUS.");
     assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
     assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
+    assert (`DCACHE | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally.");
     assert (`IDIV_ON_FPU == 0 | `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED");
   end
 

From b3ff4fe02e62e636b76b8f05c482f3bc0ba0c25c Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 21 Dec 2022 22:13:05 -0600
Subject: [PATCH 3/3] CacheEn enables reading or writing the cache memory
 arrays.  This is only disabled if we have a stall while in the ready state
 and we don't have a cache miss.  This is a cache hit, but we are stalled.

---
 pipelined/src/cache/cachefsm.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv
index 22f943da6..a8ba78564 100644
--- a/pipelined/src/cache/cachefsm.sv
+++ b/pipelined/src/cache/cachefsm.sv
@@ -185,6 +185,6 @@ module cachefsm
                   resetDelay;
 
   assign SelFetchBuffer = CurrState == STATE_WRITE_LINE | CurrState == STATE_READ_HOLD;
-  assign CacheEn = (CurrState == STATE_READY & ~Stall | CacheStall) | (CurrState != STATE_READY) | reset;
+  assign CacheEn = (CurrState == STATE_READY  & (~Stall | FlushCache | AnyMiss)) | (CurrState != STATE_READY) | reset;
                        
 endmodule // cachefsm