Modified the mmu to not mux the lower 12 bits of the physical address and instead directly

assign from the input non translated virtual address.  Since the lower bits never change there is
no reason to place these lower bits on a longer critical path.
The cache and lsu were previously using the lower bits from the virtual address rather than
the physical address.  This change will allow us to keep the shorter critical path and
reduce the complexity of the lsu, ifu, and cache drawings.

pipelined/src/cache/cache.sv

@@ -39,7 +39,6 @@ module cache #(parameter integer LINELEN,
    input logic				   InvalidateCacheM,
    input logic [11:0]		   NextAdr, // virtual address, but we only use the lower 12 bits.
    input logic [`PA_BITS-1:0]  PAdr, // physical address
-   input logic [11:0]		   NoTranAdr, // physical or virtual address   
    input logic [`XLEN-1:0]	   FinalWriteData,
    output logic [`XLEN-1:0]	   ReadDataWord,
    output logic				   CacheCommitted,
@@ -120,7 +119,7 @@ module cache #(parameter integer LINELEN,
 
   mux3 #(INDEXLEN)
   AdrSelMux(.d0(NextAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
-			.d1(NoTranAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
+			.d1(PAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
 			.d2(FlushAdr),
 			.s(SelAdr),
 			.y(RAdr));
@@ -147,7 +146,7 @@ module cache #(parameter integer LINELEN,
     cachereplacementpolicy(.clk, .reset,
               .WayHit,
               .VictimWay,
-              .PAdr(NoTranAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
+              .PAdr(PAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
               .RAdr,
               .LRUWriteEn);
   end else begin:vict

pipelined/src/ifu/ifu.sv

@@ -269,7 +269,6 @@ module ifu (
 			 .FlushCache(1'b0),
 			 .NextAdr(PCNextFMux),
 			 .PAdr(PCPF),
-			 .NoTranAdr(PCFMux[11:0]),
 			 .CacheCommitted(),
 			 .InvalidateCacheM(InvalidateICacheM));
 

pipelined/src/lsu/lsu.sv

@@ -98,6 +98,7 @@ module lsu
   logic [1:0] 				   LsuRWM;
   logic [1:0] 				   PreLsuRWM;
   logic [2:0] 				   LsuFunct3M;
+  logic [7:0] 				   LsuFunct7M;
   logic [1:0] 				   LsuAtomicM;
 (* mark_debug = "true" *)  logic [`PA_BITS-1:0] 		   PreLsuPAdrM, LocalLsuBusAdr;
   logic [11:0] 				   PreLsuAdrE, LsuAdrE;  
@@ -146,6 +147,7 @@ module lsu
     // multiplex the outputs to LSU
     mux2 #(2) rwmux(MemRWM, {HPTWRead, 1'b0}, SelHPTW, PreLsuRWM);
     mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LsuFunct3M);
+    mux2 #(7) funct7mux(Funct7M, 7'b0, SelHPTW, LsuFunct7M);    
     mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LsuAtomicM);
     mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, PreLsuAdrE);
     mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, PreLsuPAdrM);
@@ -179,6 +181,7 @@ module lsu
     
     assign PreLsuRWM = MemRWM;
     assign LsuFunct3M = Funct3M;
+    assign LsuFunct7M = Funct7M;
     assign LsuAtomicM = AtomicM;
     assign PreLsuAdrE = IEUAdrE[11:0];
     assign PreLsuPAdrM = IEUAdrExtM;
@@ -301,7 +304,7 @@ module lsu
 			.NUMWAYS(`DCACHE_NUMWAYS), .DCACHE(1)) 
 	 dcache(.clk, .reset, .CPUBusy,
 			.RW(CacheableM ? LsuRWM : 2'b00), .FlushCache(FlushDCacheM), .Atomic(CacheableM ? LsuAtomicM : 2'b00), 
-			.NextAdr(LsuAdrE), .PAdr(LsuPAdrM), .NoTranAdr(PreLsuPAdrM[11:0]),
+			.NextAdr(LsuAdrE), .PAdr(LsuPAdrM), 
 			.FinalWriteData(FinalWriteDataM), .ReadDataWord(ReadDataWordM), .CacheStall(DCacheStall),
 			.CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), 
 			.IgnoreRequest, .CacheCommitted(DCacheCommittedM),
@@ -336,7 +339,7 @@ module lsu
 
   if (`A_SUPPORTED) begin : amo
     logic [`XLEN-1:0] AMOResult;
-    amoalu amoalu(.srca(ReadDataM), .srcb(WriteDataM), .funct(Funct7M), .width(LsuFunct3M[1:0]), 
+    amoalu amoalu(.srca(ReadDataM), .srcb(WriteDataM), .funct(LsuFunct7M), .width(LsuFunct3M[1:0]), 
                   .result(AMOResult));
     mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, LsuAtomicM[1], FinalAMOWriteDataM);
   end else

pipelined/src/mmu/mmu.sv

@@ -111,7 +111,12 @@ module mmu #(parameter TLB_ENTRIES = 8, // number of TLB Entries
   end
 
   // If translation is occuring, select translated physical address from TLB
-  mux2 #(`PA_BITS) addressmux(PAdr, TLBPAdr, Translate, PhysicalAddress);
+  // the lower 12 bits are the page offset. These are never changed from the orginal
+  // non translated address.
+  //mux2 #(`PA_BITS) addressmux(PAdr, TLBPAdr, Translate, PhysicalAddress);
+  mux2 #(`PA_BITS-12) addressmux(PAdr[`PA_BITS-1:12], TLBPAdr[`PA_BITS-1:12], Translate, PhysicalAddress[`PA_BITS-1:12]);
+  assign PhysicalAddress[11:0] = PAdr[11:0];
+  
   
   ///////////////////////////////////////////
   // Check physical memory accesses