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Merge pull request #311 from stineje/main

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Update some bugs in FPU
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Ross Thompson 2023-06-05 12:19:08 -04:00 committed by GitHub
commit f9ca6732b8
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2 changed files with 28 additions and 32 deletions
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7
src/fpu/fcvt.sv
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@ -65,7 +65,6 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
logic [P.CVTLEN:0] LzcInFull; // input to the Leading Zero Counter (priority encoder)
logic [P.LOGCVTLEN-1:0] LeadingZeros; // output from the LZC
// seperate OpCtrl for code readability
assign Signed = OpCtrl[0];
assign Int64 = OpCtrl[1];
@ -79,7 +78,6 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
else if (P.FPSIZES == 3 | P.FPSIZES == 4)
assign OutFmt = IntToFp ? Fmt : OpCtrl[1:0];
///////////////////////////////////////////////////////////////////////////
// negation
///////////////////////////////////////////////////////////////////////////
@ -143,7 +141,6 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
assign NewBias = ToInt ? (P.NE-1)'(1) : NewBiasToFp;
end
// select the old exponent
// int -> fp : largest bias + XLEN-1
// fp -> ??? : XExp
@ -185,13 +182,11 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
// oldexp - biasold - LeadingZeros + newbias
assign Ce = {1'b0, OldExp} - (P.NE+1)'(P.BIAS) - {{P.NE-P.LOGCVTLEN+1{1'b0}}, (LeadingZeros)} + {2'b0, NewBias};
// find if the result is dnormal or underflows
// - if Calculated expoenent is 0 or negitive (and the input/result is not exactaly 0)
// - can't underflow an integer to Fp conversion
assign ResSubnormUf = (~|Ce | Ce[P.NE])&~XZero&~IntToFp;
///////////////////////////////////////////////////////////////////////////
// shifter
///////////////////////////////////////////////////////////////////////////
@ -213,7 +208,6 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
else if (ResSubnormUf) ShiftAmt = (P.LOGCVTLEN)'(P.NF-1)+Ce[P.LOGCVTLEN-1:0];
else ShiftAmt = LeadingZeros;
///////////////////////////////////////////////////////////////////////////
// sign
///////////////////////////////////////////////////////////////////////////
@ -230,4 +224,3 @@ module fcvt import cvw::*; #(parameter cvw_t P) (
else Cs = Xs;
endmodule

5
tests/coverage/fpu.S
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@ -94,7 +94,10 @@ main:
fcvt.wu.q a0, ft3
fcvt.l.q a0, ft3
fcvt.lu.q a0, ft3
fcvt.l.s a0, ft0
fcvt.lu.s a0, ft0
fcvt.s.l ft0, t0
fcvt.s.lu ft0, t0
// Tests verfying that half and quad floating point convertion instructions are not supported by rv64gc
# fcvt.h.d ft3, ft0 // Somehow this instruction is taking the route on line 124