From f9c4b32bd5b81a5533b15ff5618c050f3abf0457 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 29 Sep 2022 18:06:34 -0500
Subject: [PATCH] Simplification to EBU.

---
 pipelined/src/ebu/controllerinputstage.sv | 3 +--
 pipelined/src/ebu/ebu.sv                  | 6 +++---
 2 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/pipelined/src/ebu/controllerinputstage.sv b/pipelined/src/ebu/controllerinputstage.sv
index d302cc395..5902a7a42 100644
--- a/pipelined/src/ebu/controllerinputstage.sv
+++ b/pipelined/src/ebu/controllerinputstage.sv
@@ -40,7 +40,7 @@ module controllerinputstage
   (input logic HCLK,
    input logic                 HRESETn,
    input logic                 Save, Restore, Disable,
-   output logic                Request, Active,
+   output logic                Request,
    // controller input
    input logic                 HWRITEin,
    input logic [2:0]           HSIZEin,
@@ -73,7 +73,6 @@ module controllerinputstage
 
   assign Request = HTRANSOut != 2'b00;
   assign HREADYOut = HREADYin & ~Disable;
-  assign Active = Request & HREADYOut;
 
 endmodule
   
diff --git a/pipelined/src/ebu/ebu.sv b/pipelined/src/ebu/ebu.sv
index e8d35c9ff..328cd59fe 100644
--- a/pipelined/src/ebu/ebu.sv
+++ b/pipelined/src/ebu/ebu.sv
@@ -109,7 +109,7 @@ module ebu
 
   // input stage IFU
   controllerinputstage IFUInput(.HCLK, .HRESETn, .Save(save[0]), .Restore(restore[0]), .Disable(dis[0]),
-    .Request(IFUReq), .Active(IFUActive),
+    .Request(IFUReq),
     .HWRITEin(1'b0), .HSIZEin(IFUHSIZE), .HBURSTin(IFUHBURST), .HTRANSin(IFUHTRANS), .HADDRin(IFUHADDR),
     .HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY),
     .HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYin(HREADY));
@@ -117,7 +117,7 @@ module ebu
   // input stage LSU
   // LSU always has priority so there should never be a need to save and restore the address phase inputs.
   controllerinputstage LSUInput(.HCLK, .HRESETn, .Save(save[1]), .Restore(restore[1]), .Disable(dis[1]),
-    .Request(LSUReq), .Active(LSUActive),
+    .Request(LSUReq),
     .HWRITEin(LSUHWRITE), .HSIZEin(LSUHSIZE), .HBURSTin(LSUHBURST), .HTRANSin(LSUHTRANS), .HADDRin(LSUHADDR), .HREADYOut(LSUHREADY),
     .HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut),
     .HTRANSOut(LSUHTRANSOut), .HADDROut(LSUHADDROut), .HREADYin(HREADY));
@@ -138,7 +138,7 @@ module ebu
 
   // FSM decides if arbitration needed.  Arbitration is held until the last beat of
   // a burst is completed.
-  assign both = LSUActive & IFUActive;
+  assign both = LSUReq & IFUReq;
   flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextState, IDLE, CurrState);
   always_comb 
     case (CurrState)