From f9a04c13df04a3b2e691306a58cc49e93ba5e16c Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Sat, 22 Oct 2022 16:28:44 -0500 Subject: [PATCH] comment updates. --- pipelined/src/cache/cachefsm.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 94bf36a6a..36e9e087a 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -205,7 +205,7 @@ module cachefsm // (CurrState == STATE_FLUSH_CHECK & VictimDirty); // **** can this be simplified? assign SelAdr = (CurrState == STATE_READY & (IgnoreRequestTLB & ~TrapM)) | // Ignore Request is needed on TLB miss. - // use the raw requests as we don't want DCacheTrapM in the critical path + // use the raw requests as we don't want TrapM in the critical path (CurrState == STATE_READY & ((AMO | CacheRW[0]) & CacheHit)) | // changes if store delay hazard removed (CurrState == STATE_READY & (DoAnyMiss)) | (CurrState == STATE_MISS_FETCH_WDV) |