diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index 1bdea74a7..eaedcd726 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -126,3 +126,4 @@ `define TESTSBP 0 `define REPLAY 0 +`define HPTW_WRITES_SUPPORTED 1 diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index 223aa3d80..2e8063e23 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -132,3 +132,4 @@ `define TESTSBP 1 `define REPLAY 0 +`define HPTW_WRITES_SUPPORTED 1 diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index 9102cf637..aadc41cbc 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -130,3 +130,4 @@ `define TESTSBP 0 `define REPLAY 0 +`define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index af6ef40cf..da45b57ba 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -128,3 +128,4 @@ `define TESTSBP 0 `define REPLAY 0 +`define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index 4d7b0418a..bddc02337 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -128,3 +128,4 @@ `define TESTSBP 0 `define REPLAY 0 +`define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64BP/wally-config.vh b/pipelined/config/rv64BP/wally-config.vh index f8ee8903b..dea046868 100644 --- a/pipelined/config/rv64BP/wally-config.vh +++ b/pipelined/config/rv64BP/wally-config.vh @@ -131,3 +131,4 @@ `define TESTSBP 1 `define REPLAY 0 +`define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index ea17620c3..a7dc78386 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -131,3 +131,4 @@ `define TESTSBP 0 `define REPLAY 0 +`define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64ic/wally-config.vh b/pipelined/config/rv64ic/wally-config.vh index ec497db2a..927924721 100644 --- a/pipelined/config/rv64ic/wally-config.vh +++ b/pipelined/config/rv64ic/wally-config.vh @@ -131,3 +131,4 @@ `define TESTSBP 0 `define REPLAY 0 +`define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/regression/buildrootBugFinder.py b/pipelined/regression/buildrootBugFinder.py index a20b7bf57..b6639e714 100755 --- a/pipelined/regression/buildrootBugFinder.py +++ b/pipelined/regression/buildrootBugFinder.py @@ -22,7 +22,7 @@ def main(): break checkpoint = checkpointList[0] logFile = logDir+"checkpoint"+str(checkpoint)+".log" - runCommand="{\nvsim -c < 1) begin:vict cachereplacementpolicy #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy( - .clk, .reset, .WayHit(WayHitFinal), .VictimWay, .PAdr, .RAdr, .LRUWriteEn); + .clk, .reset, .HitWay(HitWayFinal), .VictimWay, .RAdr, .LRUWriteEn); end else assign VictimWay = 1'b1; // one hot. - assign CacheHit = | WayHit; + assign CacheHit = | HitWay; assign VictimDirty = | VictimDirtyWay; // ReadDataLineWay is a 2d array of cache line len by number of ways. // Need to OR together each way in a bitwise manner. @@ -130,69 +128,59 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWay), .y(ReadDataLine)); or_rows #(NUMWAYS, TAGLEN) VictimTagAOMux(.a(VictimTagWay), .y(VictimTag)); - // Because of the sram clocked read when the ieu is stalled the read data maybe lost. // There are two ways to resolve. 1. We can replay the read of the sram or we can save // the data. Replay is eaiser but creates a longer critical path. // save/restore only wayhit and readdata. if(!`REPLAY) begin - flopenr #(NUMWAYS) wayhitsavereg(clk, save, reset, WayHit, WayHitSaved); - mux2 #(NUMWAYS) saverestoremux(WayHit, WayHitSaved, restore, WayHitFinal); - end else assign WayHitFinal = WayHit; + flopenr #(NUMWAYS) wayhitsavereg(clk, save, reset, HitWay, HitWaySaved); + mux2 #(NUMWAYS) saverestoremux(HitWay, HitWaySaved, restore, HitWayFinal); + end else assign HitWayFinal = HitWay; ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path: Write data and address. Muxes between writes from bus and writes from CPU. ///////////////////////////////////////////////////////////////////////////////////////////// - mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}), - .d1(CacheMemWriteData), .s(FSMLineWriteEn), .y(CacheWriteData)); + .d1(CacheBusWriteData), .s(SetValid), .y(CacheWriteData)); mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .d1({VictimTag, PAdr[SETTOP-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}), - .s({SelFlush, SelEvict}), - .y(CacheBusAdr)); + .s({SelFlush, SelEvict}), .y(CacheBusAdr)); ///////////////////////////////////////////////////////////////////////////////////////////// // Flush address and way generation during flush ///////////////////////////////////////////////////////////////////////////////////////////// - assign ResetOrFlushAdr = reset | FlushAdrCntRst; - flopenr #(SETLEN) FlushAdrReg(.clk, .reset(ResetOrFlushAdr), - .en(FlushAdrCntEn), .d(FlushAdrP1), .q(FlushAdr)); + flopenr #(SETLEN) FlushAdrReg(.clk, .reset(ResetOrFlushAdr), .en(FlushAdrCntEn), + .d(FlushAdrP1), .q(FlushAdr)); assign FlushAdrP1 = FlushAdr + 1'b1; assign FlushAdrFlag = (FlushAdr == FlushAdrThreshold[SETLEN-1:0]); - assign ResetOrFlushWay = reset | FlushWayCntRst; - flopenl #(NUMWAYS) FlushWayReg(.clk, .load(ResetOrFlushWay), - .en(FlushWayCntEn), .val({{NUMWAYS-1{1'b0}}, 1'b1}), - .d(NextFlushWay), .q(FlushWay)); + flopenl #(NUMWAYS) FlushWayReg(.clk, .load(ResetOrFlushWay), .en(FlushWayCntEn), + .val({{NUMWAYS-1{1'b0}}, 1'b1}), .d(NextFlushWay), .q(FlushWay)); assign FlushWayFlag = FlushWay[NUMWAYS-1]; assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]}; ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path: Write Enables ///////////////////////////////////////////////////////////////////////////////////////////// - - // *** change to structural - mux3 #(NUMWAYS) selectwaymux(WayHitFinal, VictimWay, FlushWay, {SelFlush, FSMLineWriteEn}, SelectedWay); + mux3 #(NUMWAYS) selectwaymux(HitWayFinal, VictimWay, FlushWay, + {SelFlush, SetValid}, SelectedWay); assign SetValidWay = SetValid ? SelectedWay : '0; assign ClearValidWay = ClearValid ? SelectedWay : '0; assign SetDirtyWay = SetDirty ? SelectedWay : '0; assign ClearDirtyWay = ClearDirty ? SelectedWay : '0; - assign WriteWordWayEn = FSMWordWriteEn ? SelectedWay : '0; - assign WriteLineWayEn = FSMLineWriteEn ? SelectedWay : '0; ///////////////////////////////////////////////////////////////////////////////////////////// // Cache FSM ///////////////////////////////////////////////////////////////////////////////////////////// - cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck, .RW, .Atomic, .CPUBusy, .IgnoreRequestTLB, .IgnoreRequestTrapM, .CacheHit, .VictimDirty, .CacheStall, .CacheCommitted, - .CacheMiss, .CacheAccess, .SelAdr, .SetValid, - .ClearValid, .SetDirty, .ClearDirty, .FSMWordWriteEn, - .FSMLineWriteEn, .SelEvict, .SelFlush, + .CacheMiss, .CacheAccess, .SelAdr, + .ClearValid, .ClearDirty, .SetDirty, + .SetValid, .SelEvict, .SelFlush, .FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst, .FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache, .save, .restore, diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 0fd7f5d51..df05e6cbc 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -32,78 +32,74 @@ module cachefsm (input logic clk, - input logic reset, + input logic reset, // inputs from IEU - input logic [1:0] RW, - input logic [1:0] Atomic, - input logic FlushCache, + input logic [1:0] RW, + input logic [1:0] Atomic, + input logic FlushCache, // hazard inputs - input logic CPUBusy, + input logic CPUBusy, // interlock fsm - input logic IgnoreRequestTLB, - input logic IgnoreRequestTrapM, + input logic IgnoreRequestTLB, + input logic IgnoreRequestTrapM, // Bus inputs - input logic CacheBusAck, + input logic CacheBusAck, // dcache internals - input logic CacheHit, - input logic VictimDirty, - input logic FlushAdrFlag, - input logic FlushWayFlag, + input logic CacheHit, + input logic VictimDirty, + input logic FlushAdrFlag, + input logic FlushWayFlag, // hazard outputs - output logic CacheStall, + output logic CacheStall, // counter outputs - output logic CacheMiss, - output logic CacheAccess, + output logic CacheMiss, + output logic CacheAccess, // Bus outputs - output logic CacheCommitted, - output logic CacheWriteLine, - output logic CacheFetchLine, + output logic CacheCommitted, + output logic CacheWriteLine, + output logic CacheFetchLine, // dcache internals - output logic [1:0] SelAdr, - output logic SetValid, - output logic ClearValid, - output logic SetDirty, - output logic ClearDirty, - output logic FSMWordWriteEn, - output logic FSMLineWriteEn, - output logic SelEvict, - output logic LRUWriteEn, - output logic SelFlush, - output logic FlushAdrCntEn, - output logic FlushWayCntEn, - output logic FlushAdrCntRst, - output logic FlushWayCntRst, - output logic save, - output logic restore); + output logic SelAdr, + output logic ClearValid, + output logic ClearDirty, + output logic SetDirty, + output logic SetValid, + output logic SelEvict, + output logic LRUWriteEn, + output logic SelFlush, + output logic FlushAdrCntEn, + output logic FlushWayCntEn, + output logic FlushAdrCntRst, + output logic FlushWayCntRst, + output logic save, + output logic restore); - logic [1:0] PreSelAdr; logic resetDelay; - logic Read, Write, AMO; + logic AMO; logic DoAMO, DoRead, DoWrite, DoFlush; - logic DoAMOHit, DoReadHit, DoWriteHit; - logic DoAMOMiss, DoReadMiss, DoWriteMiss; - logic FlushFlag; + logic DoAnyUpdateHit, DoAnyHit; + logic DoAnyMiss; + logic FlushFlag, FlushWayAndNotAdrFlag; - typedef enum logic [3:0] {STATE_READY, - - STATE_MISS_FETCH_WDV, - STATE_MISS_FETCH_DONE, - STATE_MISS_EVICT_DIRTY, - STATE_MISS_WRITE_CACHE_LINE, - STATE_MISS_READ_WORD, - STATE_MISS_READ_WORD_DELAY, - STATE_MISS_WRITE_WORD, - - STATE_CPU_BUSY, - STATE_CPU_BUSY_FINISH_AMO, - - STATE_FLUSH, - STATE_FLUSH_CHECK, - STATE_FLUSH_INCR, - STATE_FLUSH_WRITE_BACK, - STATE_FLUSH_CLEAR_DIRTY} statetype; + typedef enum logic [3:0] {STATE_READY, // hit states + // miss states + STATE_MISS_FETCH_WDV, + STATE_MISS_FETCH_DONE, + STATE_MISS_EVICT_DIRTY, + STATE_MISS_WRITE_CACHE_LINE, + STATE_MISS_READ_WORD, + STATE_MISS_READ_WORD_DELAY, + STATE_MISS_WRITE_WORD, + // cpu stalled replay/restore state + STATE_CPU_BUSY, + // flush cache + STATE_FLUSH, + STATE_FLUSH_CHECK, + STATE_FLUSH_INCR, + STATE_FLUSH_WRITE_BACK, + STATE_FLUSH_CLEAR_DIRTY} statetype; (* mark_debug = "true" *) statetype CurrState, NextState; logic IgnoreRequest; @@ -112,21 +108,15 @@ module cachefsm // if the command is used in the READY state then the cache needs to be able to supress // using both IgnoreRequestTLB and IgnoreRequestTrapM. Otherwise we can just use IgnoreRequestTLB. - // need to re organize all of these. Low priority though. assign DoFlush = FlushCache & ~IgnoreRequestTrapM; // do NOT suppress flush on DTLBMissM. Does not depend on address translation. assign AMO = Atomic[1] & (&RW); assign DoAMO = AMO & ~IgnoreRequest; - assign DoAMOHit = DoAMO & CacheHit; - assign DoAMOMiss = DoAMO & ~CacheHit; - assign Read = RW[1]; - assign DoRead = Read & ~IgnoreRequest; - assign DoReadHit = DoRead & CacheHit; - assign DoReadMiss = DoRead & ~CacheHit; - assign Write = RW[0]; - assign DoWrite = Write & ~IgnoreRequest; - assign DoWriteHit = DoWrite & CacheHit; - assign DoWriteMiss = DoWrite & ~CacheHit; + assign DoRead = RW[1] & ~IgnoreRequest; + assign DoWrite = RW[0] & ~IgnoreRequest; + assign DoAnyMiss = (DoAMO | DoRead | DoWrite) & ~CacheHit; + assign DoAnyUpdateHit = (DoAMO | DoWrite) & CacheHit; + assign DoAnyHit = DoAnyUpdateHit | (DoRead & CacheHit); assign FlushFlag = FlushAdrFlag & FlushWayFlag; // outputs for the performance counters. @@ -137,7 +127,6 @@ module cachefsm // PCNextF will no longer be pointing to the correct address. // But PCF will be the reset vector. flop #(1) resetDelayReg(.clk, .d(reset), .q(resetDelay)); - assign SelAdr = resetDelay ? 2'b01 : PreSelAdr; always_ff @(posedge clk) if (reset) CurrState <= #1 STATE_READY; @@ -146,54 +135,49 @@ module cachefsm always_comb begin NextState = STATE_READY; case (CurrState) - STATE_READY: if(IgnoreRequest) NextState = STATE_READY; - else if(DoFlush) NextState = STATE_FLUSH; - else if(DoAMOHit & CPUBusy) NextState = STATE_CPU_BUSY_FINISH_AMO; // change - else if(DoReadHit & CPUBusy) NextState = STATE_CPU_BUSY; - else if(DoWriteHit & CPUBusy) NextState = STATE_CPU_BUSY; - else if(DoReadMiss | DoWriteMiss | DoAMOMiss) NextState = STATE_MISS_FETCH_WDV; // change - else NextState = STATE_READY; - STATE_MISS_FETCH_WDV: if (CacheBusAck) NextState = STATE_MISS_FETCH_DONE; - else NextState = STATE_MISS_FETCH_WDV; - STATE_MISS_FETCH_DONE: if(VictimDirty) NextState = STATE_MISS_EVICT_DIRTY; - else NextState = STATE_MISS_WRITE_CACHE_LINE; - STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_WORD; - STATE_MISS_READ_WORD: if (Write & ~AMO) NextState = STATE_MISS_WRITE_WORD; - else NextState = STATE_MISS_READ_WORD_DELAY; - STATE_MISS_READ_WORD_DELAY: if(AMO & CPUBusy) NextState = STATE_CPU_BUSY_FINISH_AMO; - else if(CPUBusy) NextState = STATE_CPU_BUSY; - else NextState = STATE_READY; - STATE_MISS_WRITE_WORD: if(CPUBusy) NextState = STATE_CPU_BUSY; - else NextState = STATE_READY; - STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_WRITE_CACHE_LINE; - else NextState = STATE_MISS_EVICT_DIRTY; - STATE_CPU_BUSY: if(CPUBusy) NextState = STATE_CPU_BUSY; - else NextState = STATE_READY; - STATE_CPU_BUSY_FINISH_AMO: if(CPUBusy) NextState = STATE_CPU_BUSY_FINISH_AMO; - else NextState = STATE_READY; - STATE_FLUSH: NextState = STATE_FLUSH_CHECK; - STATE_FLUSH_CHECK: if(VictimDirty) NextState = STATE_FLUSH_WRITE_BACK; - else if (FlushFlag) NextState = STATE_READY; - else if(FlushWayFlag) NextState = STATE_FLUSH_INCR; - else NextState = STATE_FLUSH_CHECK; - STATE_FLUSH_INCR: NextState = STATE_FLUSH_CHECK; - STATE_FLUSH_WRITE_BACK: if(CacheBusAck) NextState = STATE_FLUSH_CLEAR_DIRTY; - else NextState = STATE_FLUSH_WRITE_BACK; - STATE_FLUSH_CLEAR_DIRTY: if(FlushAdrFlag & FlushWayFlag) NextState = STATE_READY; - else if (FlushWayFlag) NextState = STATE_FLUSH_INCR; - else NextState = STATE_FLUSH_CHECK; - default: NextState = STATE_READY; + STATE_READY: if(IgnoreRequest) NextState = STATE_READY; + else if(DoFlush) NextState = STATE_FLUSH; + else if(DoAnyHit & CPUBusy) NextState = STATE_CPU_BUSY; + else if(DoAnyMiss) NextState = STATE_MISS_FETCH_WDV; // change + else NextState = STATE_READY; + STATE_MISS_FETCH_WDV: if(CacheBusAck) NextState = STATE_MISS_FETCH_DONE; + else NextState = STATE_MISS_FETCH_WDV; + STATE_MISS_FETCH_DONE: if(VictimDirty) NextState = STATE_MISS_EVICT_DIRTY; + else NextState = STATE_MISS_WRITE_CACHE_LINE; + STATE_MISS_WRITE_CACHE_LINE: NextState = STATE_MISS_READ_WORD; + STATE_MISS_READ_WORD: if(RW[0] & ~AMO) NextState = STATE_MISS_WRITE_WORD; + else NextState = STATE_MISS_READ_WORD_DELAY; + STATE_MISS_READ_WORD_DELAY: if(CPUBusy) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; + STATE_MISS_WRITE_WORD: if(CPUBusy) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; + STATE_MISS_EVICT_DIRTY: if(CacheBusAck) NextState = STATE_MISS_WRITE_CACHE_LINE; + else NextState = STATE_MISS_EVICT_DIRTY; + STATE_CPU_BUSY: if(CPUBusy) NextState = STATE_CPU_BUSY; + else NextState = STATE_READY; + STATE_FLUSH: NextState = STATE_FLUSH_CHECK; + STATE_FLUSH_CHECK: if(VictimDirty) NextState = STATE_FLUSH_WRITE_BACK; + else if(FlushFlag) NextState = STATE_READY; + else if(FlushWayFlag) NextState = STATE_FLUSH_INCR; + else NextState = STATE_FLUSH_CHECK; + STATE_FLUSH_INCR: NextState = STATE_FLUSH_CHECK; + STATE_FLUSH_WRITE_BACK: if(CacheBusAck) NextState = STATE_FLUSH_CLEAR_DIRTY; + else NextState = STATE_FLUSH_WRITE_BACK; + STATE_FLUSH_CLEAR_DIRTY: if(FlushFlag) NextState = STATE_READY; + else if(FlushWayFlag) NextState = STATE_FLUSH_INCR; + else NextState = STATE_FLUSH_CHECK; + default: NextState = STATE_READY; endcase end // com back to CPU assign CacheCommitted = CurrState != STATE_READY; - assign CacheStall = (CurrState == STATE_READY & (DoFlush | DoAMOMiss | DoReadMiss | DoWriteMiss)) | + assign CacheStall = (CurrState == STATE_READY & (DoFlush | DoAnyMiss)) | (CurrState == STATE_MISS_FETCH_WDV) | (CurrState == STATE_MISS_FETCH_DONE) | + (CurrState == STATE_MISS_EVICT_DIRTY) | (CurrState == STATE_MISS_WRITE_CACHE_LINE) | (CurrState == STATE_MISS_READ_WORD) | - (CurrState == STATE_MISS_EVICT_DIRTY) | (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK & ~(FlushFlag)) | (CurrState == STATE_FLUSH_INCR) | @@ -201,18 +185,13 @@ module cachefsm (CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag)); // write enables internal to cache assign SetValid = CurrState == STATE_MISS_WRITE_CACHE_LINE; - assign ClearValid = '0; - assign SetDirty = (CurrState == STATE_READY & DoAMO) | - (CurrState == STATE_READY & DoWrite) | - (CurrState == STATE_MISS_READ_WORD_DELAY & AMO) | - (CurrState == STATE_MISS_WRITE_WORD); - assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE) | - (CurrState == STATE_FLUSH_CLEAR_DIRTY); - assign FSMWordWriteEn = (CurrState == STATE_READY & (DoAMOHit | DoWriteHit)) | + assign SetDirty = (CurrState == STATE_READY & DoAnyUpdateHit) | (CurrState == STATE_MISS_READ_WORD_DELAY & AMO) | (CurrState == STATE_MISS_WRITE_WORD); - assign FSMLineWriteEn = (CurrState == STATE_MISS_WRITE_CACHE_LINE); - assign LRUWriteEn = (CurrState == STATE_READY & (DoAMOHit | DoReadHit | DoWriteHit)) | + assign ClearValid = '0; + assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE) | + (CurrState == STATE_FLUSH_CLEAR_DIRTY); + assign LRUWriteEn = (CurrState == STATE_READY & DoAnyHit) | (CurrState == STATE_MISS_READ_WORD_DELAY) | (CurrState == STATE_MISS_WRITE_WORD); // Flush and eviction controls @@ -220,42 +199,38 @@ module cachefsm assign SelFlush = (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK) | (CurrState == STATE_FLUSH_INCR) | (CurrState == STATE_FLUSH_WRITE_BACK) | (CurrState == STATE_FLUSH_CLEAR_DIRTY); - assign FlushAdrCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & FlushWayFlag & ~FlushAdrFlag) | - (CurrState == STATE_FLUSH_CLEAR_DIRTY & FlushWayFlag & ~FlushAdrFlag); + assign FlushWayAndNotAdrFlag = FlushWayFlag & ~FlushAdrFlag; + assign FlushAdrCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & FlushWayAndNotAdrFlag) | + (CurrState == STATE_FLUSH_CLEAR_DIRTY & FlushWayAndNotAdrFlag); assign FlushWayCntEn = (CurrState == STATE_FLUSH_CHECK & ~VictimDirty & ~(FlushFlag)) | - (CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag)); + (CurrState == STATE_FLUSH_CLEAR_DIRTY & ~FlushFlag); assign FlushAdrCntRst = (CurrState == STATE_READY); assign FlushWayCntRst = (CurrState == STATE_READY) | (CurrState == STATE_FLUSH_INCR); // Bus interface controls - assign CacheFetchLine = (CurrState == STATE_READY & (DoAMOMiss | DoWriteMiss | DoReadMiss)); + assign CacheFetchLine = (CurrState == STATE_READY & DoAnyMiss); assign CacheWriteLine = (CurrState == STATE_MISS_FETCH_DONE & VictimDirty) | (CurrState == STATE_FLUSH_CHECK & VictimDirty); // handle cpu stall. - assign restore = ((CurrState == STATE_CPU_BUSY) | (CurrState == STATE_CPU_BUSY_FINISH_AMO)) & ~`REPLAY; - assign save = ((CurrState == STATE_READY & (DoAMOHit | DoReadHit | DoWriteHit) & CPUBusy) | - (CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | Read) & CPUBusy) | + assign restore = ((CurrState == STATE_CPU_BUSY)) & ~`REPLAY; + assign save = ((CurrState == STATE_READY & DoAnyHit & CPUBusy) | + (CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | RW[1]) & CPUBusy) | (CurrState == STATE_MISS_WRITE_WORD & DoWrite & CPUBusy)) & ~`REPLAY; // **** can this be simplified? - assign PreSelAdr = ((CurrState == STATE_READY & IgnoreRequestTLB) | // Ignore Request is needed on TLB miss. - (CurrState == STATE_READY & (AMO & CacheHit)) | - (CurrState == STATE_READY & (Read & CacheHit) & (CPUBusy & `REPLAY)) | - (CurrState == STATE_READY & (Write & CacheHit)) | - (CurrState == STATE_MISS_FETCH_WDV) | - (CurrState == STATE_MISS_FETCH_DONE) | - (CurrState == STATE_MISS_WRITE_CACHE_LINE) | - (CurrState == STATE_MISS_READ_WORD) | - (CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | (CPUBusy & `REPLAY))) | - (CurrState == STATE_MISS_WRITE_WORD) | - (CurrState == STATE_MISS_EVICT_DIRTY) | - (CurrState == STATE_CPU_BUSY & (CPUBusy & `REPLAY)) | - (CurrState == STATE_CPU_BUSY_FINISH_AMO)) ? 2'b01 : - ((CurrState == STATE_FLUSH) | - (CurrState == STATE_FLUSH_CHECK & ~(VictimDirty & FlushFlag)) | - (CurrState == STATE_FLUSH_INCR) | - (CurrState == STATE_FLUSH_WRITE_BACK) | - (CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag))) ? 2'b10 : - 2'b00; - + assign SelAdr = (CurrState == STATE_READY & IgnoreRequestTLB) | // Ignore Request is needed on TLB miss. + // use the raw requests as we don't want IgnoreRequestTrapM in the critical path + (CurrState == STATE_READY & ((AMO | RW[0]) & CacheHit)) | // changes if store delay hazard removed + (CurrState == STATE_READY & (RW[1] & CacheHit) & (CPUBusy & `REPLAY)) | + + (CurrState == STATE_MISS_FETCH_WDV) | + (CurrState == STATE_MISS_FETCH_DONE) | + (CurrState == STATE_MISS_EVICT_DIRTY) | + (CurrState == STATE_MISS_WRITE_CACHE_LINE) | + (CurrState == STATE_MISS_READ_WORD) | + (CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | (CPUBusy & `REPLAY))) | + (CurrState == STATE_MISS_WRITE_WORD) | + + (CurrState == STATE_CPU_BUSY & (CPUBusy & `REPLAY)) | + resetDelay; endmodule // cachefsm diff --git a/pipelined/src/cache/cachereplacementpolicy.sv b/pipelined/src/cache/cachereplacementpolicy.sv index 49f0f79c2..80fc251c7 100644 --- a/pipelined/src/cache/cachereplacementpolicy.sv +++ b/pipelined/src/cache/cachereplacementpolicy.sv @@ -32,9 +32,8 @@ module cachereplacementpolicy #(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMLINES = 128)( input logic clk, reset, - input logic [NUMWAYS-1:0] WayHit, + input logic [NUMWAYS-1:0] HitWay, output logic [NUMWAYS-1:0] VictimWay, - input logic [`PA_BITS-1:0] PAdr, input logic [SETLEN-1:0] RAdr, input logic LRUWriteEn); @@ -53,7 +52,6 @@ module cachereplacementpolicy // Pipeline Delay Registers flopr #(SETLEN) RAdrDelayReg(clk, reset, RAdr, RAdrD); - flopr #(SETLEN) PAdrDelayReg(clk, reset, PAdr[SETLEN+OFFSETLEN-1:OFFSETLEN], PAdrD); flopr #(1) LRUWriteEnDelayReg(clk, reset, LRUWriteEn, LRUWriteEnD); flopr #(NUMWAYS-1) NewReplacementDelayReg(clk, reset, NewReplacement, NewReplacementD); @@ -61,13 +59,13 @@ module cachereplacementpolicy // Needs to be resettable for simulation, but could omit reset for synthesis *** always_ff @(posedge clk) if (reset) for (int set = 0; set < NUMLINES; set++) ReplacementBits[set] = '0; - else if (LRUWriteEnD) ReplacementBits[PAdrD[SETLEN+OFFSETLEN-1:OFFSETLEN]] = NewReplacementD; + else if (LRUWriteEnD) ReplacementBits[RAdrD] = NewReplacementD; assign LineReplacementBits = ReplacementBits[RAdrD]; genvar index; if(NUMWAYS == 2) begin : PseudoLRU assign LRUEn[0] = 1'b0; - assign NewReplacement[0] = WayHit[1]; + assign NewReplacement[0] = HitWay[1]; assign VictimWay[1] = ~LineReplacementBits[0]; assign VictimWay[0] = LineReplacementBits[0]; end else if (NUMWAYS == 4) begin : PseudoLRU @@ -84,15 +82,15 @@ module cachereplacementpolicy assign VictimWay[2] = LineReplacementBits[2] & ~LineReplacementBits[1]; assign VictimWay[3] = LineReplacementBits[2] & LineReplacementBits[1]; - // New LRU bits which are updated is function only of the WayHit. + // New LRU bits which are updated is function only of the HitWay. // However the not updated bits come from the old LRU. - assign LRUEn[2] = |WayHit; - assign LRUEn[1] = WayHit[3] | WayHit[2]; - assign LRUEn[0] = WayHit[1] | WayHit[0]; + assign LRUEn[2] = |HitWay; + assign LRUEn[1] = HitWay[3] | HitWay[2]; + assign LRUEn[0] = HitWay[1] | HitWay[0]; - assign LRUMask[2] = WayHit[1] | WayHit[0]; - assign LRUMask[1] = WayHit[2]; - assign LRUMask[0] = WayHit[0]; + assign LRUMask[2] = HitWay[1] | HitWay[0]; + assign LRUMask[1] = HitWay[2]; + assign LRUMask[0] = HitWay[0]; mux2 #(1) LRUMuxes[NUMWAYS-2:0](LineReplacementBits, LRUMask, LRUEn, NewReplacement); end @@ -101,21 +99,21 @@ module cachereplacementpolicy // selects assign LRUEn[6] = 1'b1; - assign LRUEn[5] = WayHit[7] | WayHit[6] | WayHit[5] | WayHit[4]; - assign LRUEn[4] = WayHit[7] | WayHit[6]; - assign LRUEn[3] = WayHit[5] | WayHit[4]; - assign LRUEn[2] = WayHit[3] | WayHit[2] | WayHit[1] | WayHit[0]; - assign LRUEn[1] = WayHit[3] | WayHit[2]; - assign LRUEn[0] = WayHit[1] | WayHit[0]; + assign LRUEn[5] = HitWay[7] | HitWay[6] | HitWay[5] | HitWay[4]; + assign LRUEn[4] = HitWay[7] | HitWay[6]; + assign LRUEn[3] = HitWay[5] | HitWay[4]; + assign LRUEn[2] = HitWay[3] | HitWay[2] | HitWay[1] | HitWay[0]; + assign LRUEn[1] = HitWay[3] | HitWay[2]; + assign LRUEn[0] = HitWay[1] | HitWay[0]; // mask - assign LRUMask[6] = WayHit[7] | WayHit[6] | WayHit[5] | WayHit[4]; - assign LRUMask[5] = WayHit[7] | WayHit[6]; - assign LRUMask[4] = WayHit[7]; - assign LRUMask[3] = WayHit[5]; - assign LRUMask[2] = WayHit[3] | WayHit[2]; - assign LRUMask[1] = WayHit[2]; - assign LRUMask[0] = WayHit[0]; + assign LRUMask[6] = HitWay[7] | HitWay[6] | HitWay[5] | HitWay[4]; + assign LRUMask[5] = HitWay[7] | HitWay[6]; + assign LRUMask[4] = HitWay[7]; + assign LRUMask[3] = HitWay[5]; + assign LRUMask[2] = HitWay[3] | HitWay[2]; + assign LRUMask[1] = HitWay[2]; + assign LRUMask[0] = HitWay[0]; for(index = 0; index < NUMWAYS-1; index++) assign NewReplacement[index] = LRUEn[index] ? LRUMask[index] : LineReplacementBits[index]; diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index a5bb52812..d9dfdfff4 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -37,21 +37,20 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, input logic [$clog2(NUMLINES)-1:0] RAdr, input logic [`PA_BITS-1:0] PAdr, - input logic WriteWordWayEn, - input logic WriteLineWayEn, input logic [LINELEN-1:0] CacheWriteData, input logic SetValidWay, input logic ClearValidWay, input logic SetDirtyWay, input logic ClearDirtyWay, input logic SelEvict, - input logic VictimWay, - input logic InvalidateAll, input logic SelFlush, + input logic VictimWay, input logic FlushWay, + input logic Invalidate, + output logic [LINELEN-1:0] ReadDataLineWay, - output logic WayHit, + output logic HitWay, output logic VictimDirtyWay, output logic [TAGLEN-1:0] VictimTagWay); @@ -59,28 +58,25 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, localparam LOGWPL = $clog2(WORDSPERLINE); localparam LOGXLENBYTES = $clog2(`XLEN/8); - logic [NUMLINES-1:0] ValidBits; - logic [NUMLINES-1:0] DirtyBits; - logic [LINELEN-1:0] ReadDataLine; - logic [TAGLEN-1:0] ReadTag; - logic Valid; - logic Dirty; - logic SelData; - logic SelTag; - - logic [$clog2(NUMLINES)-1:0] RAdrD; - - logic [2**LOGWPL-1:0] MemPAdrDecoded; - logic [LINELEN/`XLEN-1:0] SelectedWriteWordEn; + logic [NUMLINES-1:0] ValidBits; + logic [NUMLINES-1:0] DirtyBits; + logic [LINELEN-1:0] ReadDataLine; + logic [TAGLEN-1:0] ReadTag; + logic Valid; + logic Dirty; + logic SelData; + logic SelTag; + logic [$clog2(NUMLINES)-1:0] RAdrD; + logic [2**LOGWPL-1:0] MemPAdrDecoded; + logic [LINELEN/`XLEN-1:0] SelectedWriteWordEn; - ///////////////////////////////////////////////////////////////////////////////////////////// // Write Enable demux ///////////////////////////////////////////////////////////////////////////////////////////// onehotdecoder #(LOGWPL) adrdec( .bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded)); // If writing the whole line set all write enables to 1, else only set the correct word. - assign SelectedWriteWordEn = WriteLineWayEn ? '1 : WriteWordWayEn ? MemPAdrDecoded : '0; // OR-AND + assign SelectedWriteWordEn = SetValidWay ? '1 : SetDirtyWay ? MemPAdrDecoded : '0; // OR-AND ///////////////////////////////////////////////////////////////////////////////////////////// // Tag Array @@ -88,12 +84,13 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .Adr(RAdr), .ReadData(ReadTag), - .CacheWriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(WriteLineWayEn)); + .CacheWriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(SetValidWay)); // AND portion of distributed tag multiplexer - assign SelTag = SelFlush ? FlushWay : VictimWay; + mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag); assign VictimTagWay = SelTag ? ReadTag : '0; // AND part of AOMux assign VictimDirtyWay = SelTag & Dirty & Valid; + assign HitWay = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]); ///////////////////////////////////////////////////////////////////////////////////////////// // Data Array @@ -109,8 +106,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, end // AND portion of distributed read multiplexers - assign WayHit = Valid & (ReadTag == PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]); - mux3 #(1) selecteddatamux(WayHit, VictimWay, FlushWay, {SelFlush, SelEvict}, SelData); + mux3 #(1) selecteddatamux(HitWay, VictimWay, FlushWay, {SelFlush, SelEvict}, SelData); assign ReadDataLineWay = SelData ? ReadDataLine : '0; // AND part of AO mux. ///////////////////////////////////////////////////////////////////////////////////////////// @@ -118,9 +114,9 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, ///////////////////////////////////////////////////////////////////////////////////////////// always_ff @(posedge clk) begin // Valid bit array, - if (reset | InvalidateAll) ValidBits <= #1 '0; - else if (SetValidWay) ValidBits[RAdr] <= #1 1'b1; - else if (ClearValidWay) ValidBits[RAdr] <= #1 1'b0; + if (reset | Invalidate) ValidBits <= #1 '0; + else if (SetValidWay) ValidBits[RAdr] <= #1 1'b1; + else if (ClearValidWay) ValidBits[RAdr] <= #1 1'b0; end flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD); assign Valid = ValidBits[RAdrD]; @@ -132,8 +128,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, // Dirty bits if (DIRTY_BITS) begin:dirty always_ff @(posedge clk) begin - if (reset) DirtyBits <= #1 {NUMLINES{1'b0}}; - else if (SetDirtyWay) DirtyBits[RAdr] <= #1 1'b1; + if (reset) DirtyBits <= #1 {NUMLINES{1'b0}}; + else if (SetDirtyWay) DirtyBits[RAdr] <= #1 1'b1; else if (ClearDirtyWay) DirtyBits[RAdr] <= #1 1'b0; end assign Dirty = DirtyBits[RAdrD]; diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index 9b82aff47..a68370cdb 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -111,7 +111,7 @@ module ahblite ( else if (IFUBusRead) NextBusState = INSTRREAD; else NextBusState = IDLE; INSTRREAD: if (~HREADY) NextBusState = INSTRREAD; - else NextBusState = IDLE; // if (IFUBusRead still high) + else NextBusState = IDLE; // if (IFUBusRead still high) *** need to wait? default: NextBusState = IDLE; endcase diff --git a/pipelined/src/ieu/controller.sv b/pipelined/src/ieu/controller.sv index 8f3967576..646d87074 100644 --- a/pipelined/src/ieu/controller.sv +++ b/pipelined/src/ieu/controller.sv @@ -156,10 +156,13 @@ module controller( 7'b1100011: ControlsD = `CTRLW'b0_010_11_00_000_1_0_0_0_0_0_0_0_0_00_0; // branches 7'b1100111: ControlsD = `CTRLW'b1_000_01_00_000_0_0_1_1_0_0_0_0_0_00_0; // jalr 7'b1101111: ControlsD = `CTRLW'b1_011_11_00_000_0_0_1_1_0_0_0_0_0_00_0; // jal - 7'b1110011: if (Funct3D == 3'b000) + 7'b1110011: if (`ZICSR_SUPPORTED) begin + if (Funct3D == 3'b000) ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_1_0_0_00_0; // privileged; decoded further in priveleged modules - else + else ControlsD = `CTRLW'b1_000_00_00_010_0_0_0_0_0_1_0_0_0_00_0; // csrs + end else + ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction default: ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction endcase diff --git a/pipelined/src/ieu/regfile.sv b/pipelined/src/ieu/regfile.sv index 2dfb0626d..71ef621a7 100644 --- a/pipelined/src/ieu/regfile.sv +++ b/pipelined/src/ieu/regfile.sv @@ -49,6 +49,7 @@ module regfile ( // register 0 hardwired to 0 // reset is intended for simulation only, not synthesis + // can logic be adjusted to not need resettable registers? always_ff @(negedge clk) // or posedge reset) // *** make this a preload in testbench rather than reset if (reset) for(i=1; i 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp - begin - errors = errors+1; - $display("result was %h, should be %h %h %h\n", r, correctr, diffn, diffp); - $display("failed\n"); - $stop; - end - if (a === 52'hxxxxxxxxxxxxx) - begin - $display("%d Tests completed successfully", testnum); - $stop; - end - end - if (req) - begin - req <= #5 0; - correctr = nextr; - testnum = testnum+1; - Vec = Tests[testnum]; - $display("a = %h b = %h",a,b); - a = Vec[`mema]; - b = Vec[`memb]; - nextr = Vec[`memr]; - end - end - -endmodule - diff --git a/pipelined/srt/srt_stanford.sv b/pipelined/srt/srt_stanford.sv index ce0417f56..e66cfa3c3 100644 --- a/pipelined/srt/srt_stanford.sv +++ b/pipelined/srt/srt_stanford.sv @@ -11,7 +11,52 @@ // This Verilog file models a radix 2 SRT divider which // produces one quotient digit per cycle. The divider // keeps the partial remainder in carry-save form. - + +`include "wally-config.vh" + +// will also be used for integer division so keep in mind when naming modules/signals + +///////////////// +// srt_divide // +//////////////// +module srt_divide(input logic clk, + input logic req, + input logic sqrt, // 1 to compute sqrt(a), 0 to compute a/b + input logic [63:0] a, b, // input numbers + output logic [54:0] rp, rm, + output logic [10:0] expE); + + // output logic from Unpackers + logic XSgnE, YSgnE, ZSgnE; + logic [10:0] XExpE, YExpE, ZExpE; // exponent + logic [52:0] XManE, YManE, ZManE; + logic XNormE; + logic XNaNE, YNaNE, ZNaNE; + logic XSNaNE, YSNaNE, ZSNaNE; + logic XDenormE, YDenormE, ZDenormE; // denormals + logic XZeroE, YZeroE, ZZeroE; + logic [10:0] BiasE; // currrently hardcoded, will probs be removed + logic XInfE, YInfE, ZInfE; + logic XExpMaxE; // says exponent is all ones, can ignore + + // have Unpackers + // have mantissa divider + // exponent divider + + // hopefully having the .* here works for unpacker --- nope it doesn't + unpack unpacking(a, b, 0, 1'b1, 0, XSgnE, YSgnE, ZSgnE, XExpE, YExpE, ZExpE, XManE, YManE, ZManE, XNormE,XNaNE, YNaNE, ZNaNE,XSNaNE, YSNaNE, ZSNaNE,XDenormE, YDenormE, ZDenormE,XZeroE, YZeroE, ZZeroE,BiasE,XInfE, YInfE, ZInfE,XExpMaxE); + srt srt(clk, req, XManE[51:0], YManE[51:0], rp, rm); + exp exp(XexpE, YExpE, expE); +endmodule + +// exponent module +// first iteration +module exp(input [10:0] e1, e2, + output [10:0] e); // for a 64 bit number, exponent section is 11 bits + assign e = (e1 - e2) + 11'd1023; // bias is hardcoded +endmodule + + ///////// // srt // ///////// @@ -39,12 +84,12 @@ module srt(input logic clk, // When start is asserted, the inputs are loaded into the divider. // Otherwise, the divisor is retained and the partial remainder // is fed back for the next iteration. - mux2 psmux({psa[54:0], 1'b0}, {4'b0001, a}, req, psn); - flop psflop(clk, psn, ps); - mux2 pcmux({pca[54:0], 1'b0}, 56'b0, req, pcn); - flop pcflop(clk, pcn, pc); - mux2 dmux(d, {4'b0001, b}, req, dn); - flop dflop(clk, dn, d); + mux2_special psmux({psa[54:0], 1'b0}, {4'b0001, a}, req, psn); + flop_special psflop(clk, psn, ps); + mux2_special pcmux({pca[54:0], 1'b0}, 56'b0, req, pcn); + flop_special pcflop(clk, pcn, pc); + mux2_special dmux(d, {4'b0001, b}, req, dn); + flop_special dflop(clk, dn, d); // Quotient Selection logic // Given partial remainder, select quotient of +1, 0, or -1 (qp, qz, pm) @@ -54,7 +99,7 @@ module srt(input logic clk, // Divisor Selection logic inv dinv(d, d_b); - mux3 divisorsel(d_b, 56'b0, d, qp, qz, qm, dsel); + mux3_special divisorsel(d_b, 56'b0, d, qp, qz, qm, dsel); // Partial Product Generation csa csa(ps, pc, dsel, qp, psa, pca); @@ -63,7 +108,7 @@ endmodule ////////// // mux2 // ////////// -module mux2(input logic [55:0] in0, in1, +module mux2_special(input logic [55:0] in0, in1, input logic sel, output logic [55:0] out); @@ -73,7 +118,7 @@ endmodule ////////// // flop // ////////// -module flop(clk, in, out); +module flop_special(clk, in, out); input clk; input [55:0] in; output [55:0] out; @@ -159,9 +204,9 @@ module inv(input logic [55:0] in, endmodule ////////// -// mux3 // +// mux3_special // ////////// -module mux3(in0, in1, in2, sel0, sel1, sel2, out); +module mux3_special(in0, in1, in2, sel0, sel1, sel2, out); input [55:0] in0; input [55:0] in1; input [55:0] in2; @@ -271,6 +316,24 @@ module testbench; logic [51:0] b; logic [51:0] r; logic [54:0] rp, rm; // positive quotient digits + + //input logic [63:0] X, Y, Z, - numbers + //input logic FmtE, ---- format, 1 is for double precision, 0 is single + //input logic [2:0] FOpCtrlE, ---- controling operations for FPU, 1 is sqrt, 0 is divide + // all variables are commented in fpu.sv + + // output logic from Unpackers + logic XSgnE, YSgnE, ZSgnE; + logic [10:0] XExpE, YExpE, ZExpE; // exponent + logic [52:0] XManE, YManE, ZManE; + logic XNormE; + logic XNaNE, YNaNE, ZNaNE; + logic XSNaNE, YSNaNE, ZSNaNE; + logic XDenormE, YDenormE, ZDenormE; // denormals + logic XZeroE, YZeroE, ZZeroE; + logic [10:0] BiasE; // currrently hardcoded, will probs be removed + logic XInfE, YInfE, ZInfE; + logic XExpMaxE; // says exponent is all ones, can ignore // Test parameters parameter MEM_SIZE = 40000; @@ -287,8 +350,15 @@ module testbench; logic [51:0] correctr, nextr; integer testnum, errors; + // Unpackers + unpacking unpack(.X({12'b100010000010,a}), .Y({12'b100010000001,b}), .Z(0), .FmtE(1'b1), .FOpCtrlE(0), .*); + // Divider - srt srt(clk, req, a, b, rp, rm); + srt srt(.clk(clk), .req(req), .sqrt(1'b0), .a(XManE[51:0]), .b(YManE[51:0]), .rp(rp),.rm(rm)); + + //srt srt(.clk(clk), .req(req), .sqrt(1'b0), .a(a), .b(b), .rp(rp),.rm(rm)); + + // Divider + unpacker // Final adder converts quotient digits to 2's complement & normalizes finaladd finaladd(rp, rm, r); @@ -326,7 +396,9 @@ module testbench; begin req <= #5 1; $display("result was %h, should be %h\n", r, correctr); - if ((correctr - r) > 1) // check if accurate to 1 ulp + //if (abs(correctr - r) > 1) // check if accurate to 1 ulp + // giving error "srt_stanford.sv(395): (vopt-7063) Failed to find 'abs' in hierarchical name 'abs'." + if (correctr - r > 1) // check if accurate to 1 ulp begin errors = errors+1; $display("failed\n"); diff --git a/pipelined/srt/testbench.sv b/pipelined/srt/testbench.sv new file mode 100644 index 000000000..0af3821ec --- /dev/null +++ b/pipelined/srt/testbench.sv @@ -0,0 +1,132 @@ +///////////// +// counter // +///////////// +module counter(input logic clk, + input logic req, + output logic done); + + logic [5:0] count; + + // This block of control logic sequences the divider + // through its iterations. You may modify it if you + // build a divider which completes in fewer iterations. + // You are not responsible for the (trivial) circuit + // design of the block. + + always @(posedge clk) + begin + if (count == 54) done <= #1 1; + else if (done | req) done <= #1 0; + if (req) count <= #1 0; + else count <= #1 count+1; + end +endmodule + +/////////// +// clock // +/////////// +module clock(clk); + output clk; + + // Internal clk signal + logic clk; + +endmodule + +////////// +// testbench // +////////// +module testbench; + logic clk; + logic req; + logic done; + logic [51:0] a; + logic [51:0] b; + logic [51:0] r; + logic [54:0] rp, rm; // positive quotient digits + + // Test parameters + parameter MEM_SIZE = 40000; + parameter MEM_WIDTH = 52+52+52; + + `define memr 51:0 + `define memb 103:52 + `define mema 155:104 + + // Test logicisters + logic [MEM_WIDTH-1:0] Tests [0:MEM_SIZE]; // Space for input file + logic [MEM_WIDTH-1:0] Vec; // Verilog doesn't allow direct access to a + // bit field of an array + logic [51:0] correctr, nextr, diffn, diffp; + integer testnum, errors; + + // Divider + srt #(52) srt(.clk, .Start(req), + .Stall(1'b0), .Flush(1'b0), + .SrcXFrac(a), .SrcYFrac(b), + .SrcA('0), .SrcB('0), .Fmt(2'b00), + .W64(1'b0), .Signed(1'b0), .Int(1'b0), .Sqrt(1'b0), + .Quot(r), .Rem(), .Flags()); + + // Counter + counter counter(clk, req, done); + + + initial + forever + begin + clk = 1; #17; + clk = 0; #16; + end + + + // Read test vectors from disk + initial + begin + testnum = 0; + errors = 0; + $readmemh ("testvectors", Tests); + Vec = Tests[testnum]; + a = Vec[`mema]; + b = Vec[`memb]; + nextr = Vec[`memr]; + req <= #5 1; + end + + // Apply directed test vectors read from file. + + always @(posedge clk) + begin + if (done) + begin + req <= #5 1; + diffp = correctr - r; + diffn = r - correctr; + if (($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp + begin + errors = errors+1; + $display("result was %h, should be %h %h %h\n", r, correctr, diffn, diffp); + $display("failed\n"); + $stop; + end + if (a === 52'hxxxxxxxxxxxxx) + begin + $display("%d Tests completed successfully", testnum); + $stop; + end + end + if (req) + begin + req <= #5 0; + correctr = nextr; + testnum = testnum+1; + Vec = Tests[testnum]; + $display("a = %h b = %h",a,b); + a = Vec[`mema]; + b = Vec[`memb]; + nextr = Vec[`memr]; + end + end + +endmodule + diff --git a/pipelined/srt/testgen.c b/pipelined/srt/testgen.c index 98d52819b..143ef058f 100644 --- a/pipelined/srt/testgen.c +++ b/pipelined/srt/testgen.c @@ -28,7 +28,7 @@ double random_input(void); void main(void) { FILE *fptr; - double a, b, r; + double x1, x2, a, b, r; double list[ENTRIES] = {1, 1.5, 1.25, 1.125, 1.0625, 1.75, 1.875, 1.99999, 1.1, 1.2, 1.01, 1.001, 1.0001, @@ -63,6 +63,7 @@ void main(void) void output(FILE *fptr, double a, double b, double r) { + printhex(fptr, a); fprintf(fptr, "_"); printhex(fptr, b); diff --git a/pipelined/testbench/common/instrNameDecTB.sv b/pipelined/testbench/common/instrNameDecTB.sv index 7ed309764..f0aaba92d 100644 --- a/pipelined/testbench/common/instrNameDecTB.sv +++ b/pipelined/testbench/common/instrNameDecTB.sv @@ -102,7 +102,6 @@ module instrNameDecTB( 10'b1101111_???: name = "JAL"; 10'b1110011_000: if (imm == 0) name = "ECALL"; else if (imm == 1) name = "EBREAK"; - else if (imm == 2) name = "URET"; else if (imm == 258) name = "SRET"; else if (imm == 770) name = "MRET"; else if (funct7 == 9) name = "SFENCE.VMA"; diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 9cce5847f..0a2aa706d 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -1483,13 +1483,13 @@ string imperas32f[] = '{ string wally64priv[] = '{ `WALLYTEST, - "rv64i_m/privilege/WALLY-MMU-SV39", "30A0", - "rv64i_m/privilege/WALLY-MMU-SV48", "30A0", - "rv64i_m/privilege/WALLY-PMP", "30A0", - "rv64i_m/privilege/WALLY-PMA", "30A0", - "rv64i_m/privilege/WALLY-minfo-01", "30A0", - "rv64i_m/privilege/WALLY-CSR-permission-s-01", "40A0", - "rv64i_m/privilege/WALLY-CSR-permission-u-01", "40A0" + "rv64i_m/privilege/WALLY-MMU-SV39", "40A0", + "rv64i_m/privilege/WALLY-MMU-SV48", "40A0", + "rv64i_m/privilege/WALLY-PMP", "40A0", + "rv64i_m/privilege/WALLY-PMA", "40A0", + "rv64i_m/privilege/WALLY-minfo-01", "40A0", + "rv64i_m/privilege/WALLY-CSR-permission-s-01", "50A0", + "rv64i_m/privilege/WALLY-CSR-permission-u-01", "50A0" }; string wally64periph[] = '{ @@ -1548,9 +1548,11 @@ string wally32i[] = '{ string wally32priv[] = '{ `WALLYTEST, - "rv32i_m/privilege/WALLY-MMU-SV32", "3080", - "rv32i_m/privilege/WALLY-PMP", "3080", - "rv32i_m/privilege/WALLY-PMA", "3080" + "rv32i_m/privilege/WALLY-MMU-SV32", "4080", + "rv32i_m/privilege/WALLY-PMP", "4080", + "rv32i_m/privilege/WALLY-CSR-permission-s-01", "5080", + "rv32i_m/privilege/WALLY-CSR-permission-u-01", "5080", + "rv32i_m/privilege/WALLY-minfo-01", "4080" }; string wally32periph[] = '{ diff --git a/synthDC/Makefile b/synthDC/Makefile index eecb952c6..aa148802d 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -7,17 +7,53 @@ NAME := synth export DESIGN ?= wallypipelinedcore export FREQ ?= 500 export CONFIG ?= rv32e -export TECH ?= 130 +# sky130 and sky90 presently supported +export TECH ?= sky130 +# MAXCORES allows parallel compilation, which is faster but less CPU-efficient +# Avoid when doing sweeps of many optimization points in parallel +export MAXCORES ?= 4 +# MAXOPT turns on flattening, boundary optimization, and retiming +# The output netlist is hard to interpret, but significantly better PPA +export MAXOPT ?= 0 time := $(shell date +%F-%H-%M) hash := $(shell git rev-parse --short HEAD) export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(hash) export SAIFPOWER ?= 0 +CONFIGDIR ?= ~/riscv-wally/pipelined/config +#CONFIGS ?= $(shell find $(CONFIGDIR) -name "rv*") +CONFIGS ?= ("rv32e", "rv32ic") + +print: + echo "files in $(CONFIGDIR) are $(CONFIGS)." + default: - @echo "Basic synthesis procedure for OSU/HMC/UNLV:" - @echo " adapt Makefile to your liking..." - @echo + @echo "Basic synthesis procedure for Wally:" + @echo " Invoke with make synth" + +test: rv% + echo "Running test on $<" + +rv%.log: rv% + echo $< + +flavors: + rm -rf $(CONFIGDIR)/rv32em + cp -r $(CONFIGDIR)/rv32e $(CONFIGDIR)/rv32em + sed -i 's/h00000010/h00001010/' $(CONFIGDIR)/rv32em/wally-config.vh + # rv32e, 32ic, 32gc 64ic, 64gc + # 64gc - FPU + # PMP16 + # PMP0 + # No virtual memory + # Muldiv + + +allsynth: + make flavors + make synth DESIGN=wallypipelinedcore CONFIG=rv32e TECH=sky90 FREQ=500 MAXCORES=1 + make synth DESIGN=wallypipelinedcore CONFIG=rv32em TECH=sky90 FREQ=500 MAXCORES=1 synth: @echo "DC Synthesis" diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 5b21e94e8..3146e14ed 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -10,6 +10,9 @@ suppress_message {VER-130} suppress_message {VER-281} suppress_message {VER-173} +# Enable Multicore +set_host_options -max_cores $::env(MAXCORES) + # get outputDir from environment (Makefile) set outputDir $::env(OUTPUTDIR) set cfgName $::env(CONFIG) @@ -17,6 +20,7 @@ set cfgName $::env(CONFIG) set hdl_src "../pipelined/src" set cfg "${hdl_src}/../config/${cfgName}/wally-config.vh" set saifpower $::env(SAIFPOWER) +set maxopt $::env(MAXOPT) eval file copy -force ${cfg} {hdl/} eval file copy -force ${cfg} $outputDir @@ -65,7 +69,7 @@ if { $saifpower == 1 } { # Set reset false path set_false_path -from [get_ports reset] -# Set Frequency in [MHz] or [ps] +# Set Frequency in [MHz] or period in [ns] set my_clock_pin clk set my_uncertainty 0.0 set my_clk_freq_MHz $::env(FREQ) @@ -84,13 +88,20 @@ if { $find_clock != [list] } { create_clock -period $my_period -name $my_clk } +# Optimize paths that are close to critical +set_critical_range [expr $my_period*0.05] $current_design + # Partitioning - flatten or hierarchically synthesize -# ungroup -all -flatten -simple_names +if { $maxopt == 1 } { + ungroup -all -flatten -simple_names +} # Set input pins except clock set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]] # Specifies delays be propagated through the clock network +# This is getting optimized poorly in the current flow, causing a lot of clock skew +# and unrealistic bad timing results. # set_propagated_clock [get_clocks $my_clk] # Setting constraints on input ports @@ -101,8 +112,8 @@ if {$tech == "sky130"} { } # Set input/output delay -set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk -set_output_delay 0.0 -max -clock $my_clk [all_outputs] +set_input_delay 0.1 -max -clock $my_clk $all_in_ex_clk +set_output_delay 0.1 -max -clock $my_clk [all_outputs] # Setting load constraint on output ports if {$tech == "sky130"} { @@ -120,7 +131,7 @@ set_wire_load_mode "top" # Set fanout set_max_fanout 6 $all_in_ex_clk -# Fix hold time violations +# Fix hold time violations (DH: this doesn't seem to be working right now) #set_fix_hold [all_clocks] # Deal with constants and buffers to isolate ports @@ -132,11 +143,16 @@ set_fix_multiple_port_nets -all -buffer_constants # group_path -name COMBO -from [all_inputs] -to [all_outputs] # Save Unmapped Design -set filename [format "%s%s%s%s" $outputDir "/unmapped/" $my_toplevel ".ddc"] -write_file -format ddc -hierarchy -o $filename +#set filename [format "%s%s%s%s" $outputDir "/unmapped/" $my_toplevel ".ddc"] +#write_file -format ddc -hierarchy -o $filename # Compile statements -compile_ultra -no_seq_output_inversion -no_boundary_optimization +if { $maxopt == 1 } { + compile_ultra -retime + optimize_registers +} else { + compile_ultra -no_seq_output_inversion -no_boundary_optimization +} # Eliminate need for assign statements (yuck!) set verilogout_no_tri true @@ -160,7 +176,7 @@ redirect $filename {report_constraint -all_violators} redirect $outputDir/reports/check_design.rpt { check_design } # Report Final Netlist (Hierarchical) -set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".vh"] +set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sv"] write_file -f verilog -hierarchy -output $filename set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sdc"] @@ -178,14 +194,17 @@ redirect $filename { report_qor } # Report Timing set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_reportpath.rep"] -redirect $filename { report_path_group } +#redirect $filename { report_path_group } set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_report_clock.rep"] -redirect $filename { report_clock } +# redirect $filename { report_clock } set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_timing.rep"] redirect $filename { report_timing -capacitance -transition_time -nets -nworst 1 } +set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_mindelay.rep"] +redirect $filename { report_timing -capacitance -transition_time -nets -delay_type min -nworst 1 } + set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_per_module_timing.rep"] redirect -append $filename { echo "\n\n\n//// Critical paths through ifu ////\n\n\n" } redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/*} -nworst 1 } @@ -265,20 +284,14 @@ redirect -append $filename { echo "\n\n\n//// Critical path through FlushW ////\ redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushW} -nworst 1 } set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_ieu_timing.rep"] -redirect -append $filename { echo "\n\n\n//// Critical path through datapath/RD1D ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/RD1D} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical path through datapath/RD2D ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/RD2D} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical path through datapath/PreSrcAE ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/PreSrcAE} -nworst 1 } +redirect -append $filename { echo "\n\n\n//// Critical path through datapath/R1D ////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/R1D} -nworst 1 } +redirect -append $filename { echo "\n\n\n//// Critical path through datapath/R2D ////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/R2D} -nworst 1 } redirect -append $filename { echo "\n\n\n//// Critical path through datapath/SrcAE ////\n\n\n" } redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/SrcAE} -nworst 1 } redirect -append $filename { echo "\n\n\n//// Critical path through datapath/ALUResultE ////\n\n\n" } redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ALUResultE} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical path through datapath/WriteDataE ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/WriteDataE} -nworst 1 } -redirect -append $filename { echo "\n\n\n//// Critical path through dataphath/ResultM ////\n\n\n" } -redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ResultM} -nworst 1 } redirect -append $filename { echo "\n\n\n//// Critical path through datapath/WriteDataW ////\n\n\n" } redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/WriteDataW} -nworst 1 } redirect -append $filename { echo "\n\n\n//// Critical path through datapath/ReadDataM ////\n\n\n" } @@ -323,7 +336,7 @@ set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_area.rep" redirect $filename { report_area -hierarchy -nosplit -physical -designware} set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_cell.rep"] -redirect $filename { report_cell [get_cells -hier *] } +# redirect $filename { report_cell [get_cells -hier *] } set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_power.rep"] redirect $filename { report_power -hierarchy -levels 1 } @@ -332,6 +345,6 @@ set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_constrain redirect $filename { report_constraint } set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_hier.rep"] -redirect $filename { report_hierarchy } +# redirect $filename { report_hierarchy } quit diff --git a/tests/wally-riscv-arch-test/riscv-test-env/verify.sh b/tests/wally-riscv-arch-test/riscv-test-env/verify.sh index 543854982..6a809b730 100755 --- a/tests/wally-riscv-arch-test/riscv-test-env/verify.sh +++ b/tests/wally-riscv-arch-test/riscv-test-env/verify.sh @@ -28,15 +28,15 @@ do echo -e "Check $(printf %-24s ${stub}) \e[33m ... IGNORE \e[39m" continue fi - # KMG: changed diff snippet to a grep that will strip comments with '//' and '#' out of the reference file - diff --ignore-case --ignore-trailing-space --strip-trailing-cr <(grep -o '^[^//#]*' ${ref}) ${sig} &> /dev/null + # KMG: changed diff snippet to a grep that will strip comments with '#' out of the reference file + diff --ignore-case --ignore-trailing-space --strip-trailing-cr <(grep -o '^[^#]*' ${ref}) ${sig} &> /dev/null if [ $? == 0 ] then echo -e "\e[32m ... OK \e[39m" else echo -e "\e[31m ... FAIL \e[39m" FAIL=$((${FAIL} + 1)) - sdiff ${ref} ${sig} > ${dif} + sdiff <(grep -o '^[^#]*' ${ref}) ${sig} > ${dif} fi done diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include b/tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include index ae84be741..fe5f14aaa 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include +++ b/tests/wally-riscv-arch-test/riscv-test-suite/Makefile.include @@ -63,9 +63,8 @@ copy: $(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!) $(info <<<<<<<<<<<<<<<<<<<<<<<<<<<< COPYING REFERENCES WITHOUT SIMULATING >>>>>>>>>>>>>>>>>>>>>>>>>>>>) $(info !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!) - $(V) echo "Copying References without simulating for the following tests:" - $(V) echo $(target_tests_nosim) - $(V) for test in $(target_tests_nosim); do grep -o '^[^//#]*' $(ref_dir)/$$test.reference_output > $(work_dir_isa)/$$test.signature.output; done + $(V) echo "Copying References without simulating for the following tests: $(target_tests_nosim)" + $(V) for test in $(target_tests_nosim); do grep -o '^[^#]*' $(ref_dir)/$$test.reference_output > $(work_dir_isa)/$$test.signature.output; done compile: $(combined_elf) run: $(target_log) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag index d1e1ac4b7..abd1d1211 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/Makefrag @@ -29,7 +29,10 @@ rv32i_sc_tests = \ WALLY-MMU-SV32 \ - WALLY-PMP + WALLY-PMP \ + WALLY-CSR-permission-s-01 \ + WALLY-CSR-permission-u-01 \ + WALLY-minfo-01 target_tests_nosim = WALLY-PMA \ diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-CSR-permission-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-CSR-permission-s-01.reference_output new file mode 100644 index 000000000..4327e2c31 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-CSR-permission-s-01.reference_output @@ -0,0 +1,1024 @@ +0000000b # Test 5.2.3.6: ecall from going to S mode from M mode +00000002 # S mode write to pmpcfg1 with illegal instruction +00000002 # S mode read from pmpcfg1 with illegal instruction +00000bad +00000002 # S mode write to pmpcfg3 with illegal instruction +00000002 # S mode read from pmpcfg3 with illegal instruction +00000bad +00000002 # S mode write to mcycleh with illegal instruction +00000002 # S mode read from mcycleh with illegal instruction +00000bad +00000002 # S mode write to minstreth with illegal instruction +00000002 # S mode read from minstreth with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter3h with illegal instruction +00000002 # S mode read from mhpmcounter3h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter4h with illegal instruction +00000002 # S mode read from mhpmcounter4h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter5h with illegal instruction +00000002 # S mode read from mhpmcounter5h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter6h with illegal instruction +00000002 # S mode read from mhpmcounter6h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter7h with illegal instruction +00000002 # S mode read from mhpmcounter7h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter8h with illegal instruction +00000002 # S mode read from mhpmcounter8h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter9h with illegal instruction +00000002 # S mode read from mhpmcounter9h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter10h with illegal instruction +00000002 # S mode read from mhpmcounter10h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter11h with illegal instruction +00000002 # S mode read from mhpmcounter11h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter12h with illegal instruction +00000002 # S mode read from mhpmcounter12h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter13h with illegal instruction +00000002 # S mode read from mhpmcounter13h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter14h with illegal instruction +00000002 # S mode read from mhpmcounter14h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter15h with illegal instruction +00000002 # S mode read from mhpmcounter15h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter16h with illegal instruction +00000002 # S mode read from mhpmcounter16h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter17h with illegal instruction +00000002 # S mode read from mhpmcounter17h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter18h with illegal instruction +00000002 # S mode read from mhpmcounter18h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter19h with illegal instruction +00000002 # S mode read from mhpmcounter19h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter20h with illegal instruction +00000002 # S mode read from mhpmcounter20h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter21h with illegal instruction +00000002 # S mode read from mhpmcounter21h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter22h with illegal instruction +00000002 # S mode read from mhpmcounter22h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter23h with illegal instruction +00000002 # S mode read from mhpmcounter23h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter24h with illegal instruction +00000002 # S mode read from mhpmcounter24h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter25h with illegal instruction +00000002 # S mode read from mhpmcounter25h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter26h with illegal instruction +00000002 # S mode read from mhpmcounter26h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter27h with illegal instruction +00000002 # S mode read from mhpmcounter27h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter28h with illegal instruction +00000002 # S mode read from mhpmcounter28h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter29h with illegal instruction +00000002 # S mode read from mhpmcounter29h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter30h with illegal instruction +00000002 # S mode read from mhpmcounter30h with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter31h with illegal instruction +00000002 # S mode read from mhpmcounter31h with illegal instruction +00000bad +00000002 # S mode write to mvendorid with illegal instruction +00000002 # S mode read from mvendorid with illegal instruction +00000bad +00000002 # S mode write to marchid with illegal instruction +00000002 # S mode read from marchid with illegal instruction +00000bad +00000002 # S mode write to mimpid with illegal instruction +00000002 # S mode read from mimpid with illegal instruction +00000bad +00000002 # S mode write to mhartid with illegal instruction +00000002 # S mode read from mhartid with illegal instruction +00000bad +00000002 # S mode write to mstatus with illegal instruction +00000002 # S mode read from mstatus with illegal instruction +00000bad +00000002 # S mode write to misa with illegal instruction +00000002 # S mode read from misa with illegal instruction +00000bad +00000002 # S mode write to medeleg with illegal instruction +00000002 # S mode read from medeleg with illegal instruction +00000bad +00000002 # S mode write to mideleg with illegal instruction +00000002 # S mode read from mideleg with illegal instruction +00000bad +00000002 # S mode write to mie with illegal instruction +00000002 # S mode read from mie with illegal instruction +00000bad +00000002 # S mode write to mtvec with illegal instruction +00000002 # S mode read from mtvec with illegal instruction +00000bad +00000002 # S mode write to mcounteren with illegal instruction +00000002 # S mode read from mcounteren with illegal instruction +00000bad +00000002 # S mode write to mscratch with illegal instruction +00000002 # S mode read from mscratch with illegal instruction +00000bad +00000002 # S mode write to mepc with illegal instruction +00000002 # S mode read from mepc with illegal instruction +00000bad +00000002 # S mode write to mcause with illegal instruction +00000002 # S mode read from mcause with illegal instruction +00000bad +00000002 # S mode write to mtval with illegal instruction +00000002 # S mode read from mtval with illegal instruction +00000bad +00000002 # S mode write to mip with illegal instruction +00000002 # S mode read from mip with illegal instruction +00000bad +00000002 # S mode write to pmpcfg0 with illegal instruction +00000002 # S mode read from pmpcfg0 with illegal instruction +00000bad +00000002 # S mode write to pmpcfg2 with illegal instruction +00000002 # S mode read from pmpcfg2 with illegal instruction +00000bad +00000002 # S mode write to pmpaddr0 with illegal instruction +00000002 # S mode read from pmpaddr0 with illegal instruction +00000bad +00000002 # S mode write to pmpaddr1 with illegal instruction +00000002 # S mode read from pmpaddr1 with illegal instruction +00000bad +00000002 # S mode write to pmpaddr2 with illegal instruction +00000002 # S mode read from pmpaddr2 with illegal instruction +00000bad +00000002 # S mode write to pmpaddr3 with illegal instruction +00000002 # S mode read from pmpaddr3 with illegal instruction +00000bad +00000002 # S mode write to pmpaddr4 with illegal instruction +00000002 # S mode read from pmpaddr4 with illegal instruction +00000bad +00000002 # S mode write to pmpaddr5 with illegal instruction +00000002 # S mode read from pmpaddr5 with illegal instruction +00000bad +00000002 # S mode write to pmpaddr6 with illegal instruction +00000002 # S mode read from pmpaddr6 with illegal instruction +00000bad +00000002 # S mode write to pmpaddr7 with illegal instruction +00000002 # S mode read from pmpaddr7 with illegal instruction +00000bad +00000002 # S mode write to pmpaddr8 with illegal instruction +00000002 # S mode read from pmpaddr8 with illegal instruction +00000bad +00000002 # S mode write to pmpaddr9 with illegal instruction +00000002 # S mode read from pmpaddr9 with illegal instruction +00000bad +00000002 # S mode write to pmpaddr10 with illegal instruction +00000002 # S mode read from pmpaddr10 with illegal instruction +00000bad +00000002 # S mode write to pmpaddr11 with illegal instruction +00000002 # S mode read from pmpaddr11 with illegal instruction +00000bad +00000002 # S mode write to pmpaddr12 with illegal instruction +00000002 # S mode read from pmpaddr12 with illegal instruction +00000bad +00000002 # S mode write to pmpaddr13 with illegal instruction +00000002 # S mode read from pmpaddr13 with illegal instruction +00000bad +00000002 # S mode write to pmpaddr14 with illegal instruction +00000002 # S mode read from pmpaddr14 with illegal instruction +00000bad +00000002 # S mode write to pmpaddr15 with illegal instruction +00000002 # S mode read from pmpaddr15 with illegal instruction +00000bad +00000002 # S mode write to mcycle with illegal instruction +00000002 # S mode read from mcycle with illegal instruction +00000bad +00000002 # S mode write to minstret with illegal instruction +00000002 # S mode read from minstret with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter3 with illegal instruction +00000002 # S mode read from mhpmcounter3 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter4 with illegal instruction +00000002 # S mode read from mhpmcounter4 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter5 with illegal instruction +00000002 # S mode read from mhpmcounter5 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter6 with illegal instruction +00000002 # S mode read from mhpmcounter6 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter7 with illegal instruction +00000002 # S mode read from mhpmcounter7 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter8 with illegal instruction +00000002 # S mode read from mhpmcounter8 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter9 with illegal instruction +00000002 # S mode read from mhpmcounter9 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter10 with illegal instruction +00000002 # S mode read from mhpmcounter10 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter11 with illegal instruction +00000002 # S mode read from mhpmcounter11 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter12 with illegal instruction +00000002 # S mode read from mhpmcounter12 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter13 with illegal instruction +00000002 # S mode read from mhpmcounter13 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter14 with illegal instruction +00000002 # S mode read from mhpmcounter14 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter15 with illegal instruction +00000002 # S mode read from mhpmcounter15 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter16 with illegal instruction +00000002 # S mode read from mhpmcounter16 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter17 with illegal instruction +00000002 # S mode read from mhpmcounter17 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter18 with illegal instruction +00000002 # S mode read from mhpmcounter18 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter19 with illegal instruction +00000002 # S mode read from mhpmcounter19 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter20 with illegal instruction +00000002 # S mode read from mhpmcounter20 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter21 with illegal instruction +00000002 # S mode read from mhpmcounter21 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter22 with illegal instruction +00000002 # S mode read from mhpmcounter22 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter23 with illegal instruction +00000002 # S mode read from mhpmcounter23 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter24 with illegal instruction +00000002 # S mode read from mhpmcounter24 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter25 with illegal instruction +00000002 # S mode read from mhpmcounter25 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter26 with illegal instruction +00000002 # S mode read from mhpmcounter26 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter27 with illegal instruction +00000002 # S mode read from mhpmcounter27 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter28 with illegal instruction +00000002 # S mode read from mhpmcounter28 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter29 with illegal instruction +00000002 # S mode read from mhpmcounter29 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter30 with illegal instruction +00000002 # S mode read from mhpmcounter30 with illegal instruction +00000bad +00000002 # S mode write to mhpmcounter31 with illegal instruction +00000002 # S mode read from mhpmcounter31 with illegal instruction +00000bad +00000002 # S mode write to mcountinhibit with illegal instruction +00000002 # S mode read from mcountinhibit with illegal instruction +00000bad +00000002 # S mode write to mhpmevent3 with illegal instruction +00000002 # S mode read from mhpmevent3 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent4 with illegal instruction +00000002 # S mode read from mhpmevent4 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent5 with illegal instruction +00000002 # S mode read from mhpmevent5 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent6 with illegal instruction +00000002 # S mode read from mhpmevent6 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent7 with illegal instruction +00000002 # S mode read from mhpmevent7 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent8 with illegal instruction +00000002 # S mode read from mhpmevent8 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent9 with illegal instruction +00000002 # S mode read from mhpmevent9 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent10 with illegal instruction +00000002 # S mode read from mhpmevent10 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent11 with illegal instruction +00000002 # S mode read from mhpmevent11 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent12 with illegal instruction +00000002 # S mode read from mhpmevent12 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent13 with illegal instruction +00000002 # S mode read from mhpmevent13 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent14 with illegal instruction +00000002 # S mode read from mhpmevent14 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent15 with illegal instruction +00000002 # S mode read from mhpmevent15 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent16 with illegal instruction +00000002 # S mode read from mhpmevent16 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent17 with illegal instruction +00000002 # S mode read from mhpmevent17 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent18 with illegal instruction +00000002 # S mode read from mhpmevent18 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent19 with illegal instruction +00000002 # S mode read from mhpmevent19 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent20 with illegal instruction +00000002 # S mode read from mhpmevent20 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent21 with illegal instruction +00000002 # S mode read from mhpmevent21 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent22 with illegal instruction +00000002 # S mode read from mhpmevent22 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent23 with illegal instruction +00000002 # S mode read from mhpmevent23 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent24 with illegal instruction +00000002 # S mode read from mhpmevent24 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent25 with illegal instruction +00000002 # S mode read from mhpmevent25 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent26 with illegal instruction +00000002 # S mode read from mhpmevent26 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent27 with illegal instruction +00000002 # S mode read from mhpmevent27 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent28 with illegal instruction +00000002 # S mode read from mhpmevent28 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent29 with illegal instruction +00000002 # S mode read from mhpmevent29 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent30 with illegal instruction +00000002 # S mode read from mhpmevent30 with illegal instruction +00000bad +00000002 # S mode write to mhpmevent31 with illegal instruction +00000002 # S mode read from mhpmevent31 with illegal instruction +00000bad +00000009 # ecall from terminating tess from S mode +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-CSR-permission-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-CSR-permission-u-01.reference_output new file mode 100644 index 000000000..8069d08a9 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-CSR-permission-u-01.reference_output @@ -0,0 +1,1024 @@ +0000000b # Test 5.2.3.6: ecall from going to U mode from M mode +00000002 # U mode write to sstatus with illegal instruction +00000002 # U mode read from sstatus with illegal instruction +00000bad +00000002 # U mode write to sie with illegal instruction +00000002 # U mode read from sie with illegal instruction +00000bad +00000002 # U mode write to stvec with illegal instruction +00000002 # U mode read from stvec with illegal instruction +00000bad +00000002 # U mode write to scounteren with illegal instruction +00000002 # U mode read from scounteren with illegal instruction +00000bad +00000002 # U mode write to sscratch with illegal instruction +00000002 # U mode read from sscratch with illegal instruction +00000bad +00000002 # U mode write to sepc with illegal instruction +00000002 # U mode read from sepc with illegal instruction +00000bad +00000002 # U mode write to scause with illegal instruction +00000002 # U mode read from scause with illegal instruction +00000bad +00000002 # U mode write to stval with illegal instruction +00000002 # U mode read from stval with illegal instruction +00000bad +00000002 # U mode write to sip with illegal instruction +00000002 # U mode read from sip with illegal instruction +00000bad +00000002 # U mode write to satp with illegal instruction +00000002 # U mode read from satp with illegal instruction +00000bad +00000002 # U mode write to mvendorid with illegal instruction +00000002 # U mode read from mvendorid with illegal instruction +00000bad +00000002 # U mode write to marchid with illegal instruction +00000002 # U mode read from marchid with illegal instruction +00000bad +00000002 # U mode write to mimpid with illegal instruction +00000002 # U mode read from mimpid with illegal instruction +00000bad +00000002 # U mode write to mhartid with illegal instruction +00000002 # U mode read from mhartid with illegal instruction +00000bad +00000002 # U mode write to mstatus with illegal instruction +00000002 # U mode read from mstatus with illegal instruction +00000bad +00000002 # U mode write to misa with illegal instruction +00000002 # U mode read from misa with illegal instruction +00000bad +00000002 # U mode write to medeleg with illegal instruction +00000002 # U mode read from medeleg with illegal instruction +00000bad +00000002 # U mode write to mideleg with illegal instruction +00000002 # U mode read from mideleg with illegal instruction +00000bad +00000002 # U mode write to mie with illegal instruction +00000002 # U mode read from mie with illegal instruction +00000bad +00000002 # U mode write to mtvec with illegal instruction +00000002 # U mode read from mtvec with illegal instruction +00000bad +00000002 # U mode write to mcounteren with illegal instruction +00000002 # U mode read from mcounteren with illegal instruction +00000bad +00000002 # U mode write to mscratch with illegal instruction +00000002 # U mode read from mscratch with illegal instruction +00000bad +00000002 # U mode write to mepc with illegal instruction +00000002 # U mode read from mepc with illegal instruction +00000bad +00000002 # U mode write to mcause with illegal instruction +00000002 # U mode read from mcause with illegal instruction +00000bad +00000002 # U mode write to mtval with illegal instruction +00000002 # U mode read from mtval with illegal instruction +00000bad +00000002 # U mode write to mip with illegal instruction +00000002 # U mode read from mip with illegal instruction +00000bad +00000002 # U mode write to pmpcfg0 with illegal instruction +00000002 # U mode read from pmpcfg0 with illegal instruction +00000bad +00000002 # U mode write to pmpcfg2 with illegal instruction +00000002 # U mode read from pmpcfg2 with illegal instruction +00000bad +00000002 # U mode write to pmpaddr0 with illegal instruction +00000002 # U mode read from pmpaddr0 with illegal instruction +00000bad +00000002 # U mode write to pmpaddr1 with illegal instruction +00000002 # U mode read from pmpaddr1 with illegal instruction +00000bad +00000002 # U mode write to pmpaddr2 with illegal instruction +00000002 # U mode read from pmpaddr2 with illegal instruction +00000bad +00000002 # U mode write to pmpaddr3 with illegal instruction +00000002 # U mode read from pmpaddr3 with illegal instruction +00000bad +00000002 # U mode write to pmpaddr4 with illegal instruction +00000002 # U mode read from pmpaddr4 with illegal instruction +00000bad +00000002 # U mode write to pmpaddr5 with illegal instruction +00000002 # U mode read from pmpaddr5 with illegal instruction +00000bad +00000002 # U mode write to pmpaddr6 with illegal instruction +00000002 # U mode read from pmpaddr6 with illegal instruction +00000bad +00000002 # U mode write to pmpaddr7 with illegal instruction +00000002 # U mode read from pmpaddr7 with illegal instruction +00000bad +00000002 # U mode write to pmpaddr8 with illegal instruction +00000002 # U mode read from pmpaddr8 with illegal instruction +00000bad +00000002 # U mode write to pmpaddr9 with illegal instruction +00000002 # U mode read from pmpaddr9 with illegal instruction +00000bad +00000002 # U mode write to pmpaddr10 with illegal instruction +00000002 # U mode read from pmpaddr10 with illegal instruction +00000bad +00000002 # U mode write to pmpaddr11 with illegal instruction +00000002 # U mode read from pmpaddr11 with illegal instruction +00000bad +00000002 # U mode write to pmpaddr12 with illegal instruction +00000002 # U mode read from pmpaddr12 with illegal instruction +00000bad +00000002 # U mode write to pmpaddr13 with illegal instruction +00000002 # U mode read from pmpaddr13 with illegal instruction +00000bad +00000002 # U mode write to pmpaddr14 with illegal instruction +00000002 # U mode read from pmpaddr14 with illegal instruction +00000bad +00000002 # U mode write to pmpaddr15 with illegal instruction +00000002 # U mode read from pmpaddr15 with illegal instruction +00000bad +00000002 # U mode write to mcycle with illegal instruction +00000002 # U mode read from mcycle with illegal instruction +00000bad +00000002 # U mode write to minstret with illegal instruction +00000002 # U mode read from minstret with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter3 with illegal instruction +00000002 # U mode read from mhpmcounter3 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter4 with illegal instruction +00000002 # U mode read from mhpmcounter4 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter5 with illegal instruction +00000002 # U mode read from mhpmcounter5 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter6 with illegal instruction +00000002 # U mode read from mhpmcounter6 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter7 with illegal instruction +00000002 # U mode read from mhpmcounter7 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter8 with illegal instruction +00000002 # U mode read from mhpmcounter8 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter9 with illegal instruction +00000002 # U mode read from mhpmcounter9 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter10 with illegal instruction +00000002 # U mode read from mhpmcounter10 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter11 with illegal instruction +00000002 # U mode read from mhpmcounter11 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter12 with illegal instruction +00000002 # U mode read from mhpmcounter12 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter13 with illegal instruction +00000002 # U mode read from mhpmcounter13 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter14 with illegal instruction +00000002 # U mode read from mhpmcounter14 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter15 with illegal instruction +00000002 # U mode read from mhpmcounter15 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter16 with illegal instruction +00000002 # U mode read from mhpmcounter16 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter17 with illegal instruction +00000002 # U mode read from mhpmcounter17 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter18 with illegal instruction +00000002 # U mode read from mhpmcounter18 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter19 with illegal instruction +00000002 # U mode read from mhpmcounter19 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter20 with illegal instruction +00000002 # U mode read from mhpmcounter20 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter21 with illegal instruction +00000002 # U mode read from mhpmcounter21 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter22 with illegal instruction +00000002 # U mode read from mhpmcounter22 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter23 with illegal instruction +00000002 # U mode read from mhpmcounter23 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter24 with illegal instruction +00000002 # U mode read from mhpmcounter24 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter25 with illegal instruction +00000002 # U mode read from mhpmcounter25 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter26 with illegal instruction +00000002 # U mode read from mhpmcounter26 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter27 with illegal instruction +00000002 # U mode read from mhpmcounter27 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter28 with illegal instruction +00000002 # U mode read from mhpmcounter28 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter29 with illegal instruction +00000002 # U mode read from mhpmcounter29 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter30 with illegal instruction +00000002 # U mode read from mhpmcounter30 with illegal instruction +00000bad +00000002 # U mode write to mhpmcounter31 with illegal instruction +00000002 # U mode read from mhpmcounter31 with illegal instruction +00000bad +00000002 # U mode write to mcountinhibit with illegal instruction +00000002 # U mode read from mcountinhibit with illegal instruction +00000bad +00000002 # U mode write to mhpmevent3 with illegal instruction +00000002 # U mode read from mhpmevent3 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent4 with illegal instruction +00000002 # U mode read from mhpmevent4 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent5 with illegal instruction +00000002 # U mode read from mhpmevent5 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent6 with illegal instruction +00000002 # U mode read from mhpmevent6 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent7 with illegal instruction +00000002 # U mode read from mhpmevent7 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent8 with illegal instruction +00000002 # U mode read from mhpmevent8 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent9 with illegal instruction +00000002 # U mode read from mhpmevent9 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent10 with illegal instruction +00000002 # U mode read from mhpmevent10 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent11 with illegal instruction +00000002 # U mode read from mhpmevent11 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent12 with illegal instruction +00000002 # U mode read from mhpmevent12 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent13 with illegal instruction +00000002 # U mode read from mhpmevent13 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent14 with illegal instruction +00000002 # U mode read from mhpmevent14 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent15 with illegal instruction +00000002 # U mode read from mhpmevent15 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent16 with illegal instruction +00000002 # U mode read from mhpmevent16 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent17 with illegal instruction +00000002 # U mode read from mhpmevent17 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent18 with illegal instruction +00000002 # U mode read from mhpmevent18 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent19 with illegal instruction +00000002 # U mode read from mhpmevent19 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent20 with illegal instruction +00000002 # U mode read from mhpmevent20 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent21 with illegal instruction +00000002 # U mode read from mhpmevent21 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent22 with illegal instruction +00000002 # U mode read from mhpmevent22 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent23 with illegal instruction +00000002 # U mode read from mhpmevent23 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent24 with illegal instruction +00000002 # U mode read from mhpmevent24 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent25 with illegal instruction +00000002 # U mode read from mhpmevent25 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent26 with illegal instruction +00000002 # U mode read from mhpmevent26 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent27 with illegal instruction +00000002 # U mode read from mhpmevent27 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent28 with illegal instruction +00000002 # U mode read from mhpmevent28 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent29 with illegal instruction +00000002 # U mode read from mhpmevent29 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent30 with illegal instruction +00000002 # U mode read from mhpmevent30 with illegal instruction +00000bad +00000002 # U mode write to mhpmevent31 with illegal instruction +00000002 # U mode read from mhpmevent31 with illegal instruction +00000bad +00000008 # ecall from terminating tests in U mode +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef 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+deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-minfo-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-minfo-01.reference_output new file mode 100644 index 000000000..55904acab --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-minfo-01.reference_output @@ -0,0 +1,1024 @@ +00000002 # Test 5.2.3.1: write to read-only CSR failed with illegal instruction +00000011 # confirm read-only permissions of mvendorid +00000002 # write to read-only CSR failed with illegal instruction +00000011 # confirm read-only permissions of marchid +00000002 # write to read-only CSR failed with illegal instruction +00000011 # confirm read-only permissions of mimpid +00000002 # write to read-only CSR failed with illegal instruction +00000011 # confirm read-only permissions of mhartid +0000000b # ecall from terminating tests in M mode +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef +deadbeef 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and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-32.h" + +INIT_TESTS + +s_file_begin: + +# Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in S mode. + +# *** several of these appear not to be implemented in the assembler? +# I get "assembler messages: error: unkown CSR" with many of them. + +GOTO_S_MODE 0x0, 0x0 + +# Attempt to write 0xbad to each of these CSRs and read the value back +# should result in an illegal instruction for the write and read, respectively + +# High-bit versions storing the upper 32 bits of some CSRs for RV32 +# WRITE_READ_CSR mstatush 0xbad # *** these appear not to be implemented in GCC +# WRITE_READ_CSR menvcfgh 0xbad +# WRITE_READ_CSR mseccfgh 0xbad +WRITE_READ_CSR pmpcfg1 0xbad +WRITE_READ_CSR pmpcfg3 0xbad +WRITE_READ_CSR mcycleh 0xbad +WRITE_READ_CSR minstreth 0xbad +WRITE_READ_CSR mhpmcounter3h 0xbad +WRITE_READ_CSR mhpmcounter4h 0xbad +WRITE_READ_CSR mhpmcounter5h 0xbad +WRITE_READ_CSR mhpmcounter6h 0xbad +WRITE_READ_CSR mhpmcounter7h 0xbad +WRITE_READ_CSR mhpmcounter8h 0xbad +WRITE_READ_CSR mhpmcounter9h 0xbad +WRITE_READ_CSR mhpmcounter10h 0xbad +WRITE_READ_CSR mhpmcounter11h 0xbad +WRITE_READ_CSR mhpmcounter12h 0xbad +WRITE_READ_CSR mhpmcounter13h 0xbad +WRITE_READ_CSR mhpmcounter14h 0xbad +WRITE_READ_CSR mhpmcounter15h 0xbad +WRITE_READ_CSR mhpmcounter16h 0xbad +WRITE_READ_CSR mhpmcounter17h 0xbad +WRITE_READ_CSR mhpmcounter18h 0xbad +WRITE_READ_CSR mhpmcounter19h 0xbad +WRITE_READ_CSR mhpmcounter20h 0xbad +WRITE_READ_CSR mhpmcounter21h 0xbad +WRITE_READ_CSR mhpmcounter22h 0xbad +WRITE_READ_CSR mhpmcounter23h 0xbad +WRITE_READ_CSR mhpmcounter24h 0xbad +WRITE_READ_CSR mhpmcounter25h 0xbad +WRITE_READ_CSR mhpmcounter26h 0xbad +WRITE_READ_CSR mhpmcounter27h 0xbad +WRITE_READ_CSR mhpmcounter28h 0xbad +WRITE_READ_CSR mhpmcounter29h 0xbad +WRITE_READ_CSR mhpmcounter30h 0xbad +WRITE_READ_CSR mhpmcounter31h 0xbad + +# Machine information Registers +WRITE_READ_CSR mvendorid, 0xbad +WRITE_READ_CSR marchid, 0xbad +WRITE_READ_CSR mimpid, 0xbad +WRITE_READ_CSR mhartid, 0xbad +# WRITE_READ_CSR mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22 + +# Machine Trap Setup +WRITE_READ_CSR mstatus, 0xbad +WRITE_READ_CSR misa, 0xbad +WRITE_READ_CSR medeleg, 0xbad +WRITE_READ_CSR mideleg, 0xbad +WRITE_READ_CSR mie, 0xbad +WRITE_READ_CSR mtvec, 0xbad +WRITE_READ_CSR mcounteren, 0xbad + +# Machine Trap Handling +WRITE_READ_CSR mscratch, 0xbad +WRITE_READ_CSR mepc, 0xbad +WRITE_READ_CSR mcause, 0xbad +WRITE_READ_CSR mtval, 0xbad +WRITE_READ_CSR mip, 0xbad +# WRITE_READ_CSR mtinst, 0xbad # *** these appear not to be implemented in GCC +# WRITE_READ_CSR mtval2, 0xbad + +# Machine Configuration +# WRITE_READ_CSR menvcfg, 0xbad # *** these appear not to be implemented in GCC +# WRITE_READ_CSR mseccgf, 0xbad + +# Machine Memory Protection +WRITE_READ_CSR pmpcfg0, 0xbad +WRITE_READ_CSR pmpcfg2, 0xbad # there's 1 pmpcfg reg per 8 pmpaddr regs + +WRITE_READ_CSR pmpaddr0, 0xbad +WRITE_READ_CSR pmpaddr1, 0xbad +WRITE_READ_CSR pmpaddr2, 0xbad +WRITE_READ_CSR pmpaddr3, 0xbad +WRITE_READ_CSR pmpaddr4, 0xbad +WRITE_READ_CSR pmpaddr5, 0xbad +WRITE_READ_CSR pmpaddr6, 0xbad +WRITE_READ_CSR pmpaddr7, 0xbad +WRITE_READ_CSR pmpaddr8, 0xbad +WRITE_READ_CSR pmpaddr9, 0xbad +WRITE_READ_CSR pmpaddr10, 0xbad +WRITE_READ_CSR pmpaddr11, 0xbad +WRITE_READ_CSR pmpaddr12, 0xbad +WRITE_READ_CSR pmpaddr13, 0xbad +WRITE_READ_CSR pmpaddr14, 0xbad +WRITE_READ_CSR pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config + +# Machine Counter/Timers +WRITE_READ_CSR mcycle, 0xbad +WRITE_READ_CSR minstret, 0xbad +WRITE_READ_CSR mhpmcounter3, 0xbad +WRITE_READ_CSR mhpmcounter4, 0xbad +WRITE_READ_CSR mhpmcounter5, 0xbad +WRITE_READ_CSR mhpmcounter6, 0xbad +WRITE_READ_CSR mhpmcounter7, 0xbad +WRITE_READ_CSR mhpmcounter8, 0xbad +WRITE_READ_CSR mhpmcounter9, 0xbad +WRITE_READ_CSR mhpmcounter10, 0xbad +WRITE_READ_CSR mhpmcounter11, 0xbad +WRITE_READ_CSR mhpmcounter12, 0xbad +WRITE_READ_CSR mhpmcounter13, 0xbad +WRITE_READ_CSR mhpmcounter14, 0xbad +WRITE_READ_CSR mhpmcounter15, 0xbad +WRITE_READ_CSR mhpmcounter16, 0xbad +WRITE_READ_CSR mhpmcounter17, 0xbad +WRITE_READ_CSR mhpmcounter18, 0xbad +WRITE_READ_CSR mhpmcounter19, 0xbad +WRITE_READ_CSR mhpmcounter20, 0xbad +WRITE_READ_CSR mhpmcounter21, 0xbad +WRITE_READ_CSR mhpmcounter22, 0xbad +WRITE_READ_CSR mhpmcounter23, 0xbad +WRITE_READ_CSR mhpmcounter24, 0xbad +WRITE_READ_CSR mhpmcounter25, 0xbad +WRITE_READ_CSR mhpmcounter26, 0xbad +WRITE_READ_CSR mhpmcounter27, 0xbad +WRITE_READ_CSR mhpmcounter28, 0xbad +WRITE_READ_CSR mhpmcounter29, 0xbad +WRITE_READ_CSR mhpmcounter30, 0xbad +WRITE_READ_CSR mhpmcounter31, 0xbad + +# Machine Counter Setup +WRITE_READ_CSR mcountinhibit, 0xbad +WRITE_READ_CSR mhpmevent3, 0xbad +WRITE_READ_CSR mhpmevent4, 0xbad +WRITE_READ_CSR mhpmevent5, 0xbad +WRITE_READ_CSR mhpmevent6, 0xbad +WRITE_READ_CSR mhpmevent7, 0xbad +WRITE_READ_CSR mhpmevent8, 0xbad +WRITE_READ_CSR mhpmevent9, 0xbad +WRITE_READ_CSR mhpmevent10, 0xbad +WRITE_READ_CSR mhpmevent11, 0xbad +WRITE_READ_CSR mhpmevent12, 0xbad +WRITE_READ_CSR mhpmevent13, 0xbad +WRITE_READ_CSR mhpmevent14, 0xbad +WRITE_READ_CSR mhpmevent15, 0xbad +WRITE_READ_CSR mhpmevent16, 0xbad +WRITE_READ_CSR mhpmevent17, 0xbad +WRITE_READ_CSR mhpmevent18, 0xbad +WRITE_READ_CSR mhpmevent19, 0xbad +WRITE_READ_CSR mhpmevent20, 0xbad +WRITE_READ_CSR mhpmevent21, 0xbad +WRITE_READ_CSR mhpmevent22, 0xbad +WRITE_READ_CSR mhpmevent23, 0xbad +WRITE_READ_CSR mhpmevent24, 0xbad +WRITE_READ_CSR mhpmevent25, 0xbad +WRITE_READ_CSR mhpmevent26, 0xbad +WRITE_READ_CSR mhpmevent27, 0xbad +WRITE_READ_CSR mhpmevent28, 0xbad +WRITE_READ_CSR mhpmevent29, 0xbad +WRITE_READ_CSR mhpmevent30, 0xbad +WRITE_READ_CSR mhpmevent31, 0xbad + +END_TESTS + +TEST_STACK_AND_DATA \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-u-01.S new file mode 100644 index 000000000..190b6ed24 --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-CSR-permission-u-01.S @@ -0,0 +1,173 @@ +/////////////////////////////////////////// +// +// WALLY-CSR-permissions +// +// Author: Kip Macsai-Goren +// +// Created 2022-02-05 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-32.h" + +INIT_TESTS + +s_file_begin: + +# Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in R mode. + +GOTO_U_MODE 0x0, 0x0 + +# Attempt to write 0xbad to each of these CSRs and read the value back +# should result in an illegal instruction for the write and read, respectively + +# Supervisor Trap Setup +WRITE_READ_CSR sstatus, 0xbad +WRITE_READ_CSR sie, 0xbad +WRITE_READ_CSR stvec, 0xbad +WRITE_READ_CSR scounteren, 0xbad + +# Supervisor Configuration +# WRITE_READ_CSR senvcfg, 0xbad # *** these appear not to be implemented in the compile step of make??? + +# Supervisor Trap Handling +WRITE_READ_CSR sscratch, 0xbad +WRITE_READ_CSR sepc, 0xbad +WRITE_READ_CSR scause, 0xbad +WRITE_READ_CSR stval, 0xbad +WRITE_READ_CSR sip, 0xbad + +# Supervisor Protection and Translation +WRITE_READ_CSR satp, 0xbad + +# Machine information Registers +WRITE_READ_CSR mvendorid, 0xbad +WRITE_READ_CSR marchid, 0xbad +WRITE_READ_CSR mimpid, 0xbad +WRITE_READ_CSR mhartid, 0xbad +# WRITE_READ_CSR mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22 + +# Machine Trap Setup +WRITE_READ_CSR mstatus, 0xbad +WRITE_READ_CSR misa, 0xbad +WRITE_READ_CSR medeleg, 0xbad +WRITE_READ_CSR mideleg, 0xbad +WRITE_READ_CSR mie, 0xbad +WRITE_READ_CSR mtvec, 0xbad +WRITE_READ_CSR mcounteren, 0xbad + +# Machine Trap Handling +WRITE_READ_CSR mscratch, 0xbad +WRITE_READ_CSR mepc, 0xbad +WRITE_READ_CSR mcause, 0xbad +WRITE_READ_CSR mtval, 0xbad +WRITE_READ_CSR mip, 0xbad +# WRITE_READ_CSR mtinst, 0xbad # *** these appear not to be implemented in GCC +# WRITE_READ_CSR mtval2, 0xbad + +# Machine Configuration +# WRITE_READ_CSR menvcfg, 0xbad # *** these appear not to be implemented in GCC +# WRITE_READ_CSR mseccgf, 0xbad + +# Machine Memory Protection +WRITE_READ_CSR pmpcfg0, 0xbad +WRITE_READ_CSR pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs + +WRITE_READ_CSR pmpaddr0, 0xbad +WRITE_READ_CSR pmpaddr1, 0xbad +WRITE_READ_CSR pmpaddr2, 0xbad +WRITE_READ_CSR pmpaddr3, 0xbad +WRITE_READ_CSR pmpaddr4, 0xbad +WRITE_READ_CSR pmpaddr5, 0xbad +WRITE_READ_CSR pmpaddr6, 0xbad +WRITE_READ_CSR pmpaddr7, 0xbad +WRITE_READ_CSR pmpaddr8, 0xbad +WRITE_READ_CSR pmpaddr9, 0xbad +WRITE_READ_CSR pmpaddr10, 0xbad +WRITE_READ_CSR pmpaddr11, 0xbad +WRITE_READ_CSR pmpaddr12, 0xbad +WRITE_READ_CSR pmpaddr13, 0xbad +WRITE_READ_CSR pmpaddr14, 0xbad +WRITE_READ_CSR pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config + +# Machine Counter/Timers +WRITE_READ_CSR mcycle, 0xbad +WRITE_READ_CSR minstret, 0xbad +WRITE_READ_CSR mhpmcounter3, 0xbad +WRITE_READ_CSR mhpmcounter4, 0xbad +WRITE_READ_CSR mhpmcounter5, 0xbad +WRITE_READ_CSR mhpmcounter6, 0xbad +WRITE_READ_CSR mhpmcounter7, 0xbad +WRITE_READ_CSR mhpmcounter8, 0xbad +WRITE_READ_CSR mhpmcounter9, 0xbad +WRITE_READ_CSR mhpmcounter10, 0xbad +WRITE_READ_CSR mhpmcounter11, 0xbad +WRITE_READ_CSR mhpmcounter12, 0xbad +WRITE_READ_CSR mhpmcounter13, 0xbad +WRITE_READ_CSR mhpmcounter14, 0xbad +WRITE_READ_CSR mhpmcounter15, 0xbad +WRITE_READ_CSR mhpmcounter16, 0xbad +WRITE_READ_CSR mhpmcounter17, 0xbad +WRITE_READ_CSR mhpmcounter18, 0xbad +WRITE_READ_CSR mhpmcounter19, 0xbad +WRITE_READ_CSR mhpmcounter20, 0xbad +WRITE_READ_CSR mhpmcounter21, 0xbad +WRITE_READ_CSR mhpmcounter22, 0xbad +WRITE_READ_CSR mhpmcounter23, 0xbad +WRITE_READ_CSR mhpmcounter24, 0xbad +WRITE_READ_CSR mhpmcounter25, 0xbad +WRITE_READ_CSR mhpmcounter26, 0xbad +WRITE_READ_CSR mhpmcounter27, 0xbad +WRITE_READ_CSR mhpmcounter28, 0xbad +WRITE_READ_CSR mhpmcounter29, 0xbad +WRITE_READ_CSR mhpmcounter30, 0xbad +WRITE_READ_CSR mhpmcounter31, 0xbad + +# Machine Counter Setup +WRITE_READ_CSR mcountinhibit, 0xbad +WRITE_READ_CSR mhpmevent3, 0xbad +WRITE_READ_CSR mhpmevent4, 0xbad +WRITE_READ_CSR mhpmevent5, 0xbad +WRITE_READ_CSR mhpmevent6, 0xbad +WRITE_READ_CSR mhpmevent7, 0xbad +WRITE_READ_CSR mhpmevent8, 0xbad +WRITE_READ_CSR mhpmevent9, 0xbad +WRITE_READ_CSR mhpmevent10, 0xbad +WRITE_READ_CSR mhpmevent11, 0xbad +WRITE_READ_CSR mhpmevent12, 0xbad +WRITE_READ_CSR mhpmevent13, 0xbad +WRITE_READ_CSR mhpmevent14, 0xbad +WRITE_READ_CSR mhpmevent15, 0xbad +WRITE_READ_CSR mhpmevent16, 0xbad +WRITE_READ_CSR mhpmevent17, 0xbad +WRITE_READ_CSR mhpmevent18, 0xbad +WRITE_READ_CSR mhpmevent19, 0xbad +WRITE_READ_CSR mhpmevent20, 0xbad +WRITE_READ_CSR mhpmevent21, 0xbad +WRITE_READ_CSR mhpmevent22, 0xbad +WRITE_READ_CSR mhpmevent23, 0xbad +WRITE_READ_CSR mhpmevent24, 0xbad +WRITE_READ_CSR mhpmevent25, 0xbad +WRITE_READ_CSR mhpmevent26, 0xbad +WRITE_READ_CSR mhpmevent27, 0xbad +WRITE_READ_CSR mhpmevent28, 0xbad +WRITE_READ_CSR mhpmevent29, 0xbad +WRITE_READ_CSR mhpmevent30, 0xbad +WRITE_READ_CSR mhpmevent31, 0xbad + +END_TESTS + +TEST_STACK_AND_DATA \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MMU-SV32.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MMU-SV32.S index 91681f81d..69ba260b3 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MMU-SV32.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-MMU-SV32.S @@ -22,9 +22,18 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-32.h" -// Test library includes and handler for each type of test, a trap handler, imperas compliance instructions -// Ideally this should mean that a test can be written by simply adding .8byte statements as below. +INIT_TESTS + +s_file_begin: +j test_loop_setup // begin test loop/table tests instead of executing inline code. + +INIT_TEST_TABLE + +TEST_STACK_AND_DATA + +.align 2 +test_cases: # --------------------------------------------------------------------------------------------- # Test Contents # diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S index 80d6d504f..475a6dd83 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMA.S @@ -35,9 +35,18 @@ #define PLIC_RANGE 0x03FFFFFF #include "WALLY-TEST-LIB-32.h" -// Test library includes and handler for each type of test, a trap handler, imperas compliance instructions -// Ideally this should mean that a test can be written by simply adding .4byte statements as below. +INIT_TESTS + +s_file_begin: +j test_loop_setup // begin test loop/table tests instead of executing inline code. + +INIT_TEST_TABLE + +TEST_STACK_AND_DATA + +.align 2 +test_cases: # --------------------------------------------------------------------------------------------- # Test Contents # diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMP.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMP.S index 887bfd97f..d1d02cf20 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMP.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-PMP.S @@ -22,9 +22,18 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-32.h" -// Test library includes and handler for each type of test, a trap handler, imperas compliance instructions -// Ideally this should mean that a test can be written by simply adding .4byte statements as below. +INIT_TESTS + +s_file_begin: +j test_loop_setup // begin test loop/table tests instead of executing inline code. + +INIT_TEST_TABLE + +TEST_STACK_AND_DATA + +.align 2 +test_cases: # --------------------------------------------------------------------------------------------- # Test Contents # @@ -45,22 +54,22 @@ # Test 12.3.2.2.1 Config: Write known values and set PMP config according to table 12.4 in the *** riscv book, copied below # write pmpaddr regs - # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments | -.4byte 0x0, 0x0FFFFFFF, write_pmpaddr_0 # | 0 | 0x0FFFFFFF | 1F | 0 | NAPOT | 0 | 1 | 1 | I/O 00000000-7FFFFFFF RW | -.4byte 0x1, 0x20040000, write_pmpaddr_0 # | 1 | 0x20040000 | 00 | 0 | OFF | 0 | 0 | 0 | | -.4byte 0x2, 0x2004003F, write_pmpaddr_0 # | 2 | 0x2004003F | 09 | 0 | TOR | 0 | 0 | 1 | 80100000-801000FF R | -.4byte 0x3, 0x20040080, write_pmpaddr_0 # | 3 | 0x20040080 | 00 | 0 | OFF | 0 | 0 | 0 | | -.4byte 0x4, 0x20040084, write_pmpaddr_0 # | 4 | 0x20040084 | 0C | 0 | TOR | 1 | 0 | 0 | 80100200-80100210 X | -.4byte 0x5, 0x200400C0, write_pmpaddr_0 # | 5 | 0x200400C0 | 90 | 1 | NA4 | 0 | 0 | 0 | 80100300-80100303 locked out | -.4byte 0x6, 0x2004013F, write_pmpaddr_0 # | 6 | 0x2004013F | 18 | 0 | NAPOT | 0 | 0 | 0 | 80100400-801004FF no access | + # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments | +.4byte 0x0, 0x0FFFFFFF, write_pmpaddr_0 # | 0 | 0x0FFFFFFF | 1F | 0 | NAPOT | 0 | 1 | 1 | I/O 00000000-7FFFFFFF RW | +.4byte 0x1, 0x20040000, write_pmpaddr_1 # | 1 | 0x20040000 | 00 | 0 | OFF | 0 | 0 | 0 | | +.4byte 0x2, 0x2004003F, write_pmpaddr_2 # | 2 | 0x2004003F | 09 | 0 | TOR | 0 | 0 | 1 | 80100000-801000FF R | +.4byte 0x3, 0x20040080, write_pmpaddr_3 # | 3 | 0x20040080 | 00 | 0 | OFF | 0 | 0 | 0 | | +.4byte 0x4, 0x20040084, write_pmpaddr_4 # | 4 | 0x20040084 | 0C | 0 | TOR | 1 | 0 | 0 | 80100200-80100210 X | +.4byte 0x5, 0x200400C0, write_pmpaddr_5 # | 5 | 0x200400C0 | 90 | 1 | NA4 | 0 | 0 | 0 | 80100300-80100303 locked out | +.4byte 0x6, 0x2004013F, write_pmpaddr_6 # | 6 | 0x2004013F | 18 | 0 | NAPOT | 0 | 0 | 0 | 80100400-801004FF no access | # Pmpaddr 7-14 are all zeroed out in this test, so they don't need writes. -.4byte 0xF, 0x2FFFFFFF, write_pmpaddr_0 # | 15 | 0x2FFFFFFF | 1F | 0 | NAPOT | 1 | 1 | 1 | Main mem 80000000-FFFFFFFF RWX| +.4byte 0xF, 0x2FFFFFFF, write_pmpaddr_15 # | 15 | 0x2FFFFFFF | 1F | 0 | NAPOT | 1 | 1 | 1 | Main mem 80000000-FFFFFFFF RWX| # write pmpcfg regs with the information in the table above. this should also write the value of these registers to the output. .4byte 0x0, 0x0009001F, write_pmpcfg_0 # write pmpcfg0, output 0x0009001F -.4byte 0x1, 0x0018900C, write_pmpcfg_0 # write pmpcfg1, output 0x0018900C +.4byte 0x1, 0x0018900C, write_pmpcfg_1 # write pmpcfg1, output 0x0018900C # pmpcfg2 is zeroed out, so it doesn't need a write -.4byte 0x3, 0x1F000000, write_pmpcfg_0 # write pmpcfg3, output 0x1F000000 +.4byte 0x3, 0x1F000000, write_pmpcfg_3 # write pmpcfg3, output 0x1F000000 # write known values to memory where W=0. This should be possible since we're in machine mode. .4byte 0x80100010, 0x600DAA, write32_test # write to pmpaddr 1-2 range @@ -74,9 +83,9 @@ # attempt to write to pmpaddr5 and pmp5cfg after lockout -.4byte 0x1, 0x0018FF0C, write_pmpcfg_0 # attempt to edit only pmp5cfg (pmpcfg1[8:15]) after lockout. +.4byte 0x1, 0x0018FF0C, write_pmpcfg_1 # attempt to edit only pmp5cfg (pmpcfg1[8:15]) after lockout. # instruction ignored, output is 0x0018900C, NOT 0x0018FF0C -.4byte 0x5, 0xFFFFFFFF, write_pmpaddr_0 # attempt to edit pmpaddr5 after lockout. +.4byte 0x5, 0xFFFFFFFF, write_pmpaddr_5 # attempt to edit pmpaddr5 after lockout. # instruction ignored, output is 0x200400C0, NOT 0xFFFFFFFF # Test 12.3.2.2.2 Machine mode access diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index 31bd11940..b96ee15a1 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -4,7 +4,7 @@ // // Author: Kip Macsai-Goren // -// Created 2021-07-20 +// Created 2021-07-19 // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // @@ -23,6 +23,9 @@ #include "model_test.h" #include "arch_test.h" + +.macro INIT_TESTS + RVTEST_ISA("RV32I") .section .text.init @@ -31,7 +34,7 @@ rvtest_entry_point: RVMODEL_BOOT RVTEST_CODE_BEGIN - // --------------------------------------------------------------------------------------------- + // --------------------------------------------------------------------------------------------- // Initialization Overview: // // Initialize x6 as a virtual pointer to the test results @@ -56,9 +59,9 @@ RVTEST_CODE_BEGIN li a1, 0 li a2, 0 // reset trap handler inputs to zero - // go to first test! - j test_setup - + // go to beginning of S file where we can decide between using the test data loop + // or using the macro inline code insertion + j s_file_begin // --------------------------------------------------------------------------------------------- // General traps Handler @@ -225,12 +228,16 @@ ecallhandler_changetousermode: j trapreturn instrfault: - lw x1, -4(sp) // load return address int x1 (the address after the jal into faulting page) + lw x1, -4(sp) // load return address int x1 (the address AFTER the jal into faulting page) j trapreturn_finished // puts x1 into mepc, restores stack and returns to program (outside of faulting page) +illegalinstr: + j trapreturn // return to the code after recording the mcause + accessfault: // *** What do I have to do here? j trapreturn + // Table of trap behavior // lists what to do on each exception (not interrupts) // unexpected exceptions should cause segfaults for easy detection @@ -239,13 +246,13 @@ accessfault: .align 2 // aligns this data table to an 4 byte boundary trap_handler_vector_table: .4byte segfault // 0: instruction address misaligned - .4byte instrfault // 1: instruction access fault - .4byte segfault // 2: illegal instruction + .4byte instrfault // 1: instruction access fault + .4byte illegalinstr // 2: illegal instruction .4byte segfault // 3: breakpoint .4byte segfault // 4: load address misaligned - .4byte accessfault // 5: load access fault + .4byte accessfault // 5: load access fault .4byte segfault // 6: store address misaligned - .4byte accessfault // 7: store access fault + .4byte accessfault // 7: store access fault .4byte ecallhandler // 8: ecall from U-mode .4byte ecallhandler // 9: ecall from S-mode .4byte segfault // 10: reserved @@ -260,6 +267,220 @@ trap_return_pagetype_table: .4byte 0xC // 0: kilopage has 12 offset bits .4byte 0x16 // 1: megapage has 22 offset bits +.endm + +// Test Summary table! + +// Test Name : Description : Fault output value : Normal output values +// ---------------------:-------------------------------------------:-------------------------------------------:------------------------------------------------------ +// write64_test : Write 64 bits to address : 0x6, 0x7, or 0xf : None +// write32_test : Write 32 bits to address : 0x6, 0x7, or 0xf : None +// write16_test : Write 16 bits to address : 0x6, 0x7, or 0xf : None +// write08_test : Write 8 bits to address : 0x6, 0x7, or 0xf : None +// read64_test : Read 64 bits from address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex +// read32_test : Read 32 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex +// read16_test : Read 16 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex +// read08_test : Read 8 bitsfrom address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex +// executable_test : test executable on virtual page : 0x0, 0x1, or 0xc, then 0xbad : value of x7 modified by exectuion code (usually 0x111) +// terminate_test : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// goto_baremetal : satp.MODE = bare metal : None : None +// goto_sv32 : satp.MODE = sv32 : None : None +// goto_m_mode : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// goto_s_mode : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// goto_u_mode : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// write_read_csr : write to specified CSR : old CSR value, 0x2, depending on perms : value written to CSR +// csr_r_access : test read-only permissions on CSR : 0xbad : 0x2, then 0x11 + +// *** TESTS TO ADD: execute inline, read unknown value out, read CSR unknown value, just read CSR value + +.macro WRITE32 ADDR VAL + // attempt to write VAL to ADDR + // Success outputs: + // None + // Fault outputs: + // 0x6: misaligned address + // 0x7: access fault + // 0xf: page fault + li x29, \VAL + li x30, \ADDR + sw x29, 0(x30) +.endm + +.macro WRITE16 ADDR VAL + // all write tests have the same description/outputs as write64 + li x29, \VAL + li x30, \ADDR + sh x29, 0(x30) +.endm + +.macro WRITE08 ADDR VAL + // all write tests have the same description/outputs as write64 + li x29, \VAL + li x30, \ADDR + sb x29, 0(x30) +.endm + +.macro READ32 ADDR + // Attempt read at ADDR. Write the value read out to the output *** Consider adding specific test for reading a non known value + // Success outputs: + // value read out from ADDR + // Fault outputs: + // One of the following followed by 0xBAD + // 0x4: misaligned address + // 0x5: access fault + // 0xD: page fault + li x7, 0xBAD // bad value that will be overwritten on good reads. + li x29, \ADDR + lw x7, 0(x29) + sw x7, 0(x6) + addi x6, x6, 4 + addi x16, x16, 4 +.endm + +.macro READ16 ADDR + // All reads have the same description/outputs as read32. + // They will store the sign extended value of what was read out at ADDR + li x7, 0xBAD // bad value that will be overwritten on good reads. + li x29, \ADDR + lh x7, 0(x29) + sw x7, 0(x6) + addi x6, x6, 4 + addi x16, x16, 4 +.endm + +.macro READ08 ADDR + // All reads have the same description/outputs as read64. + // They will store the sign extended value of what was read out at ADDR + li x7, 0xBAD // bad value that will be overwritten on good reads. + li x29, \ADDR + lb x7, 0(x29) + sw x7, 0(x6) + addi x6, x6, 4 + addi x16, x16, 4 +.endm + +// These goto_x_mode tests all involve invoking the trap handler, +// So their outputs are inevitably: +// 0x8: test called from U mode +// 0x9: test called from S mode +// 0xB: test called from M mode +// they generally do not fault or cause issues as long as these modes are enabled +// *** add functionality to check if modes are enabled before jumping? maybe cause a fault if not? + +.macro GOTO_M_MODE RETURN_VPN RETURN_PAGETYPE + li a0, 2 // determine trap handler behavior (go to machine mode) + li a1, \RETURN_VPN // return VPN + li a2, \RETURN_PAGETYPE // return page types + ecall // writes mcause to the output. + // now in S mode +.endm + +.macro GOTO_S_MODE RETURN_VPN RETURN_PAGETYPE + li a0, 3 // determine trap handler behavior (go to supervisor mode) + li a1, \RETURN_VPN // return VPN + li a2, \RETURN_PAGETYPE // return page types + ecall // writes mcause to the output. + // now in S mode +.endm + +.macro GOTO_U_MODE RETURN_VPN RETURN_PAGETYPE + li a0, 4 // determine trap handler behavior (go to user mode) + li a1, \RETURN_VPN // return VPN + li a2, \RETURN_PAGETYPE // return page types + ecall // writes mcause to the output. + // now in S mode +.endm + +// These tests change virtual memory settings, turning it on/off and changing between types. +// They don't have outputs as any error with turning on virtual memory should reveal itself in the tests *** Consider changing this policy? + +.macro GOTO_BAREMETAL + // Turn translation off + li x7, 0 // satp.MODE value for bare metal (0) + slli x7, x7, 31 + li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location + add x7, x7, x28 + csrw satp, x7 + sfence.vma x0, x0 // *** flushes global pte's as well +.endm + +.macro GOTO_SV32 + // Turn on sv39 virtual memory + li x7, 1 // satp.MODE value for Sv32 (1) + slli x7, x7, 31 + li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location + add x7, x7, x28 + csrw satp, x7 + sfence.vma x0, x0 // *** flushes global pte's as well +.endm + +.macro WRITE_READ_CSR CSR VAL + // attempt to write CSR with VAL. Note: this also tests read access to CSR + // Success outputs: + // value read back out from CSR after writing + // Fault outputs: + // The previous CSR value before write attempt + // *** Most likely 0x2, the mcause for illegal instruction if we don't have write or read access + li x30, 0xbad // load bad value to be overwritten by csrr + li x29, \VAL + csrw \CSR\(), x29 + csrr x30, \CSR + sw x30, 0(x6) + addi x6, x6, 4 + addi x16, x16, 4 +.endm + +.macro CSR_R_ACCESS CSR + // verify that a csr is accessible to read but not to write + // Success outputs: + // 0x2, then + // 0x11 *** consider changing to something more meaningful + // Fault outputs: + // 0xBAD *** consider changing this one as well. in general, do we need the branching if it hould cause an illegal instruction fault? + csrr x29, \CSR + csrwi \CSR\(), 0xA // Attempt to write a 'random' value to the CSR + csrr x30, \CSR + bne x30, x29, 1f // 1f represents write_access + li x30, 0x11 // Write failed, confirming read only permissions. + j 2f // j r_access_end +1: // w_access (write succeeded, violating read-only) + li x30, 0xBAD +2: // r_access end + sw x30, 0(x6) + addi x6, x6, 4 + addi x16, x16, 4 +.endm + +.macro EXECUTE_AT_ADDRESS ADDR + // Execute the code already written to ADDR, returning the value in x7. + // *** Note: this test itself doesn't write the code to ADDR because it might be callled at a point where we dont have write access to ADDR + // Assumes the code modifies x7, usually to become 0x111. + // Sample code: 0x11100393 (li x7, 0x111), 0x00008067 (ret) + // Success outputs: + // modified value of x7. (0x111 if you use the sample code) + // Fault outputs: + // One of the following followed by 0xBAD + // 0x0: misaligned address + // 0x1: access fault + // 0xC: page fault + fence.i // forces caches and main memory to sync so execution code written to ADDR can run. + li x7, 0xBAD + li x28, \ADDR + jalr x28 // jump to executable test code + sw x7, 0(x6) + addi x6, x6, 4 + addi x16, x16, 4 +.endm + +.macro END_TESTS + // invokes one final ecall to return to machine mode then terminates this program, so the output is + // 0x8: termination called from U mode + // 0x9: termination called from S mode + // 0xB: termination called from M mode + j terminate_test + +.endm + // --------------------------------------------------------------------------------------------- // Test Handler // @@ -269,17 +490,18 @@ trap_return_pagetype_table: // Input parameters: // // x28: - // Address input for the test taking place (think address to read/write, new address to return to, etc...) + // Address input for the test taking place (think: address to read/write, new address to return to, etc...) // // x29: - // Value input for the test taking place (think value to write, any other extra info needed) + // Value input for the test taking place (think: value to write, any other extra info needed) // // x30: - // Test type input that determines which kind of test will take place. Encoding for this input is in the table/case statements below - // + // Label for the location of the test that's about to take place // ------------------------------------------------------------------------------------------------------------------------------------ -test_setup: +.macro INIT_TEST_TABLE // *** Consider renaming this test. to what??? + +test_loop_setup: la x5, test_cases test_loop: @@ -298,25 +520,25 @@ test_loop: jr x30 -// Test Name : Description : Fault output value : Normal output values -// ----------------------:---------------------------------------:------------------------:------------------------------------------------------ -// write32_test : Write 32 bits to address : 0xf : None -// write16_test : Write 16 bits to address : 0xf : None -// write08_test : Write 8 bits to address : 0xf : None -// read32_test : Read 32 bits from address : 0xd, 0xbad : readvalue in hex -// read16_test : Read 16 bits from address : 0xd, 0xbad : readvalue in hex -// read08_test : Read 8 bits from address : 0xd, 0xbad : readvalue in hex -// executable_test : test executable at address : 0xc, 0xbad : leading 12 bits of the li instr written to address. In general this is 0x111. (be sure to also write a return instruction) -// terminate_test : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 -// goto_baremetal : satp.MODE = bare metal : None : None -// goto_sv32 : satp.MODE = sv32 : None : None -// write_mxr_sum : write sstatus.[19:18] = MXR, SUM bits : None : None -// goto_m_mode : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 -// goto_s_mode : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 -// goto_u_mode : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 -// write_pmpcfg_x : Write one of the pmpcfg csr's : mstatuses?, 0xD : readback of pmpcfg value -// write_pmpaddr_x : Write one of the pmpaddr csr's : None : readback of pmpaddr value - +// Test Name : Description : Fault output value : Normal output values +// ----------------------:-------------------------------------------:------------------------:------------------------------------------------------ +// write32_test : Write 32 bits to address : 0xf : None +// write16_test : Write 16 bits to address : 0xf : None +// write08_test : Write 8 bits to address : 0xf : None +// read32_test : Read 32 bits from address : 0xd, 0xbad : readvalue in hex +// read16_test : Read 16 bits from address : 0xd, 0xbad : readvalue in hex +// read08_test : Read 8 bits from address : 0xd, 0xbad : readvalue in hex +// executable_test : test executable on virtual page : 0xc, 0xbad : value of x7 modified by exectuion code (usually 0x111) +// terminate_test : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// goto_baremetal : satp.MODE = bare metal : None : None +// goto_sv39 : satp.MODE = sv39 : None : None +// goto_sv48 : satp.MODE = sv48 : None : None +// write_mxr_sum : write sstatus.[19:18] = MXR, SUM bits : None : None +// goto_m_mode : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// goto_s_mode : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// goto_u_mode : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// write_pmpcfg_x : Write one of the pmpcfg csr's : mstatuses?, 0xD : readback of pmpcfg value +// write_pmpaddr_x : Write one of the pmpaddr csr's : None : readback of pmpaddr value write32_test: // address to write in x28, word value in x29 @@ -360,9 +582,9 @@ read08_test: addi x16, x16, 4 j test_loop // go to next test case - goto_s_mode: - li a0, 3 // Trap handler behavior (go to machine mode) + // return to address in x28, + li a0, 3 // Trap handler behavior (go to supervisor mode) mv a1, x28 // return VPN mv a2, x29 // return page types ecall // writes mcause to the output. @@ -385,21 +607,11 @@ goto_u_mode: goto_baremetal: // Turn translation off - li x7, 0 // satp.MODE value for bare metal (0) - slli x7, x7, 31 - li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. - add x7, x7, x28 - csrw satp, x7 - sfence.vma x0, x0 // *** flushes global pte's as well. Be careful + GOTO_BAREMETAL j test_loop // go to next test case goto_sv32: - li x7, 1 // satp.MODE value for Sv39 (1) - slli x7, x7, 31 - li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. - add x7, x7, x28 - csrw satp, x7 - sfence.vma x0, x0 // *** flushes global pte's as well. Be careful + GOTO_SV32 j test_loop // go to next test case write_mxr_sum: @@ -415,25 +627,26 @@ write_mxr_sum: write_pmpcfg_0: // writes the value in x29 to the pmpcfg register specified in x28. - li x7, 0x0 - bne x7, x28, write_pmpcfg_1 + // then writes the final value of pmpcfgX to the output. csrw pmpcfg0, x29 csrr x30, pmpcfg0 + j write_pmpcfg_end + write_pmpcfg_1: - li x7, 0x1 - bne x7, x28, write_pmpcfg_2 csrw pmpcfg1, x29 - csrr x30, pmpcfg1 + csrr x30, pmpcfg1 + j write_pmpcfg_end + write_pmpcfg_2: - li x7, 0x2 - bne x7, x28, write_pmpcfg_3 csrw pmpcfg2, x29 csrr x30, pmpcfg2 + j write_pmpcfg_end + write_pmpcfg_3: - li x7, 0x3 - bne x7, x28, write_pmpcfg_end csrw pmpcfg3, x29 csrr x30, pmpcfg3 + j write_pmpcfg_end + write_pmpcfg_end: sw x30, 0(x6) addi x6, x6, 4 @@ -441,103 +654,88 @@ write_pmpcfg_end: j test_loop write_pmpaddr_0: + // write_read_csr pmpaddr0, x29 // writes the value in x29 to the pmpaddr register specified in x28. // then writes the final value of pmpaddrX to the output. - li x7, 0x0 - bne x7, x28, write_pmpaddr_1 csrw pmpaddr0, x29 csrr x30, pmpaddr0 j write_pmpaddr_end + write_pmpaddr_1: - li x7, 0x1 - bne x7, x28, write_pmpaddr_2 csrw pmpaddr1, x29 csrr x30, pmpaddr1 j write_pmpaddr_end + write_pmpaddr_2: - li x7, 0x2 - bne x7, x28, write_pmpaddr_3 csrw pmpaddr2, x29 csrr x30, pmpaddr2 j write_pmpaddr_end + write_pmpaddr_3: - li x7, 0x3 - bne x7, x28, write_pmpaddr_4 csrw pmpaddr3, x29 csrr x30, pmpaddr3 j write_pmpaddr_end + write_pmpaddr_4: - li x7, 0x4 - bne x7, x28, write_pmpaddr_5 csrw pmpaddr4, x29 csrr x30, pmpaddr4 j write_pmpaddr_end + write_pmpaddr_5: - li x7, 0x5 - bne x7, x28, write_pmpaddr_6 csrw pmpaddr5, x29 csrr x30, pmpaddr5 j write_pmpaddr_end + write_pmpaddr_6: - li x7, 0x6 - bne x7, x28, write_pmpaddr_7 csrw pmpaddr6, x29 csrr x30, pmpaddr6 j write_pmpaddr_end + write_pmpaddr_7: - li x7, 0x7 - bne x7, x28, write_pmpaddr_8 csrw pmpaddr7, x29 csrr x30, pmpaddr7 j write_pmpaddr_end + write_pmpaddr_8: - li x7, 0x8 - bne x7, x28, write_pmpaddr_9 csrw pmpaddr8, x29 csrr x30, pmpaddr8 j write_pmpaddr_end + write_pmpaddr_9: - li x7, 0x9 - bne x7, x28, write_pmpaddr_10 csrw pmpaddr9, x29 csrr x30, pmpaddr9 j write_pmpaddr_end + write_pmpaddr_10: - li x7, 0xA - bne x7, x28, write_pmpaddr_11 csrw pmpaddr10, x29 csrr x30, pmpaddr10 j write_pmpaddr_end + write_pmpaddr_11: - li x7, 0xB - bne x7, x28, write_pmpaddr_12 csrw pmpaddr11, x29 csrr x30, pmpaddr11 j write_pmpaddr_end + write_pmpaddr_12: - li x7, 0xC - bne x7, x28, write_pmpaddr_13 csrw pmpaddr12, x29 csrr x30, pmpaddr12 j write_pmpaddr_end + write_pmpaddr_13: - li x7, 0xD - bne x7, x28, write_pmpaddr_14 csrw pmpaddr13, x29 csrr x30, pmpaddr13 j write_pmpaddr_end + write_pmpaddr_14: - li x7, 0xE - bne x7, x28, write_pmpaddr_15 csrw pmpaddr14, x29 csrr x30, pmpaddr14 j write_pmpaddr_end + write_pmpaddr_15: - li x7, 0xF - bne x7, x28, write_pmpaddr_end csrw pmpaddr15, x29 csrr x30, pmpaddr15 j write_pmpaddr_end + write_pmpaddr_end: sw x30, 0(x6) addi x6, x6, 4 @@ -555,18 +753,21 @@ executable_test: addi x16, x16, 4 j test_loop +.endm - +// notably, terminate_test is not a part of the test table macro because it needs to be defined +// in any type of test, macro or test table, for the trap handler to work terminate_test: li a0, 2 // Trap handler behavior (go to machine mode) ecall // writes mcause to the output. csrw mtvec, x4 // restore original trap handler to halt program - RVTEST_CODE_END RVMODEL_HALT +.macro TEST_STACK_AND_DATA + RVTEST_DATA_BEGIN .align 4 rvtest_data: @@ -575,14 +776,12 @@ RVTEST_DATA_END .align 2 // align stack to 4 byte boundary bottom_of_stack: - .fill 1024, 4, 0xdeadbeef + .fill 1024, 4, 0xdeadbeef top_of_stack: - RVMODEL_DATA_BEGIN -// next lines through test cases copied over from old framework test_1_res: .fill 1024, 4, 0xdeadbeef @@ -602,6 +801,4 @@ gpr_save: #endif -.align 2 -test_cases: - +.endm diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-minfo-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-minfo-01.S new file mode 100644 index 000000000..9d1803a9f --- /dev/null +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-minfo-01.S @@ -0,0 +1,39 @@ +/////////////////////////////////////////// +// +// WALLY-MMU +// +// Author: Kip Macsai-Goren +// +// Created 2022-01-25 +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + +#include "WALLY-TEST-LIB-32.h" + +INIT_TESTS + +s_file_begin: + +// Test 5.2.3.1: testing Read-only access to Machine info CSRs +CSR_R_ACCESS mvendorid +CSR_R_ACCESS marchid +CSR_R_ACCESS mimpid +CSR_R_ACCESS mhartid +# CSR_R_ACCESS mconfigptr # Unimplemented in spike as of 31 Jan 22 + +END_TESTS + +TEST_STACK_AND_DATA \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-s-01.S index ce1069834..927e8653c 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-s-01.S @@ -21,133 +21,137 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -#include "WALLY-TEST-MACROS-64.h" +#include "WALLY-TEST-LIB-64.h" INIT_TESTS +s_file_begin: + # Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in S mode. # *** several of these appear not to be implemented in the assembler? # I get "assembler messages: error: unkown CSR" with many of them. -goto_s_mode 0x0, 0x0 +GOTO_S_MODE 0x0, 0x0 # Attempt to write 0xbad to each of these CSRs and read the value back # should result in an illegal instruction for the write and read, respectively # Machine information Registers -write_read_csr mvendorid, 0xbad -write_read_csr marchid, 0xbad -write_read_csr mimpid, 0xbad -write_read_csr mhartid, 0xbad -# write_read_csr mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22 +WRITE_READ_CSR mvendorid, 0xbad +WRITE_READ_CSR marchid, 0xbad +WRITE_READ_CSR mimpid, 0xbad +WRITE_READ_CSR mhartid, 0xbad +# WRITE_READ_CSR mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22 # Machine Trap Setup -write_read_csr mstatus, 0xbad -write_read_csr misa, 0xbad -write_read_csr medeleg, 0xbad -write_read_csr mideleg, 0xbad -write_read_csr mie, 0xbad -write_read_csr mtvec, 0xbad -write_read_csr mcounteren, 0xbad +WRITE_READ_CSR mstatus, 0xbad +WRITE_READ_CSR misa, 0xbad +WRITE_READ_CSR medeleg, 0xbad +WRITE_READ_CSR mideleg, 0xbad +WRITE_READ_CSR mie, 0xbad +WRITE_READ_CSR mtvec, 0xbad +WRITE_READ_CSR mcounteren, 0xbad # Machine Trap Handling -write_read_csr mscratch, 0xbad -write_read_csr mepc, 0xbad -write_read_csr mcause, 0xbad -write_read_csr mtval, 0xbad -write_read_csr mip, 0xbad -# write_read_csr mtinst, 0xbad # *** these appear not to be implemented in the compile step of make??? -# write_read_csr mtval2, 0xbad +WRITE_READ_CSR mscratch, 0xbad +WRITE_READ_CSR mepc, 0xbad +WRITE_READ_CSR mcause, 0xbad +WRITE_READ_CSR mtval, 0xbad +WRITE_READ_CSR mip, 0xbad +# WRITE_READ_CSR mtinst, 0xbad # *** these appear not to be implemented in GCC +# WRITE_READ_CSR mtval2, 0xbad # Machine Configuration -# write_read_csr menvcfg, 0xbad # *** these appear not to be implemented in the compile step of make??? -# write_read_csr mseccgf, 0xbad +# WRITE_READ_CSR menvcfg, 0xbad # *** these appear not to be implemented in GCC +# WRITE_READ_CSR mseccgf, 0xbad # Machine Memory Protection -write_read_csr pmpcfg0, 0xbad -write_read_csr pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs +WRITE_READ_CSR pmpcfg0, 0xbad +WRITE_READ_CSR pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs -write_read_csr pmpaddr0, 0xbad -write_read_csr pmpaddr1, 0xbad -write_read_csr pmpaddr2, 0xbad -write_read_csr pmpaddr3, 0xbad -write_read_csr pmpaddr4, 0xbad -write_read_csr pmpaddr5, 0xbad -write_read_csr pmpaddr6, 0xbad -write_read_csr pmpaddr7, 0xbad -write_read_csr pmpaddr8, 0xbad -write_read_csr pmpaddr9, 0xbad -write_read_csr pmpaddr10, 0xbad -write_read_csr pmpaddr11, 0xbad -write_read_csr pmpaddr12, 0xbad -write_read_csr pmpaddr13, 0xbad -write_read_csr pmpaddr14, 0xbad -write_read_csr pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config +WRITE_READ_CSR pmpaddr0, 0xbad +WRITE_READ_CSR pmpaddr1, 0xbad +WRITE_READ_CSR pmpaddr2, 0xbad +WRITE_READ_CSR pmpaddr3, 0xbad +WRITE_READ_CSR pmpaddr4, 0xbad +WRITE_READ_CSR pmpaddr5, 0xbad +WRITE_READ_CSR pmpaddr6, 0xbad +WRITE_READ_CSR pmpaddr7, 0xbad +WRITE_READ_CSR pmpaddr8, 0xbad +WRITE_READ_CSR pmpaddr9, 0xbad +WRITE_READ_CSR pmpaddr10, 0xbad +WRITE_READ_CSR pmpaddr11, 0xbad +WRITE_READ_CSR pmpaddr12, 0xbad +WRITE_READ_CSR pmpaddr13, 0xbad +WRITE_READ_CSR pmpaddr14, 0xbad +WRITE_READ_CSR pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config # Machine Counter/Timers -write_read_csr mcycle, 0xbad -write_read_csr minstret, 0xbad -write_read_csr mhpmcounter3, 0xbad -write_read_csr mhpmcounter4, 0xbad -write_read_csr mhpmcounter5, 0xbad -write_read_csr mhpmcounter6, 0xbad -write_read_csr mhpmcounter7, 0xbad -write_read_csr mhpmcounter8, 0xbad -write_read_csr mhpmcounter9, 0xbad -write_read_csr mhpmcounter10, 0xbad -write_read_csr mhpmcounter11, 0xbad -write_read_csr mhpmcounter12, 0xbad -write_read_csr mhpmcounter13, 0xbad -write_read_csr mhpmcounter14, 0xbad -write_read_csr mhpmcounter15, 0xbad -write_read_csr mhpmcounter16, 0xbad -write_read_csr mhpmcounter17, 0xbad -write_read_csr mhpmcounter18, 0xbad -write_read_csr mhpmcounter19, 0xbad -write_read_csr mhpmcounter20, 0xbad -write_read_csr mhpmcounter21, 0xbad -write_read_csr mhpmcounter22, 0xbad -write_read_csr mhpmcounter23, 0xbad -write_read_csr mhpmcounter24, 0xbad -write_read_csr mhpmcounter25, 0xbad -write_read_csr mhpmcounter26, 0xbad -write_read_csr mhpmcounter27, 0xbad -write_read_csr mhpmcounter28, 0xbad -write_read_csr mhpmcounter29, 0xbad -write_read_csr mhpmcounter30, 0xbad -write_read_csr mhpmcounter31, 0xbad +WRITE_READ_CSR mcycle, 0xbad +WRITE_READ_CSR minstret, 0xbad +WRITE_READ_CSR mhpmcounter3, 0xbad +WRITE_READ_CSR mhpmcounter4, 0xbad +WRITE_READ_CSR mhpmcounter5, 0xbad +WRITE_READ_CSR mhpmcounter6, 0xbad +WRITE_READ_CSR mhpmcounter7, 0xbad +WRITE_READ_CSR mhpmcounter8, 0xbad +WRITE_READ_CSR mhpmcounter9, 0xbad +WRITE_READ_CSR mhpmcounter10, 0xbad +WRITE_READ_CSR mhpmcounter11, 0xbad +WRITE_READ_CSR mhpmcounter12, 0xbad +WRITE_READ_CSR mhpmcounter13, 0xbad +WRITE_READ_CSR mhpmcounter14, 0xbad +WRITE_READ_CSR mhpmcounter15, 0xbad +WRITE_READ_CSR mhpmcounter16, 0xbad +WRITE_READ_CSR mhpmcounter17, 0xbad +WRITE_READ_CSR mhpmcounter18, 0xbad +WRITE_READ_CSR mhpmcounter19, 0xbad +WRITE_READ_CSR mhpmcounter20, 0xbad +WRITE_READ_CSR mhpmcounter21, 0xbad +WRITE_READ_CSR mhpmcounter22, 0xbad +WRITE_READ_CSR mhpmcounter23, 0xbad +WRITE_READ_CSR mhpmcounter24, 0xbad +WRITE_READ_CSR mhpmcounter25, 0xbad +WRITE_READ_CSR mhpmcounter26, 0xbad +WRITE_READ_CSR mhpmcounter27, 0xbad +WRITE_READ_CSR mhpmcounter28, 0xbad +WRITE_READ_CSR mhpmcounter29, 0xbad +WRITE_READ_CSR mhpmcounter30, 0xbad +WRITE_READ_CSR mhpmcounter31, 0xbad # Machine Counter Setup -write_read_csr mcountinhibit, 0xbad -write_read_csr mhpmevent3, 0xbad -write_read_csr mhpmevent4, 0xbad -write_read_csr mhpmevent5, 0xbad -write_read_csr mhpmevent6, 0xbad -write_read_csr mhpmevent7, 0xbad -write_read_csr mhpmevent8, 0xbad -write_read_csr mhpmevent9, 0xbad -write_read_csr mhpmevent10, 0xbad -write_read_csr mhpmevent11, 0xbad -write_read_csr mhpmevent12, 0xbad -write_read_csr mhpmevent13, 0xbad -write_read_csr mhpmevent14, 0xbad -write_read_csr mhpmevent15, 0xbad -write_read_csr mhpmevent16, 0xbad -write_read_csr mhpmevent17, 0xbad -write_read_csr mhpmevent18, 0xbad -write_read_csr mhpmevent19, 0xbad -write_read_csr mhpmevent20, 0xbad -write_read_csr mhpmevent21, 0xbad -write_read_csr mhpmevent22, 0xbad -write_read_csr mhpmevent23, 0xbad -write_read_csr mhpmevent24, 0xbad -write_read_csr mhpmevent25, 0xbad -write_read_csr mhpmevent26, 0xbad -write_read_csr mhpmevent27, 0xbad -write_read_csr mhpmevent28, 0xbad -write_read_csr mhpmevent29, 0xbad -write_read_csr mhpmevent30, 0xbad -write_read_csr mhpmevent31, 0xbad +WRITE_READ_CSR mcountinhibit, 0xbad +WRITE_READ_CSR mhpmevent3, 0xbad +WRITE_READ_CSR mhpmevent4, 0xbad +WRITE_READ_CSR mhpmevent5, 0xbad +WRITE_READ_CSR mhpmevent6, 0xbad +WRITE_READ_CSR mhpmevent7, 0xbad +WRITE_READ_CSR mhpmevent8, 0xbad +WRITE_READ_CSR mhpmevent9, 0xbad +WRITE_READ_CSR mhpmevent10, 0xbad +WRITE_READ_CSR mhpmevent11, 0xbad +WRITE_READ_CSR mhpmevent12, 0xbad +WRITE_READ_CSR mhpmevent13, 0xbad +WRITE_READ_CSR mhpmevent14, 0xbad +WRITE_READ_CSR mhpmevent15, 0xbad +WRITE_READ_CSR mhpmevent16, 0xbad +WRITE_READ_CSR mhpmevent17, 0xbad +WRITE_READ_CSR mhpmevent18, 0xbad +WRITE_READ_CSR mhpmevent19, 0xbad +WRITE_READ_CSR mhpmevent20, 0xbad +WRITE_READ_CSR mhpmevent21, 0xbad +WRITE_READ_CSR mhpmevent22, 0xbad +WRITE_READ_CSR mhpmevent23, 0xbad +WRITE_READ_CSR mhpmevent24, 0xbad +WRITE_READ_CSR mhpmevent25, 0xbad +WRITE_READ_CSR mhpmevent26, 0xbad +WRITE_READ_CSR mhpmevent27, 0xbad +WRITE_READ_CSR mhpmevent28, 0xbad +WRITE_READ_CSR mhpmevent29, 0xbad +WRITE_READ_CSR mhpmevent30, 0xbad +WRITE_READ_CSR mhpmevent31, 0xbad -END_TESTS \ No newline at end of file +END_TESTS + +TEST_STACK_AND_DATA \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-u-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-u-01.S index d7984d7f6..f68191417 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-u-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-CSR-permission-u-01.S @@ -21,149 +21,153 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -#include "WALLY-TEST-MACROS-64.h" +#include "WALLY-TEST-LIB-64.h" INIT_TESTS +s_file_begin: + # Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in R mode. -goto_u_mode 0x0, 0x0 +GOTO_U_MODE 0x0, 0x0 # Attempt to write 0xbad to each of these CSRs and read the value back # should result in an illegal instruction for the write and read, respectively # Supervisor Trap Setup -write_read_csr sstatus, 0xbad -write_read_csr sie, 0xbad -write_read_csr stvec, 0xbad -write_read_csr scounteren, 0xbad +WRITE_READ_CSR sstatus, 0xbad +WRITE_READ_CSR sie, 0xbad +WRITE_READ_CSR stvec, 0xbad +WRITE_READ_CSR scounteren, 0xbad # Supervisor Configuration -# write_read_csr senvcfg, 0xbad # *** these appear not to be implemented in the compile step of make??? +# WRITE_READ_CSR senvcfg, 0xbad # *** these appear not to be implemented in GCC # Supervisor Trap Handling -write_read_csr sscratch, 0xbad -write_read_csr sepc, 0xbad -write_read_csr scause, 0xbad -write_read_csr stval, 0xbad -write_read_csr sip, 0xbad +WRITE_READ_CSR sscratch, 0xbad +WRITE_READ_CSR sepc, 0xbad +WRITE_READ_CSR scause, 0xbad +WRITE_READ_CSR stval, 0xbad +WRITE_READ_CSR sip, 0xbad # Supervisor Protection and Translation -write_read_csr satp, 0xbad +WRITE_READ_CSR satp, 0xbad # Machine information Registers -write_read_csr mvendorid, 0xbad -write_read_csr marchid, 0xbad -write_read_csr mimpid, 0xbad -write_read_csr mhartid, 0xbad -# write_read_csr mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22 +WRITE_READ_CSR mvendorid, 0xbad +WRITE_READ_CSR marchid, 0xbad +WRITE_READ_CSR mimpid, 0xbad +WRITE_READ_CSR mhartid, 0xbad +# WRITE_READ_CSR mconfigptr, 0xbad # mconfigptr unimplemented in spike as of 31 Jan 22 # Machine Trap Setup -write_read_csr mstatus, 0xbad -write_read_csr misa, 0xbad -write_read_csr medeleg, 0xbad -write_read_csr mideleg, 0xbad -write_read_csr mie, 0xbad -write_read_csr mtvec, 0xbad -write_read_csr mcounteren, 0xbad +WRITE_READ_CSR mstatus, 0xbad +WRITE_READ_CSR misa, 0xbad +WRITE_READ_CSR medeleg, 0xbad +WRITE_READ_CSR mideleg, 0xbad +WRITE_READ_CSR mie, 0xbad +WRITE_READ_CSR mtvec, 0xbad +WRITE_READ_CSR mcounteren, 0xbad # Machine Trap Handling -write_read_csr mscratch, 0xbad -write_read_csr mepc, 0xbad -write_read_csr mcause, 0xbad -write_read_csr mtval, 0xbad -write_read_csr mip, 0xbad -# write_read_csr mtinst, 0xbad # *** these appear not to be implemented in the compile step of make??? -# write_read_csr mtval2, 0xbad +WRITE_READ_CSR mscratch, 0xbad +WRITE_READ_CSR mepc, 0xbad +WRITE_READ_CSR mcause, 0xbad +WRITE_READ_CSR mtval, 0xbad +WRITE_READ_CSR mip, 0xbad +# WRITE_READ_CSR mtinst, 0xbad # *** these appear not to be implemented in GCC +# WRITE_READ_CSR mtval2, 0xbad # Machine Configuration -# write_read_csr menvcfg, 0xbad # *** these appear not to be implemented in the compile step of make??? -# write_read_csr mseccgf, 0xbad +# WRITE_READ_CSR menvcfg, 0xbad # *** these appear not to be implemented in GCC +# WRITE_READ_CSR mseccgf, 0xbad # Machine Memory Protection -write_read_csr pmpcfg0, 0xbad -write_read_csr pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs +WRITE_READ_CSR pmpcfg0, 0xbad +WRITE_READ_CSR pmpcfg2, 0xbad # pmpcfg 1 and 3 dont exist in rv64. there's 1 pmpcfg reg per 8 pmpaddr regs -write_read_csr pmpaddr0, 0xbad -write_read_csr pmpaddr1, 0xbad -write_read_csr pmpaddr2, 0xbad -write_read_csr pmpaddr3, 0xbad -write_read_csr pmpaddr4, 0xbad -write_read_csr pmpaddr5, 0xbad -write_read_csr pmpaddr6, 0xbad -write_read_csr pmpaddr7, 0xbad -write_read_csr pmpaddr8, 0xbad -write_read_csr pmpaddr9, 0xbad -write_read_csr pmpaddr10, 0xbad -write_read_csr pmpaddr11, 0xbad -write_read_csr pmpaddr12, 0xbad -write_read_csr pmpaddr13, 0xbad -write_read_csr pmpaddr14, 0xbad -write_read_csr pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config +WRITE_READ_CSR pmpaddr0, 0xbad +WRITE_READ_CSR pmpaddr1, 0xbad +WRITE_READ_CSR pmpaddr2, 0xbad +WRITE_READ_CSR pmpaddr3, 0xbad +WRITE_READ_CSR pmpaddr4, 0xbad +WRITE_READ_CSR pmpaddr5, 0xbad +WRITE_READ_CSR pmpaddr6, 0xbad +WRITE_READ_CSR pmpaddr7, 0xbad +WRITE_READ_CSR pmpaddr8, 0xbad +WRITE_READ_CSR pmpaddr9, 0xbad +WRITE_READ_CSR pmpaddr10, 0xbad +WRITE_READ_CSR pmpaddr11, 0xbad +WRITE_READ_CSR pmpaddr12, 0xbad +WRITE_READ_CSR pmpaddr13, 0xbad +WRITE_READ_CSR pmpaddr14, 0xbad +WRITE_READ_CSR pmpaddr15, 0xbad # only pmpcfg0...15 are enabled in our config # Machine Counter/Timers -write_read_csr mcycle, 0xbad -write_read_csr minstret, 0xbad -write_read_csr mhpmcounter3, 0xbad -write_read_csr mhpmcounter4, 0xbad -write_read_csr mhpmcounter5, 0xbad -write_read_csr mhpmcounter6, 0xbad -write_read_csr mhpmcounter7, 0xbad -write_read_csr mhpmcounter8, 0xbad -write_read_csr mhpmcounter9, 0xbad -write_read_csr mhpmcounter10, 0xbad -write_read_csr mhpmcounter11, 0xbad -write_read_csr mhpmcounter12, 0xbad -write_read_csr mhpmcounter13, 0xbad -write_read_csr mhpmcounter14, 0xbad -write_read_csr mhpmcounter15, 0xbad -write_read_csr mhpmcounter16, 0xbad -write_read_csr mhpmcounter17, 0xbad -write_read_csr mhpmcounter18, 0xbad -write_read_csr mhpmcounter19, 0xbad -write_read_csr mhpmcounter20, 0xbad -write_read_csr mhpmcounter21, 0xbad -write_read_csr mhpmcounter22, 0xbad -write_read_csr mhpmcounter23, 0xbad -write_read_csr mhpmcounter24, 0xbad -write_read_csr mhpmcounter25, 0xbad -write_read_csr mhpmcounter26, 0xbad -write_read_csr mhpmcounter27, 0xbad -write_read_csr mhpmcounter28, 0xbad -write_read_csr mhpmcounter29, 0xbad -write_read_csr mhpmcounter30, 0xbad -write_read_csr mhpmcounter31, 0xbad +WRITE_READ_CSR mcycle, 0xbad +WRITE_READ_CSR minstret, 0xbad +WRITE_READ_CSR mhpmcounter3, 0xbad +WRITE_READ_CSR mhpmcounter4, 0xbad +WRITE_READ_CSR mhpmcounter5, 0xbad +WRITE_READ_CSR mhpmcounter6, 0xbad +WRITE_READ_CSR mhpmcounter7, 0xbad +WRITE_READ_CSR mhpmcounter8, 0xbad +WRITE_READ_CSR mhpmcounter9, 0xbad +WRITE_READ_CSR mhpmcounter10, 0xbad +WRITE_READ_CSR mhpmcounter11, 0xbad +WRITE_READ_CSR mhpmcounter12, 0xbad +WRITE_READ_CSR mhpmcounter13, 0xbad +WRITE_READ_CSR mhpmcounter14, 0xbad +WRITE_READ_CSR mhpmcounter15, 0xbad +WRITE_READ_CSR mhpmcounter16, 0xbad +WRITE_READ_CSR mhpmcounter17, 0xbad +WRITE_READ_CSR mhpmcounter18, 0xbad +WRITE_READ_CSR mhpmcounter19, 0xbad +WRITE_READ_CSR mhpmcounter20, 0xbad +WRITE_READ_CSR mhpmcounter21, 0xbad +WRITE_READ_CSR mhpmcounter22, 0xbad +WRITE_READ_CSR mhpmcounter23, 0xbad +WRITE_READ_CSR mhpmcounter24, 0xbad +WRITE_READ_CSR mhpmcounter25, 0xbad +WRITE_READ_CSR mhpmcounter26, 0xbad +WRITE_READ_CSR mhpmcounter27, 0xbad +WRITE_READ_CSR mhpmcounter28, 0xbad +WRITE_READ_CSR mhpmcounter29, 0xbad +WRITE_READ_CSR mhpmcounter30, 0xbad +WRITE_READ_CSR mhpmcounter31, 0xbad # Machine Counter Setup -write_read_csr mcountinhibit, 0xbad -write_read_csr mhpmevent3, 0xbad -write_read_csr mhpmevent4, 0xbad -write_read_csr mhpmevent5, 0xbad -write_read_csr mhpmevent6, 0xbad -write_read_csr mhpmevent7, 0xbad -write_read_csr mhpmevent8, 0xbad -write_read_csr mhpmevent9, 0xbad -write_read_csr mhpmevent10, 0xbad -write_read_csr mhpmevent11, 0xbad -write_read_csr mhpmevent12, 0xbad -write_read_csr mhpmevent13, 0xbad -write_read_csr mhpmevent14, 0xbad -write_read_csr mhpmevent15, 0xbad -write_read_csr mhpmevent16, 0xbad -write_read_csr mhpmevent17, 0xbad -write_read_csr mhpmevent18, 0xbad -write_read_csr mhpmevent19, 0xbad -write_read_csr mhpmevent20, 0xbad -write_read_csr mhpmevent21, 0xbad -write_read_csr mhpmevent22, 0xbad -write_read_csr mhpmevent23, 0xbad -write_read_csr mhpmevent24, 0xbad -write_read_csr mhpmevent25, 0xbad -write_read_csr mhpmevent26, 0xbad -write_read_csr mhpmevent27, 0xbad -write_read_csr mhpmevent28, 0xbad -write_read_csr mhpmevent29, 0xbad -write_read_csr mhpmevent30, 0xbad -write_read_csr mhpmevent31, 0xbad +WRITE_READ_CSR mcountinhibit, 0xbad +WRITE_READ_CSR mhpmevent3, 0xbad +WRITE_READ_CSR mhpmevent4, 0xbad +WRITE_READ_CSR mhpmevent5, 0xbad +WRITE_READ_CSR mhpmevent6, 0xbad +WRITE_READ_CSR mhpmevent7, 0xbad +WRITE_READ_CSR mhpmevent8, 0xbad +WRITE_READ_CSR mhpmevent9, 0xbad +WRITE_READ_CSR mhpmevent10, 0xbad +WRITE_READ_CSR mhpmevent11, 0xbad +WRITE_READ_CSR mhpmevent12, 0xbad +WRITE_READ_CSR mhpmevent13, 0xbad +WRITE_READ_CSR mhpmevent14, 0xbad +WRITE_READ_CSR mhpmevent15, 0xbad +WRITE_READ_CSR mhpmevent16, 0xbad +WRITE_READ_CSR mhpmevent17, 0xbad +WRITE_READ_CSR mhpmevent18, 0xbad +WRITE_READ_CSR mhpmevent19, 0xbad +WRITE_READ_CSR mhpmevent20, 0xbad +WRITE_READ_CSR mhpmevent21, 0xbad +WRITE_READ_CSR mhpmevent22, 0xbad +WRITE_READ_CSR mhpmevent23, 0xbad +WRITE_READ_CSR mhpmevent24, 0xbad +WRITE_READ_CSR mhpmevent25, 0xbad +WRITE_READ_CSR mhpmevent26, 0xbad +WRITE_READ_CSR mhpmevent27, 0xbad +WRITE_READ_CSR mhpmevent28, 0xbad +WRITE_READ_CSR mhpmevent29, 0xbad +WRITE_READ_CSR mhpmevent30, 0xbad +WRITE_READ_CSR mhpmevent31, 0xbad END_TESTS + +TEST_STACK_AND_DATA \ No newline at end of file diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MMU-SV39.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MMU-SV39.S index 39ca0a257..38f277606 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MMU-SV39.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MMU-SV39.S @@ -22,8 +22,18 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-64.h" -// Test library includes and handler for each type of test, a trap handler, imperas compliance instructions -// Ideally this should mean that a test can be written by simply adding .8byte statements as below. + +INIT_TESTS + +s_file_begin: +j test_loop_setup // begin test loop/table tests instead of executing inline code. + +INIT_TEST_TABLE + +TEST_STACK_AND_DATA + +.align 3 +test_cases: # --------------------------------------------------------------------------------------------- # Test Contents diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MMU-SV48.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MMU-SV48.S index 260a40fe9..f1625155d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MMU-SV48.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MMU-SV48.S @@ -22,8 +22,19 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-64.h" -// Test library includes and handler for each type of test, a trap handler, imperas compliance instructions -// Ideally this should mean that a test can be written by simply adding .8byte statements as below. + +INIT_TESTS + +s_file_begin: +j test_loop_setup // begin test loop/table tests instead of executing inline code. + +INIT_TEST_TABLE + +TEST_STACK_AND_DATA + +# These tests follow the testing plan in Chapter 12 of the riscv-wally textbook +.align 3 +test_cases: # --------------------------------------------------------------------------------------------- # Test Contents @@ -39,7 +50,6 @@ # # --------------------------------------------------------------------------------------------- -# These tests follow the testing plan in Chapter 12 of the riscv-wally textbook # =========== test 12.3.1.1 Page Table Translation =========== diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S index a4a50a3da..0e544fe36 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMA.S @@ -35,8 +35,19 @@ #define PLIC_RANGE 0x03FFFFFF #include "WALLY-TEST-LIB-64.h" -// Test library includes and handler for each type of test, a trap handler, imperas compliance instructions -// Ideally this should mean that a test can be written by simply adding .8byte statements as below. + +INIT_TESTS + +s_file_begin: +j test_loop_setup // begin test loop/table tests instead of executing inline code. + +INIT_TEST_TABLE + +TEST_STACK_AND_DATA + +# These tests follow the testing plan in Chapter 12 of the riscv-wally textbook +.align 3 +test_cases: # --------------------------------------------------------------------------------------------- # Test Contents diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMP.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMP.S index 5c894081c..157f0fe7f 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMP.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMP.S @@ -22,8 +22,19 @@ /////////////////////////////////////////// #include "WALLY-TEST-LIB-64.h" -// Test library includes and handler for each type of test, a trap handler, imperas compliance instructions -// Ideally this should mean that a test can be written by simply adding .8byte statements as below. + +INIT_TESTS + +s_file_begin: +j test_loop_setup // begin test loop/table tests instead of executing inline code. + +INIT_TEST_TABLE + +TEST_STACK_AND_DATA + +# These tests follow the testing plan in Chapter 12 of the riscv-wally textbook +.align 3 +test_cases: # --------------------------------------------------------------------------------------------- # Test Contents diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index 5e946618e..e8ad5de04 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -23,6 +23,9 @@ #include "model_test.h" #include "arch_test.h" + +.macro INIT_TESTS + RVTEST_ISA("RV64I") .section .text.init @@ -56,9 +59,9 @@ RVTEST_CODE_BEGIN li a1, 0 li a2, 0 // reset trap handler inputs to zero - // go to first test! - j test_setup - + // go to beginning of S file where we can decide between using the test data loop + // or using the macro inline code insertion + j s_file_begin // --------------------------------------------------------------------------------------------- // General traps Handler @@ -230,6 +233,9 @@ instrfault: ld x1, -8(sp) // load return address int x1 (the address AFTER the jal into faulting page) j trapreturn_finished // puts x1 into mepc, restores stack and returns to program (outside of faulting page) +illegalinstr: + j trapreturn // return to the code after recording the mcause + accessfault: // *** What do I have to do here? j trapreturn @@ -243,7 +249,7 @@ accessfault: trap_handler_vector_table: .8byte segfault // 0: instruction address misaligned .8byte instrfault // 1: instruction access fault - .8byte segfault // 2: illegal instruction + .8byte illegalinstr // 2: illegal instruction .8byte segfault // 3: breakpoint .8byte segfault // 4: load address misaligned .8byte accessfault // 5: load access fault @@ -265,6 +271,249 @@ trap_return_pagetype_table: .8byte 0x1E // 2: gigapage has 30 offset bits .8byte 0x27 // 3: terapage has 39 offset bits +.endm + +// Test Summary table! + +// Test Name : Description : Fault output value : Normal output values +// ---------------------:-------------------------------------------:-------------------------------------------:------------------------------------------------------ +// write64_test : Write 64 bits to address : 0x6, 0x7, or 0xf : None +// write32_test : Write 32 bits to address : 0x6, 0x7, or 0xf : None +// write16_test : Write 16 bits to address : 0x6, 0x7, or 0xf : None +// write08_test : Write 8 bits to address : 0x6, 0x7, or 0xf : None +// read64_test : Read 64 bits from address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex +// read32_test : Read 32 bits from address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex +// read16_test : Read 16 bits from address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex +// read08_test : Read 8 bits from address : 0x4, 0x5, or 0xd, then 0xbad : readvalue in hex +// executable_test : test executable on virtual page : 0x0, 0x1, or 0xc, then 0xbad : value of x7 modified by exectuion code (usually 0x111) +// terminate_test : terminate tests : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// goto_baremetal : satp.MODE = bare metal : None : None +// goto_sv39 : satp.MODE = sv39 : None : None +// goto_sv48 : satp.MODE = sv48 : None : None +// goto_m_mode : go to mahcine mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// goto_s_mode : go to supervisor mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// goto_u_mode : go to user mode : mcause value for fault : from M 0xb, from S 0x9, from U 0x8 +// write_read_csr : write to specified CSR : old CSR value, 0x2, depending on perms : value written to CSR +// csr_r_access : test read-only permissions on CSR : 0xbad : 0x2, then 0x11 + +// *** TESTS TO ADD: execute inline, read unknown value out, read CSR unknown value, just read CSR value + +.macro WRITE64 ADDR VAL + // attempt to write VAL to ADDR + // Success outputs: + // None + // Fault outputs: + // 0x6: misaligned address + // 0x7: access fault + // 0xf: page fault + li x29, \VAL + li x30, \ADDR + sd x29, 0(x30) +.endm + +.macro WRITE32 ADDR VAL + // all write tests have the same description/outputs as write64 + li x29, \VAL + li x30, \ADDR + sw x29, 0(x30) +.endm + +.macro WRITE16 ADDR VAL + // all write tests have the same description/outputs as write64 + li x29, \VAL + li x30, \ADDR + sh x29, 0(x30) +.endm + +.macro WRITE08 ADDR VAL + // all write tests have the same description/outputs as write64 + li x29, \VAL + li x30, \ADDR + sb x29, 0(x30) +.endm + +.macro READ64 ADDR + // Attempt read at ADDR. Write the value read out to the output *** Consider adding specific test for reading a non known value + // Success outputs: + // value read out from ADDR + // Fault outputs: + // One of the following followed by 0xBAD + // 0x4: misaligned address + // 0x5: access fault + // 0xD: page fault + li x7, 0xBAD // bad value that will be overwritten on good reads. + li x29, \ADDR + ld x7, 0(x29) + sd x7, 0(x6) + addi x6, x6, 8 + addi x16, x16, 8 +.endm + +.macro READ32 ADDR + // All reads have the same description/outputs as read64. + // They will store the sign extended value of what was read out at ADDR + li x7, 0xBAD // bad value that will be overwritten on good reads. + li x29, \ADDR + lw x7, 0(x29) + sd x7, 0(x6) + addi x6, x6, 8 + addi x16, x16, 8 +.endm + +.macro READ16 ADDR + // All reads have the same description/outputs as read64. + // They will store the sign extended value of what was read out at ADDR + li x7, 0xBAD // bad value that will be overwritten on good reads. + li x29, \ADDR + lh x7, 0(x29) + sd x7, 0(x6) + addi x6, x6, 8 + addi x16, x16, 8 +.endm + +.macro READ08 ADDR + // All reads have the same description/outputs as read64. + // They will store the sign extended value of what was read out at ADDR + li x7, 0xBAD // bad value that will be overwritten on good reads. + li x29, \ADDR + lb x7, 0(x29) + sd x7, 0(x6) + addi x6, x6, 8 + addi x16, x16, 8 +.endm + +// These goto_x_mode tests all involve invoking the trap handler, +// So their outputs are inevitably: +// 0x8: test called from U mode +// 0x9: test called from S mode +// 0xB: test called from M mode +// they generally do not fault or cause issues as long as these modes are enabled +// *** add functionality to check if modes are enabled before jumping? maybe cause a fault if not? + +.macro GOTO_M_MODE RETURN_VPN RETURN_PAGETYPE + li a0, 2 // determine trap handler behavior (go to machine mode) + li a1, \RETURN_VPN // return VPN + li a2, \RETURN_PAGETYPE // return page types + ecall // writes mcause to the output. + // now in S mode +.endm + +.macro GOTO_S_MODE RETURN_VPN RETURN_PAGETYPE + li a0, 3 // determine trap handler behavior (go to supervisor mode) + li a1, \RETURN_VPN // return VPN + li a2, \RETURN_PAGETYPE // return page types + ecall // writes mcause to the output. + // now in S mode +.endm + +.macro GOTO_U_MODE RETURN_VPN RETURN_PAGETYPE + li a0, 4 // determine trap handler behavior (go to user mode) + li a1, \RETURN_VPN // return VPN + li a2, \RETURN_PAGETYPE // return page types + ecall // writes mcause to the output. + // now in S mode +.endm + +// These tests change virtual memory settings, turning it on/off and changing between types. +// They don't have outputs as any error with turning on virtual memory should reveal itself in the tests *** Consider changing this policy? + +.macro GOTO_BAREMETAL + // Turn translation off + li x7, 0 // satp.MODE value for bare metal (0) + slli x7, x7, 60 + li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location + add x7, x7, x28 + csrw satp, x7 + sfence.vma x0, x0 // *** flushes global pte's as well +.endm + +.macro GOTO_SV39 + // Turn on sv39 virtual memory + li x7, 8 // satp.MODE value for Sv39 (8) + slli x7, x7, 60 + li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location + add x7, x7, x28 + csrw satp, x7 + sfence.vma x0, x0 // *** flushes global pte's as well +.endm + +.macro GOTO_SV48 + // Turn on sv48 virtual memory + li x7, 9 // satp.MODE value for Sv39 (8) + slli x7, x7, 60 + li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. *** add option for different pagetable location + add x7, x7, x28 + csrw satp, x7 + sfence.vma x0, x0 // *** flushes global pte's as well +.endm + +.macro WRITE_READ_CSR CSR VAL + // attempt to write CSR with VAL. Note: this also tests read access to CSR + // Success outputs: + // value read back out from CSR after writing + // Fault outputs: + // The previous CSR value before write attempt + // *** Most likely 0x2, the mcause for illegal instruction if we don't have write or read access + li x30, 0xbad // load bad value to be overwritten by csrr + li x29, \VAL + csrw \CSR\(), x29 + csrr x30, \CSR + sd x30, 0(x6) + addi x6, x6, 8 + addi x16, x16, 8 +.endm + +.macro CSR_R_ACCESS CSR + // verify that a csr is accessible to read but not to write + // Success outputs: + // 0x2, then + // 0x11 *** consider changing to something more meaningful + // Fault outputs: + // 0xBAD *** consider changing this one as well. in general, do we need the branching if it hould cause an illegal instruction fault? + csrr x29, \CSR + csrwi \CSR\(), 0xA // Attempt to write a 'random' value to the CSR + csrr x30, \CSR + bne x30, x29, 1f // 1f represents write_access + li x30, 0x11 // Write failed, confirming read only permissions. + j 2f // j r_access_end +1: // w_access (write succeeded, violating read-only) + li x30, 0xBAD +2: // r_access end + sd x30, 0(x6) + addi x6, x6, 8 + addi x16, x16, 8 +.endm + +.macro EXECUTE_AT_ADDRESS ADDR + // Execute the code already written to ADDR, returning the value in x7. + // *** Note: this test itself doesn't write the code to ADDR because it might be callled at a point where we dont have write access to ADDR + // Assumes the code modifies x7, usually to become 0x111. + // Sample code: 0x11100393 (li x7, 0x111), 0x00008067 (ret) + // Success outputs: + // modified value of x7. (0x111 if you use the sample code) + // Fault outputs: + // One of the following followed by 0xBAD + // 0x0: misaligned address + // 0x1: access fault + // 0xC: page fault + fence.i // forces caches and main memory to sync so execution code written to ADDR can run. + li x7, 0xBAD + li x28, \ADDR + jalr x28 // jump to executable test code + sd x7, 0(x6) + addi x6, x6, 8 + addi x16, x16, 8 +.endm + +.macro END_TESTS + // invokes one final ecall to return to machine mode then terminates this program, so the output is + // 0x8: termination called from U mode + // 0x9: termination called from S mode + // 0xB: termination called from M mode + j terminate_test + +.endm + // --------------------------------------------------------------------------------------------- // Test Handler // @@ -274,17 +523,18 @@ trap_return_pagetype_table: // Input parameters: // // x28: - // Address input for the test taking place (think address to read/write, new address to return to, etc...) + // Address input for the test taking place (think: address to read/write, new address to return to, etc...) // // x29: - // Value input for the test taking place (think value to write, any other extra info needed) + // Value input for the test taking place (think: value to write, any other extra info needed) // // x30: - // Test type input that determines which kind of test will take place. Encoding for this input is in the table/case statements below - // + // Label for the location of the test that's about to take place // ------------------------------------------------------------------------------------------------------------------------------------ -test_setup: +.macro INIT_TEST_TABLE // *** Consider renaming this test. to what??? + +test_loop_setup: la x5, test_cases test_loop: @@ -407,30 +657,15 @@ goto_u_mode: goto_baremetal: // Turn translation off - li x7, 0 // satp.MODE value for bare metal (0) - slli x7, x7, 60 - li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. - add x7, x7, x28 - csrw satp, x7 - sfence.vma x0, x0 // *** flushes global pte's as well + GOTO_BAREMETAL j test_loop // go to next test case goto_sv39: - li x7, 8 // satp.MODE value for Sv39 (8) - slli x7, x7, 60 - li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. - add x7, x7, x28 - csrw satp, x7 - sfence.vma x0, x0 // *** flushes global pte's as well + GOTO_SV39 j test_loop // go to next test case goto_sv48: - li x7, 9 // satp.MODE value for Sv48 - slli x7, x7, 60 - li x28, 0x8000D // Base Pagetable physical page number, satp.PPN field. - add x7, x7, x28 - csrw satp, x7 - sfence.vma x0, x0 // *** flushes global pte's as well + GOTO_SV48 j test_loop // go to next test case write_mxr_sum: @@ -447,15 +682,15 @@ write_mxr_sum: write_pmpcfg_0: // writes the value in x29 to the pmpcfg register specified in x28. // then writes the final value of pmpcfgX to the output. - li x7, 0x0 - bne x7, x28, write_pmpcfg_2 csrw pmpcfg0, x29 csrr x30, pmpcfg0 + j write_pmpcfg_end + write_pmpcfg_2: - li x7, 0x2 - bne x7, x28, write_pmpcfg_end csrw pmpcfg2, x29 csrr x30, pmpcfg2 // I would use csrrw but we need the value AFTER the csr has been written + j write_pmpcfg_end + write_pmpcfg_end: sd x30, 0(x6) addi x6, x6, 8 @@ -463,103 +698,88 @@ write_pmpcfg_end: j test_loop write_pmpaddr_0: + // write_read_csr pmpaddr0, x29 // writes the value in x29 to the pmpaddr register specified in x28. // then writes the final value of pmpaddrX to the output. - li x7, 0x0 - bne x7, x28, write_pmpaddr_1 csrw pmpaddr0, x29 csrr x30, pmpaddr0 j write_pmpaddr_end + write_pmpaddr_1: - li x7, 0x1 - bne x7, x28, write_pmpaddr_2 csrw pmpaddr1, x29 csrr x30, pmpaddr1 j write_pmpaddr_end + write_pmpaddr_2: - li x7, 0x2 - bne x7, x28, write_pmpaddr_3 csrw pmpaddr2, x29 csrr x30, pmpaddr2 j write_pmpaddr_end + write_pmpaddr_3: - li x7, 0x3 - bne x7, x28, write_pmpaddr_4 csrw pmpaddr3, x29 csrr x30, pmpaddr3 j write_pmpaddr_end + write_pmpaddr_4: - li x7, 0x4 - bne x7, x28, write_pmpaddr_5 csrw pmpaddr4, x29 csrr x30, pmpaddr4 j write_pmpaddr_end + write_pmpaddr_5: - li x7, 0x5 - bne x7, x28, write_pmpaddr_6 csrw pmpaddr5, x29 csrr x30, pmpaddr5 j write_pmpaddr_end + write_pmpaddr_6: - li x7, 0x6 - bne x7, x28, write_pmpaddr_7 csrw pmpaddr6, x29 csrr x30, pmpaddr6 j write_pmpaddr_end + write_pmpaddr_7: - li x7, 0x7 - bne x7, x28, write_pmpaddr_8 csrw pmpaddr7, x29 csrr x30, pmpaddr7 j write_pmpaddr_end + write_pmpaddr_8: - li x7, 0x8 - bne x7, x28, write_pmpaddr_9 csrw pmpaddr8, x29 csrr x30, pmpaddr8 j write_pmpaddr_end + write_pmpaddr_9: - li x7, 0x9 - bne x7, x28, write_pmpaddr_10 csrw pmpaddr9, x29 csrr x30, pmpaddr9 j write_pmpaddr_end + write_pmpaddr_10: - li x7, 0xA - bne x7, x28, write_pmpaddr_11 csrw pmpaddr10, x29 csrr x30, pmpaddr10 j write_pmpaddr_end + write_pmpaddr_11: - li x7, 0xB - bne x7, x28, write_pmpaddr_12 csrw pmpaddr11, x29 csrr x30, pmpaddr11 j write_pmpaddr_end + write_pmpaddr_12: - li x7, 0xC - bne x7, x28, write_pmpaddr_13 csrw pmpaddr12, x29 csrr x30, pmpaddr12 j write_pmpaddr_end + write_pmpaddr_13: - li x7, 0xD - bne x7, x28, write_pmpaddr_14 csrw pmpaddr13, x29 csrr x30, pmpaddr13 j write_pmpaddr_end + write_pmpaddr_14: - li x7, 0xE - bne x7, x28, write_pmpaddr_15 csrw pmpaddr14, x29 csrr x30, pmpaddr14 j write_pmpaddr_end + write_pmpaddr_15: - li x7, 0xF - bne x7, x28, write_pmpaddr_end csrw pmpaddr15, x29 csrr x30, pmpaddr15 j write_pmpaddr_end + write_pmpaddr_end: sd x30, 0(x6) addi x6, x6, 8 @@ -577,6 +797,10 @@ executable_test: addi x16, x16, 8 j test_loop +.endm + +// notably, terminate_test is not a part of the test table macro because it needs to be defined +// in any type of test, macro or test table, for the trap handler to work terminate_test: li a0, 2 // Trap handler behavior (go to machine mode) @@ -586,6 +810,8 @@ terminate_test: RVTEST_CODE_END RVMODEL_HALT +.macro TEST_STACK_AND_DATA + RVTEST_DATA_BEGIN .align 4 rvtest_data: @@ -619,6 +845,4 @@ gpr_save: #endif -.align 3 -test_cases: - +.endm diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S index 695c75222..1eeaed0bd 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-minfo-01.S @@ -21,17 +21,19 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -#include "WALLY-TEST-MACROS-64.h" +#include "WALLY-TEST-LIB-64.h" INIT_TESTS +s_file_begin: + // Test 5.2.3.1: testing Read-only access to Machine info CSRs +CSR_R_ACCESS mvendorid +CSR_R_ACCESS marchid +CSR_R_ACCESS mimpid +CSR_R_ACCESS mhartid +# CSR_R_ACCESS mconfigptr # Unimplemented in spike as of 31 Jan 22 -csr_r_access mvendorid -csr_r_access marchid -csr_r_access mimpid -csr_r_access mhartid -# csr_r_access mconfigptr # Unimplemented in spike as of 31 Jan 22 +END_TESTS - -END_TESTS \ No newline at end of file +TEST_STACK_AND_DATA \ No newline at end of file