mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
This commit is contained in:
commit
f966d98e56
@ -119,7 +119,7 @@ module csr #(parameter
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assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW);
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assign CSRSWriteM = CSRWriteM & (|PrivilegeModeW);
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assign CSRUWriteM = CSRWriteM;
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assign CSRUWriteM = CSRWriteM;
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csri csri(.clk, .reset, .StallW, .CSRMWriteM, .CSRSWriteM,
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csri csri(.clk, .reset, .FlushW, .StallW, .CSRMWriteM, .CSRSWriteM,
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.CSRAdrM, .ExtIntM, .TimerIntM, .SwIntM,
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.CSRAdrM, .ExtIntM, .TimerIntM, .SwIntM,
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.MIDELEG_REGW, .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .CSRWriteValM);
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.MIDELEG_REGW, .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .CSRWriteValM);
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csrsr csrsr(.clk, .reset, .StallW,
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csrsr csrsr(.clk, .reset, .StallW,
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@ -137,7 +137,7 @@ module csr #(parameter
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.CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
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.CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
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.MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
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.MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
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.MTIME_CLINT, .CSRCReadValM, .IllegalCSRCAccessM);
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.MTIME_CLINT, .CSRCReadValM, .IllegalCSRCAccessM);
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csrm csrm(.clk, .reset, .StallW,
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csrm csrm(.clk, .reset, .FlushW, .StallW,
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.CSRMWriteM, .MTrapM, .CSRAdrM,
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.CSRMWriteM, .MTrapM, .CSRAdrM,
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.NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW,
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.NextEPCM, .NextCauseM, .NextMtvalM, .MSTATUS_REGW,
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.CSRWriteValM, .CSRMReadValM, .MTVEC_REGW,
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.CSRWriteValM, .CSRMReadValM, .MTVEC_REGW,
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@ -145,7 +145,7 @@ module csr #(parameter
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.MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.MEDELEG_REGW, .MIDELEG_REGW,.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.MIP_REGW, .MIE_REGW, .WriteMSTATUSM,
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.MIP_REGW, .MIE_REGW, .WriteMSTATUSM,
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.IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM);
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.IllegalCSRMAccessM, .IllegalCSRMWriteReadonlyM);
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csrs csrs(.clk, .reset, .StallW,
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csrs csrs(.clk, .reset, .FlushW, .StallW,
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.CSRSWriteM, .STrapM, .CSRAdrM,
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.CSRSWriteM, .STrapM, .CSRAdrM,
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.NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW,
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.NextEPCM, .NextCauseM, .NextMtvalM, .SSTATUS_REGW,
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.STATUS_TVM, .CSRWriteValM, .PrivilegeModeW,
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.STATUS_TVM, .CSRWriteValM, .PrivilegeModeW,
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@ -153,12 +153,12 @@ module csr #(parameter
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.SCOUNTEREN_REGW, .SEDELEG_REGW, .SIDELEG_REGW,
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.SCOUNTEREN_REGW, .SEDELEG_REGW, .SIDELEG_REGW,
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.SATP_REGW, .SIP_REGW, .SIE_REGW,
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.SATP_REGW, .SIP_REGW, .SIE_REGW,
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.WriteSSTATUSM, .IllegalCSRSAccessM);
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.WriteSSTATUSM, .IllegalCSRSAccessM);
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csrn csrn(.clk, .reset, .StallW,
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csrn csrn(.clk, .reset, .FlushW, .StallW,
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.CSRNWriteM(CSRUWriteM), .UTrapM, .CSRAdrM,
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.CSRNWriteM(CSRUWriteM), .UTrapM, .CSRAdrM,
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.NextEPCM, .NextCauseM, .NextMtvalM, .USTATUS_REGW,
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.NextEPCM, .NextCauseM, .NextMtvalM, .USTATUS_REGW,
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.CSRWriteValM, .CSRNReadValM, .UEPC_REGW, .UTVEC_REGW,
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.CSRWriteValM, .CSRNReadValM, .UEPC_REGW, .UTVEC_REGW,
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.UIP_REGW, .UIE_REGW, .WriteUSTATUSM, .IllegalCSRNAccessM);
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.UIP_REGW, .UIE_REGW, .WriteUSTATUSM, .IllegalCSRNAccessM);
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csru csru(.clk, .reset, .StallW,
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csru csru(.clk, .reset, .FlushW, .StallW,
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.CSRUWriteM, .CSRAdrM, .CSRWriteValM, .CSRUReadValM,
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.CSRUWriteM, .CSRAdrM, .CSRWriteValM, .CSRUReadValM,
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.SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM,
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.SetFflagsM, .FRM_REGW, .WriteFRMM, .WriteFFLAGSM,
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.IllegalCSRUAccessM);
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.IllegalCSRUAccessM);
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@ -38,7 +38,7 @@ module csri #(parameter
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SIE = 12'h104,
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SIE = 12'h104,
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SIP = 12'h144) (
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SIP = 12'h144) (
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input logic clk, reset,
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input logic clk, reset,
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input logic StallW,
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input logic FlushW, StallW,
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input logic CSRMWriteM, CSRSWriteM,
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input logic CSRMWriteM, CSRSWriteM,
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input logic [11:0] CSRAdrM,
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input logic [11:0] CSRAdrM,
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input logic ExtIntM, TimerIntM, SwIntM,
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input logic ExtIntM, TimerIntM, SwIntM,
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@ -52,6 +52,9 @@ module csri #(parameter
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logic [11:0] MIP_WRITE_MASK, SIP_WRITE_MASK;
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logic [11:0] MIP_WRITE_MASK, SIP_WRITE_MASK;
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logic WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM;
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logic WriteMIPM, WriteMIEM, WriteSIPM, WriteSIEM;
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logic InstrValidNotFlushedM;
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assign InstrValidNotFlushedM = ~StallW & ~FlushW;
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// Determine which interrupts need to be set
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// Determine which interrupts need to be set
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// assumes no N-mode user interrupts
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// assumes no N-mode user interrupts
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@ -66,10 +69,10 @@ module csri #(parameter
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end
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end
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// Interrupt Write Enables
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// Interrupt Write Enables
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assign WriteMIPM = CSRMWriteM & (CSRAdrM == MIP) & ~StallW;
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assign WriteMIPM = CSRMWriteM & (CSRAdrM == MIP) & InstrValidNotFlushedM;
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assign WriteMIEM = CSRMWriteM & (CSRAdrM == MIE) & ~StallW;
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assign WriteMIEM = CSRMWriteM & (CSRAdrM == MIE) & InstrValidNotFlushedM;
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assign WriteSIPM = CSRSWriteM & (CSRAdrM == SIP) & ~StallW;
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assign WriteSIPM = CSRSWriteM & (CSRAdrM == SIP) & InstrValidNotFlushedM;
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assign WriteSIEM = CSRSWriteM & (CSRAdrM == SIE) & ~StallW;
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assign WriteSIEM = CSRSWriteM & (CSRAdrM == SIE) & InstrValidNotFlushedM;
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// Interrupt Pending and Enable Registers
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// Interrupt Pending and Enable Registers
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// MEIP, MTIP, MSIP are read-only
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// MEIP, MTIP, MSIP are read-only
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@ -70,7 +70,7 @@ module csrm #(parameter
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MIDELEG_MASK = {{(`XLEN-12){1'b0}}, 12'h222}
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MIDELEG_MASK = {{(`XLEN-12){1'b0}}, 12'h222}
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) (
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) (
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input logic clk, reset,
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input logic clk, reset,
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input logic StallW,
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input logic FlushW, StallW,
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input logic CSRMWriteM, MTrapM,
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input logic CSRMWriteM, MTrapM,
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input logic [11:0] CSRAdrM,
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input logic [11:0] CSRAdrM,
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input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW,
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input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW,
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@ -95,6 +95,9 @@ module csrm #(parameter
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logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM;
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logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM;
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logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM;
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logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM;
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logic InstrValidNotFlushedM;
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assign InstrValidNotFlushedM = ~StallW & ~FlushW;
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// There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop
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// There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop
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genvar i;
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genvar i;
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if (`PMP_ENTRIES > 0) begin:pmp
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if (`PMP_ENTRIES > 0) begin:pmp
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@ -110,13 +113,13 @@ module csrm #(parameter
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else
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else
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assign ADDRLocked[i] = PMPCFG_ARRAY_REGW[i][7] | (PMPCFG_ARRAY_REGW[i+1][7] & PMPCFG_ARRAY_REGW[i+1][4:3] == 2'b01);
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assign ADDRLocked[i] = PMPCFG_ARRAY_REGW[i][7] | (PMPCFG_ARRAY_REGW[i+1][7] & PMPCFG_ARRAY_REGW[i+1][4:3] == 2'b01);
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assign WritePMPADDRM[i] = (CSRMWriteM & (CSRAdrM == (PMPADDR0+i))) & ~StallW & ~ADDRLocked[i];
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assign WritePMPADDRM[i] = (CSRMWriteM & (CSRAdrM == (PMPADDR0+i))) & InstrValidNotFlushedM & ~ADDRLocked[i];
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flopenr #(`XLEN) PMPADDRreg(clk, reset, WritePMPADDRM[i], CSRWriteValM, PMPADDR_ARRAY_REGW[i]);
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flopenr #(`XLEN) PMPADDRreg(clk, reset, WritePMPADDRM[i], CSRWriteValM, PMPADDR_ARRAY_REGW[i]);
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if (`XLEN==64) begin
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if (`XLEN==64) begin
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assign WritePMPCFGM[i] = (CSRMWriteM & (CSRAdrM == (PMPCFG0+2*(i/8)))) & ~StallW & ~CFGLocked[i];
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assign WritePMPCFGM[i] = (CSRMWriteM & (CSRAdrM == (PMPCFG0+2*(i/8)))) & InstrValidNotFlushedM & ~CFGLocked[i];
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flopenr #(8) PMPCFGreg(clk, reset, WritePMPCFGM[i], CSRWriteValM[(i%8)*8+7:(i%8)*8], PMPCFG_ARRAY_REGW[i]);
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flopenr #(8) PMPCFGreg(clk, reset, WritePMPCFGM[i], CSRWriteValM[(i%8)*8+7:(i%8)*8], PMPCFG_ARRAY_REGW[i]);
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end else begin
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end else begin
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assign WritePMPCFGM[i] = (CSRMWriteM & (CSRAdrM == (PMPCFG0+i/4))) & ~StallW & ~CFGLocked[i];
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assign WritePMPCFGM[i] = (CSRMWriteM & (CSRAdrM == (PMPCFG0+i/4))) & InstrValidNotFlushedM & ~CFGLocked[i];
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flopenr #(8) PMPCFGreg(clk, reset, WritePMPCFGM[i], CSRWriteValM[(i%4)*8+7:(i%4)*8], PMPCFG_ARRAY_REGW[i]);
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flopenr #(8) PMPCFGreg(clk, reset, WritePMPCFGM[i], CSRWriteValM[(i%4)*8+7:(i%4)*8], PMPCFG_ARRAY_REGW[i]);
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end
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end
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end
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end
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@ -131,16 +134,16 @@ module csrm #(parameter
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assign MHARTID_REGW = 0;
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assign MHARTID_REGW = 0;
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// Write machine Mode CSRs
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// Write machine Mode CSRs
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assign WriteMSTATUSM = CSRMWriteM & (CSRAdrM == MSTATUS) & ~StallW;
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assign WriteMSTATUSM = CSRMWriteM & (CSRAdrM == MSTATUS) & InstrValidNotFlushedM;
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assign WriteMTVECM = CSRMWriteM & (CSRAdrM == MTVEC) & ~StallW;
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assign WriteMTVECM = CSRMWriteM & (CSRAdrM == MTVEC) & InstrValidNotFlushedM;
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assign WriteMEDELEGM = CSRMWriteM & (CSRAdrM == MEDELEG) & ~StallW;
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assign WriteMEDELEGM = CSRMWriteM & (CSRAdrM == MEDELEG) & InstrValidNotFlushedM;
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assign WriteMIDELEGM = CSRMWriteM & (CSRAdrM == MIDELEG) & ~StallW;
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assign WriteMIDELEGM = CSRMWriteM & (CSRAdrM == MIDELEG) & InstrValidNotFlushedM;
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assign WriteMSCRATCHM = CSRMWriteM & (CSRAdrM == MSCRATCH) & ~StallW;
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assign WriteMSCRATCHM = CSRMWriteM & (CSRAdrM == MSCRATCH) & InstrValidNotFlushedM;
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assign WriteMEPCM = MTrapM | (CSRMWriteM & (CSRAdrM == MEPC)) & ~StallW;
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assign WriteMEPCM = MTrapM | (CSRMWriteM & (CSRAdrM == MEPC)) & InstrValidNotFlushedM;
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assign WriteMCAUSEM = MTrapM | (CSRMWriteM & (CSRAdrM == MCAUSE)) & ~StallW;
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assign WriteMCAUSEM = MTrapM | (CSRMWriteM & (CSRAdrM == MCAUSE)) & InstrValidNotFlushedM;
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assign WriteMTVALM = MTrapM | (CSRMWriteM & (CSRAdrM == MTVAL)) & ~StallW;
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assign WriteMTVALM = MTrapM | (CSRMWriteM & (CSRAdrM == MTVAL)) & InstrValidNotFlushedM;
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assign WriteMCOUNTERENM = CSRMWriteM & (CSRAdrM == MCOUNTEREN) & ~StallW;
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assign WriteMCOUNTERENM = CSRMWriteM & (CSRAdrM == MCOUNTEREN) & InstrValidNotFlushedM;
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assign WriteMCOUNTINHIBITM = CSRMWriteM & (CSRAdrM == MCOUNTINHIBIT) & ~StallW;
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assign WriteMCOUNTINHIBITM = CSRMWriteM & (CSRAdrM == MCOUNTINHIBIT) & InstrValidNotFlushedM;
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assign IllegalCSRMWriteReadonlyM = CSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID);
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assign IllegalCSRMWriteReadonlyM = CSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID);
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@ -42,7 +42,7 @@ module csrn #(parameter
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UTVAL = 12'h043,
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UTVAL = 12'h043,
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UIP = 12'h044) (
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UIP = 12'h044) (
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input logic clk, reset,
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input logic clk, reset,
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input logic StallW,
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input logic FlushW, StallW,
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input logic CSRNWriteM, UTrapM,
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input logic CSRNWriteM, UTrapM,
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input logic [11:0] CSRAdrM,
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input logic [11:0] CSRAdrM,
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input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, USTATUS_REGW,
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input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, USTATUS_REGW,
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@ -61,12 +61,15 @@ module csrn #(parameter
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logic [`XLEN-1:0] UEDELEG_REGW, UIDELEG_REGW;
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logic [`XLEN-1:0] UEDELEG_REGW, UIDELEG_REGW;
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logic [`XLEN-1:0] USCRATCH_REGW, UCAUSE_REGW, UTVAL_REGW;
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logic [`XLEN-1:0] USCRATCH_REGW, UCAUSE_REGW, UTVAL_REGW;
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logic InstrValidNotFlushedM;
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assign InstrValidNotFlushedM = ~StallW & ~FlushW;
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// Write enables
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// Write enables
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assign WriteUSTATUSM = CSRNWriteM & (CSRAdrM == USTATUS) & ~StallW;
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assign WriteUSTATUSM = CSRNWriteM & (CSRAdrM == USTATUS) & InstrValidNotFlushedM;
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assign WriteUTVECM = CSRNWriteM & (CSRAdrM == UTVEC) & ~StallW;
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assign WriteUTVECM = CSRNWriteM & (CSRAdrM == UTVEC) & InstrValidNotFlushedM;
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assign WriteUEPCM = UTrapM | (CSRNWriteM & (CSRAdrM == UEPC)) & ~StallW;
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assign WriteUEPCM = UTrapM | (CSRNWriteM & (CSRAdrM == UEPC)) & InstrValidNotFlushedM;
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assign WriteUCAUSEM = UTrapM | (CSRNWriteM & (CSRAdrM == UCAUSE)) & ~StallW;
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assign WriteUCAUSEM = UTrapM | (CSRNWriteM & (CSRAdrM == UCAUSE)) & InstrValidNotFlushedM;
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assign WriteUTVALM = UTrapM | (CSRNWriteM & (CSRAdrM == UTVAL)) & ~StallW;
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assign WriteUTVALM = UTrapM | (CSRNWriteM & (CSRAdrM == UTVAL)) & InstrValidNotFlushedM;
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// CSRs
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// CSRs
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flopenl #(`XLEN) UTVECreg(clk, reset, WriteUTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, `RESET_VECTOR, UTVEC_REGW);
|
flopenl #(`XLEN) UTVECreg(clk, reset, WriteUTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, `RESET_VECTOR, UTVEC_REGW);
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@ -52,7 +52,7 @@ module csrs #(parameter
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|||||||
|
|
||||||
) (
|
) (
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input logic clk, reset,
|
input logic clk, reset,
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input logic StallW,
|
input logic FlushW, StallW,
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input logic CSRSWriteM, STrapM,
|
input logic CSRSWriteM, STrapM,
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input logic [11:0] CSRAdrM,
|
input logic [11:0] CSRAdrM,
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input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW,
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input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW,
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@ -81,14 +81,17 @@ module csrs #(parameter
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logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW;
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logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW;
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(* mark_debug = "true" *) logic [`XLEN-1:0] SCAUSE_REGW;
|
(* mark_debug = "true" *) logic [`XLEN-1:0] SCAUSE_REGW;
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|
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assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS) & ~StallW;
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logic InstrValidNotFlushedM;
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assign WriteSTVECM = CSRSWriteM & (CSRAdrM == STVEC) & ~StallW;
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assign InstrValidNotFlushedM = ~StallW & ~FlushW;
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assign WriteSSCRATCHM = CSRSWriteM & (CSRAdrM == SSCRATCH) & ~StallW;
|
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assign WriteSEPCM = STrapM | (CSRSWriteM & (CSRAdrM == SEPC)) & ~StallW;
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assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS) & InstrValidNotFlushedM;
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assign WriteSCAUSEM = STrapM | (CSRSWriteM & (CSRAdrM == SCAUSE)) & ~StallW;
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assign WriteSTVECM = CSRSWriteM & (CSRAdrM == STVEC) & InstrValidNotFlushedM;
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assign WriteSTVALM = STrapM | (CSRSWriteM & (CSRAdrM == STVAL)) & ~StallW;
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assign WriteSSCRATCHM = CSRSWriteM & (CSRAdrM == SSCRATCH) & InstrValidNotFlushedM;
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assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == `M_MODE | ~STATUS_TVM) & ~StallW;
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assign WriteSEPCM = STrapM | (CSRSWriteM & (CSRAdrM == SEPC)) & InstrValidNotFlushedM;
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assign WriteSCOUNTERENM = CSRSWriteM & (CSRAdrM == SCOUNTEREN) & ~StallW;
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assign WriteSCAUSEM = STrapM | (CSRSWriteM & (CSRAdrM == SCAUSE)) & InstrValidNotFlushedM;
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assign WriteSTVALM = STrapM | (CSRSWriteM & (CSRAdrM == STVAL)) & InstrValidNotFlushedM;
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assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == `M_MODE | ~STATUS_TVM) & InstrValidNotFlushedM;
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assign WriteSCOUNTERENM = CSRSWriteM & (CSRAdrM == SCOUNTEREN) & InstrValidNotFlushedM;
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// CSRs
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// CSRs
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flopenr #(`XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW); //busybear: change reset to 0
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flopenr #(`XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW); //busybear: change reset to 0
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@ -37,7 +37,7 @@ module csru #(parameter
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FRM = 12'h002,
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FRM = 12'h002,
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||||||
FCSR = 12'h003) (
|
FCSR = 12'h003) (
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input logic clk, reset,
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input logic clk, reset,
|
||||||
input logic StallW,
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input logic FlushW, StallW,
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input logic CSRUWriteM,
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input logic CSRUWriteM,
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input logic [11:0] CSRAdrM,
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input logic [11:0] CSRAdrM,
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||||||
input logic [`XLEN-1:0] CSRWriteValM,
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input logic [`XLEN-1:0] CSRWriteValM,
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@ -54,10 +54,13 @@ module csru #(parameter
|
|||||||
logic [2:0] NextFRMM;
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logic [2:0] NextFRMM;
|
||||||
logic [4:0] NextFFLAGSM;
|
logic [4:0] NextFFLAGSM;
|
||||||
|
|
||||||
|
logic InstrValidNotFlushedM;
|
||||||
|
assign InstrValidNotFlushedM = ~StallW & ~FlushW;
|
||||||
|
|
||||||
// Write enables
|
// Write enables
|
||||||
//assign WriteFCSRM = CSRUWriteM & (CSRAdrM == FCSR) & ~StallW;
|
//assign WriteFCSRM = CSRUWriteM & (CSRAdrM == FCSR) & InstrValidNotFlushedM;
|
||||||
assign WriteFRMM = (CSRUWriteM & (CSRAdrM == FRM | CSRAdrM == FCSR)) & ~StallW;
|
assign WriteFRMM = (CSRUWriteM & (CSRAdrM == FRM | CSRAdrM == FCSR)) & InstrValidNotFlushedM;
|
||||||
assign WriteFFLAGSM = (CSRUWriteM & (CSRAdrM == FFLAGS | CSRAdrM == FCSR)) & ~StallW;
|
assign WriteFFLAGSM = (CSRUWriteM & (CSRAdrM == FFLAGS | CSRAdrM == FCSR)) & InstrValidNotFlushedM;
|
||||||
|
|
||||||
// Write Values
|
// Write Values
|
||||||
assign NextFRMM = (CSRAdrM == FCSR) ? CSRWriteValM[7:5] : CSRWriteValM[2:0];
|
assign NextFRMM = (CSRAdrM == FCSR) ? CSRWriteValM[7:5] : CSRWriteValM[2:0];
|
||||||
|
Loading…
Reference in New Issue
Block a user