diff --git a/src/uncore/spi_apb.sv b/src/uncore/spi_apb.sv
index eb4f95047..9bcf8be05 100644
--- a/src/uncore/spi_apb.sv
+++ b/src/uncore/spi_apb.sv
@@ -271,7 +271,6 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
 
     always_ff @(posedge PCLK)
         if (~PRESETn) TransmitFIFOWriteIncrement <= 1'b0;
-        // else TransmitFIFOWriteIncrement <= (Memwrite & (Entry == 8'h48) & ~TransmitFIFOWriteFull & TransmitInactive);
         else TransmitFIFOWriteIncrement <= (Memwrite & (Entry == SPI_TXDATA) & ~TransmitFIFOWriteFull);
 
     always_ff @(posedge PCLK)
@@ -380,7 +379,6 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
 
     assign DelayMode = SckMode[0] ? (state == DELAY_1) : (state == ACTIVE_1 & ReceiveShiftFull);
     assign ChipSelectInternal = (state == CS_INACTIVE | state == INTER_CS | DelayMode & ~|(Delay0[15:8])) ? ChipSelectDef : ~ChipSelectDef;
-    // assign preSPICLK = (state == ACTIVE_0) ? ~SckMode[1] : SckMode[1];
     assign Active = (state == ACTIVE_0 | state == ACTIVE_1);
     assign SampleEdge = SckMode[0] ? (state == ACTIVE_1) : (state == ACTIVE_0);
     assign ZeroDelayHoldMode = ((ChipSelectMode == 2'b10) & (~|(Delay1[7:4])));
@@ -388,24 +386,21 @@ module spi_apb import cvw::*; #(parameter cvw_t P) (
     assign Active0 = (state == ACTIVE_0);
 
   // Signal tracks which edge of sck to shift data
-  // Jacob: We need to confirm that this represents the actual polarity and phase options for sampling.
-  //        The first option now samples on the leading edge and shifts on the falling edge like it's supposed to.
-  //        We need to confirm the validity of the other options. 
     always_comb
         case(SckMode[1:0])
             2'b00: ShiftEdge = SPICLK & SCLKenable;
-            2'b01: ShiftEdge = (~SPICLK & (|(FrameCount) | (CS_SCKCount >= (({Delay0[7:0], 1'b0}) + ImplicitDelay1))) & SCLKenable & (FrameCount != Format[4:1]) & ~TransmitInactive); // Probably wrong
-            2'b10: ShiftEdge = ~SPICLK & SCLKenable; // Probably wrong
-            2'b11: ShiftEdge = (SPICLK & (|(FrameCount) | (CS_SCKCount >= (({Delay0[7:0], 1'b0}) + ImplicitDelay1))) & SCLKenable & (FrameCount != Format[4:1]) & ~TransmitInactive); // Probably wrong
+            2'b01: ShiftEdge = (~SPICLK & (|(FrameCount) | (CS_SCKCount >= (({Delay0[7:0], 1'b0}) + ImplicitDelay1))) & SCLKenable & (FrameCount != Format[4:1]) & ~TransmitInactive);
+            2'b10: ShiftEdge = ~SPICLK & SCLKenable; 
+            2'b11: ShiftEdge = (SPICLK & (|(FrameCount) | (CS_SCKCount >= (({Delay0[7:0], 1'b0}) + ImplicitDelay1))) & SCLKenable & (FrameCount != Format[4:1]) & ~TransmitInactive);
             default: ShiftEdge = SPICLK & SCLKenable;
         endcase
 
     // Transmit shift register
     assign TransmitDataEndian = Format[0] ? {TransmitFIFOReadData[0], TransmitFIFOReadData[1], TransmitFIFOReadData[2], TransmitFIFOReadData[3], TransmitFIFOReadData[4], TransmitFIFOReadData[5], TransmitFIFOReadData[6], TransmitFIFOReadData[7]} : TransmitFIFOReadData[7:0];
     always_ff @(posedge PCLK)
-        if(~PRESETn)                        TransmitShiftReg <= 8'b0; // Temporarily changing to 1s 
+        if(~PRESETn)                        TransmitShiftReg <= 8'b0;
         else if (TransmitShiftRegLoad)      TransmitShiftReg <= TransmitDataEndian;
-        else if (ShiftEdge & Active)        TransmitShiftReg <= {TransmitShiftReg[6:0], TransmitShiftReg[0]}; // Temporarily changing to 1s
+        else if (ShiftEdge & Active)        TransmitShiftReg <= {TransmitShiftReg[6:0], TransmitShiftReg[0]};
     
     assign SPIOut = TransmitShiftReg[7];