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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
fctrl coverage at 100% after removing redundancies from conditional statements
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Sydeny
parent
10be07857c
commit
f9566299a0
@ -93,24 +93,24 @@ module fctrl (
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// FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr_FCvtInt
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// FRegWrite_FWriteInt_FResSel_PostProcSel_FOpCtrl_FDivStart_IllegalFPUInstr_FCvtInt
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always_comb
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always_comb
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if (STATUS_FS == 2'b00) // FPU instructions are illegal when FPU is disabled
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if (STATUS_FS == 2'b00) // FPU instructions are illegal when FPU is disabled
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ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0;
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ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0;
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else if (OpD != 7'b0000111 & OpD != 7'b0100111 & ~SupportedFmt)
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else if (OpD != 7'b0000111 & OpD != 7'b0100111 & ~SupportedFmt)
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ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // for anything other than loads and stores, check for supported format
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ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0; // for anything other than loads and stores, check for supported format
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else begin
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else begin
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ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // default: non-implemented instruction
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ControlsD = `FCTRLW'b0_0_00_00_000_0_1_0; // default: non-implemented instruction
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/* verilator lint_off CASEINCOMPLETE */ // default value above has priority so no other default needed
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/* verilator lint_off CASEINCOMPLETE */ // default value above has priority so no other default needed
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case(OpD)
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case(OpD)
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7'b0000111: case(Funct3D)
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7'b0000111: case(Funct3D)
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3'b010: ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flw
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3'b010: ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flw
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3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // fld
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3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // fld
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3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flq
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3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flq
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3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_xx_0xx_0_0_0; // flh
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3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b1_0_10_00_0xx_0_0_0; // flh
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endcase
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endcase
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7'b0100111: case(Funct3D)
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7'b0100111: case(Funct3D)
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3'b010: ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsw
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3'b010: ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsw
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3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsd
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3'b011: if (`D_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsd
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3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsq
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3'b100: if (`Q_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsq
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3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_xx_0xx_0_0_0; // fsh
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3'b001: if (`ZFH_SUPPORTED) ControlsD = `FCTRLW'b0_0_10_00_0xx_0_0_0; // fsh
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endcase
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endcase
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7'b1000011: ControlsD = `FCTRLW'b1_0_01_10_000_0_0_0; // fmadd
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7'b1000011: ControlsD = `FCTRLW'b1_0_01_10_000_0_0_0; // fmadd
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7'b1000111: ControlsD = `FCTRLW'b1_0_01_10_001_0_0_0; // fmsub
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7'b1000111: ControlsD = `FCTRLW'b1_0_01_10_001_0_0_0; // fmsub
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@ -123,25 +123,25 @@ module fctrl (
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7'b00011??: ControlsD = `FCTRLW'b1_0_01_01_xx0_1_0_0; // fdiv
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7'b00011??: ControlsD = `FCTRLW'b1_0_01_01_xx0_1_0_0; // fdiv
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7'b01011??: if (Rs2D == 5'b0000) ControlsD = `FCTRLW'b1_0_01_01_xx1_1_0_0; // fsqrt
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7'b01011??: if (Rs2D == 5'b0000) ControlsD = `FCTRLW'b1_0_01_01_xx1_1_0_0; // fsqrt
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7'b00100??: case(Funct3D)
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7'b00100??: case(Funct3D)
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3'b000: ControlsD = `FCTRLW'b1_0_00_xx_000_0_0_0; // fsgnj
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3'b000: ControlsD = `FCTRLW'b1_0_00_00_000_0_0_0; // fsgnj
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3'b001: ControlsD = `FCTRLW'b1_0_00_xx_001_0_0_0; // fsgnjn
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3'b001: ControlsD = `FCTRLW'b1_0_00_00_001_0_0_0; // fsgnjn
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3'b010: ControlsD = `FCTRLW'b1_0_00_xx_010_0_0_0; // fsgnjx
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3'b010: ControlsD = `FCTRLW'b1_0_00_00_010_0_0_0; // fsgnjx
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endcase
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endcase
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7'b00101??: case(Funct3D)
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7'b00101??: case(Funct3D)
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3'b000: ControlsD = `FCTRLW'b1_0_00_xx_110_0_0_0; // fmin
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3'b000: ControlsD = `FCTRLW'b1_0_00_00_110_0_0_0; // fmin
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3'b001: ControlsD = `FCTRLW'b1_0_00_xx_101_0_0_0; // fmax
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3'b001: ControlsD = `FCTRLW'b1_0_00_00_101_0_0_0; // fmax
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endcase
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endcase
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7'b10100??: case(Funct3D)
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7'b10100??: case(Funct3D)
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3'b010: ControlsD = `FCTRLW'b0_1_00_xx_010_0_0_0; // feq
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3'b010: ControlsD = `FCTRLW'b0_1_00_00_010_0_0_0; // feq
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3'b001: ControlsD = `FCTRLW'b0_1_00_xx_001_0_0_0; // flt
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3'b001: ControlsD = `FCTRLW'b0_1_00_00_001_0_0_0; // flt
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3'b000: ControlsD = `FCTRLW'b0_1_00_xx_011_0_0_0; // fle
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3'b000: ControlsD = `FCTRLW'b0_1_00_00_011_0_0_0; // fle
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endcase
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endcase
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7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000)
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7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000)
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ControlsD = `FCTRLW'b0_1_10_xx_000_0_0_0; // fclass
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ControlsD = `FCTRLW'b0_1_10_00_000_0_0_0; // fclass
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else if (Funct3D == 3'b000 & Rs2D == 5'b00000)
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else if (Funct3D == 3'b000 & Rs2D == 5'b00000)
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ControlsD = `FCTRLW'b0_1_11_xx_000_0_0_0; // fmv.x.w / fmv.x.d to int register
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ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0; // fmv.x.w / fmv.x.d to int register
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7'b111100?: if (Funct3D == 3'b000 & Rs2D == 5'b00000)
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7'b111100?: if (Funct3D == 3'b000 & Rs2D == 5'b00000)
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ControlsD = `FCTRLW'b1_0_00_xx_011_0_0_0; // fmv.w.x / fmv.d.x to fp reg
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ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0; // fmv.w.x / fmv.d.x to fp reg
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7'b0100000: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b00)
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7'b0100000: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b00)
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ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.(d/q/h)
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ControlsD = `FCTRLW'b1_0_01_00_000_0_0_0; // fcvt.s.(d/q/h)
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7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01)
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7'b0100001: if (Rs2D[4:2] == 3'b000 & SupportedFmt2 & Rs2D[1:0] != 2'b01)
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@ -242,16 +242,17 @@ module fctrl (
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// X - all except int->fp, store, load, mv int->fp
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// X - all except int->fp, store, load, mv int->fp
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assign XEnD = ~(((FResSelD==2'b10)&~FWriteIntD)| // load/store
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assign XEnD = ~(((FResSelD==2'b10)&~FWriteIntD)| // load/store
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((FResSelD==2'b11)&FRegWriteD)| // mv int to float
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// ((FResSelD==2'b11)&FRegWriteD)| // mv int to float
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((FResSelD==2'b01)&(PostProcSelD==2'b00)&OpCtrlD[2])); // cvt int to float
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((FResSelD==2'b01)&(PostProcSelD==2'b00)&OpCtrlD[2])); // cvt int to float
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// Y - all except cvt, mv, load, class, sqrt
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// Y - all except cvt, mv, load, class, sqrt
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assign YEnD = ~(((FResSelD==2'b10)&(FWriteIntD|FRegWriteD))| // load or class
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assign YEnD = ~(((FResSelD==2'b10)&(FWriteIntD|FRegWriteD))| // load or class // mv both ways
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(FResSelD==2'b11)| // mv both ways
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((FResSelD==2'b01)&((PostProcSelD==2'b00)|((PostProcSelD==2'b01)&OpCtrlD[0])))); // cvt both or sqrt
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((FResSelD==2'b01)&((PostProcSelD==2'b00)|((PostProcSelD==2'b01)&OpCtrlD[0])))); // cvt both or sqrt
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// Removed (FResSelD==2'b11)| removed to avoid redundancy
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// Z - fma ops only
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// Z - fma ops only
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assign ZEnD = (PostProcSelD==2'b10)&(FResSelD==2'b01)&(~OpCtrlD[2]|OpCtrlD[1]); // fma, add, sub
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assign ZEnD = (PostProcSelD==2'b10)&(~OpCtrlD[2]|OpCtrlD[1]); // fma, add, sub // Removed &(FResSelD==2'b01) because it' redundant, Changed all the xx PostProcSelD to 00 to avoid unnecessary contention errors.
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// Final Res Sel:
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// Final Res Sel:
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