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https://github.com/openhwgroup/cvw
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fixed bug where opctrl not changing when running several intdivrem tests
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@ -127,7 +127,7 @@ module testbenchfp;
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logic FMAop; // Is this a FMA operation?
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logic sqrtop; // Is this a SQRT operation?
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flop #(3) funct3reg(.clk, .d(Funct3E), .q(Funct3M));
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flopen #(3) funct3reg(.clk, .en(IFDivStartE), .d(Funct3E), .q(Funct3M));
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///////////////////////////////////////////////////////////////////////////////////////////////
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// ||||||||| |||||||| ||||||| ||||||||| ||||||| |||||||| |||
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@ -687,57 +687,56 @@ module testbenchfp;
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Unit = {Unit, `DIVUNIT};
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Fmt = {Fmt, 2'b10};
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end
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if (TEST === "intrem") begin // if unified div sqrt is being tested
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if (TEST === "intrem" | TEST === "intdivrem" ) begin // if unified div sqrt is being tested
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Tests = {Tests, intrem};
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OpCtrl = {OpCtrl, `INTREM_OPCTRL};
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WriteInt = {WriteInt, 1'b0};
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Unit = {Unit, `INTDIVUNIT};
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Fmt = {Fmt, 2'b10};
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end
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if (TEST === "intdiv") begin // if unified div sqrt is being tested
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if (TEST === "intdiv" | TEST ==="intdivrem") begin // if unified div sqrt is being tested
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Tests = {Tests, intdiv};
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OpCtrl = {OpCtrl, `INTDIV_OPCTRL};
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WriteInt = {WriteInt, 1'b0};
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Unit = {Unit, `INTDIVUNIT};
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Fmt = {Fmt, 2'b10};
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end
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if (TEST === "intremu") begin // if unified div sqrt is being tested
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if (TEST === "intremu"| TEST ==="intdivrem") begin // if unified div sqrt is being tested
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Tests = {Tests, intremu};
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OpCtrl = {OpCtrl, `INTREMU_OPCTRL};
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WriteInt = {WriteInt, 1'b0};
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Unit = {Unit, `INTDIVUNIT};
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Fmt = {Fmt, 2'b10};
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end
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if (TEST === "intdivu") begin // if unified div sqrt is being tested
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if (TEST === "intdivu"| TEST ==="intdivrem") begin // if unified div sqrt is being tested
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Tests = {Tests, intdivu};
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OpCtrl = {OpCtrl, `INTDIVU_OPCTRL};
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WriteInt = {WriteInt, 1'b0};
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Unit = {Unit, `INTDIVUNIT};
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Fmt = {Fmt, 2'b10};
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end
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if (TEST === "intremw") begin // if unified div sqrt is being tested
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if (TEST === "intremw"| TEST ==="intdivrem") begin // if unified div sqrt is being tested
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Tests = {Tests, intremw};
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OpCtrl = {OpCtrl, `INTREMW_OPCTRL};
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WriteInt = {WriteInt, 1'b0};
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Unit = {Unit, `INTDIVUNIT};
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Fmt = {Fmt, 2'b10};
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end
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//TODO:DIVW, DIVUW
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if (TEST === "intremuw") begin // if unified div sqrt is being tested
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if (TEST === "intremuw"| TEST ==="intdivrem") begin // if unified div sqrt is being tested
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Tests = {Tests, intremuw};
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OpCtrl = {OpCtrl, `INTREMUW_OPCTRL};
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WriteInt = {WriteInt, 1'b0};
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Unit = {Unit, `INTDIVUNIT};
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Fmt = {Fmt, 2'b10};
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end
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if (TEST === "intdivw") begin // if unified div sqrt is being tested
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if (TEST === "intdivw"| TEST ==="intdivrem") begin // if unified div sqrt is being tested
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Tests = {Tests, intdivw};
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OpCtrl = {OpCtrl, `INTDIVW_OPCTRL};
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WriteInt = {WriteInt, 1'b0};
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Unit = {Unit, `INTDIVUNIT};
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Fmt = {Fmt, 2'b10};
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end
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if (TEST === "intdivuw") begin // if unified div sqrt is being tested
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if (TEST === "intdivuw"| TEST ==="intdivrem") begin // if unified div sqrt is being tested
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Tests = {Tests, intdivuw};
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OpCtrl = {OpCtrl, `INTDIVUW_OPCTRL};
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WriteInt = {WriteInt, 1'b0};
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@ -745,8 +744,6 @@ module testbenchfp;
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Fmt = {Fmt, 2'b10};
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end
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end
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// check if nothing is being tested
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@ -865,7 +862,7 @@ module testbenchfp;
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.Funct3E(Funct3E), .IntDivE(1'b0), .FIntDivResultM(FIntDivResultM),
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.FDivDoneE(FDivDoneE), .IFDivStartE(IFDivStartE));
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end
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if (TEST === "divremsqrt" | TEST === "divremsqrttest" | TEST === "customdiv" | TEST === "intdiv" | TEST === "intrem" | TEST === "intdivu" | TEST ==="intremu" | TEST ==="intremw" | TEST ==="intremuw" | TEST ==="intdivw" | TEST ==="intdivuw") begin: divremsqrt
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if (TEST === "divremsqrt" | TEST === "divremsqrttest" | TEST === "customdiv" | TEST === "intdiv" | TEST === "intrem" | TEST === "intdivu" | TEST ==="intremu" | TEST ==="intremw" | TEST ==="intremuw" | TEST ==="intdivw" | TEST ==="intdivuw" | TEST ==="intdivrem") begin: divremsqrt
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drsu #(P) drsu(.clk, .reset, .XsE(Xs), .YsE(Ys), .FmtE(ModFmt), .XmE(Xm), .YmE(Ym),
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.XeE(Xe), .YeE(Ye), .SqrtE(OpCtrlVal===`SQRT_OPCTRL&UnitVal===`DIVUNIT), .SqrtM(OpCtrlVal===`SQRT_OPCTRL&UnitVal===`DIVUNIT),
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.XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero),
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@ -1156,7 +1153,7 @@ module testbenchfp;
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// set the vector index back to 0
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VectorNum = 0;
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// incemet the operation if all the rounding modes have been tested
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if (FrmNum === 4) OpCtrlNum += 1;
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if (FrmNum === 4 | TEST === "intdivrem") OpCtrlNum += 1;
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// increment the rounding mode or loop back to rne
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if (FrmNum < 4) FrmNum += 1;
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else FrmNum = 0;
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