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	Added and extra header and changed the comments to be accurate in ram1p1rwbe.sv
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				| @ -1,5 +1,35 @@ | |||||||
|  | ####################################################################### | ||||||
|  | # splitfile.sh | ||||||
|  | # | ||||||
|  | # Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024 | ||||||
|  | # | ||||||
|  | # Purpose: Used to split boot.mem into two sections for FPGA | ||||||
|  | # | ||||||
|  | #  | ||||||
|  | # | ||||||
|  | # A component of the Wally configurable RISC-V project. | ||||||
|  | #  | ||||||
|  | # Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University | ||||||
|  | # | ||||||
|  | # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 | ||||||
|  | # | ||||||
|  | # Licensed under the Solderpad Hardware License v 2.1 (the | ||||||
|  | # “License”); you may not use this file except in compliance with the | ||||||
|  | # License, or, at your option, the Apache License version 2.0. You | ||||||
|  | # may obtain a copy of the License at | ||||||
|  | # | ||||||
|  | # https://solderpad.org/licenses/SHL-2.1/ | ||||||
|  | # | ||||||
|  | # Unless required by applicable law or agreed to in writing, any work | ||||||
|  | # distributed under the License is distributed on an “AS IS” BASIS, | ||||||
|  | # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or | ||||||
|  | # implied. See the License for the specific language governing | ||||||
|  | # permissions and limitations under the License. | ||||||
|  | ###################################################################### | ||||||
|  | 
 | ||||||
|  | 
 | ||||||
| # Acquired from here. | # Acquired from here. | ||||||
| # https://stackoverflow.com/questions/3066948/how-to-file-split-at-a-line-number | # https:##stackoverflow.com#questions#3066948#how-to-file-split-at-a-line-number | ||||||
| file_name=$1 | file_name=$1 | ||||||
| 
 | 
 | ||||||
| # set first K lines: | # set first K lines: | ||||||
|  | |||||||
| @ -99,11 +99,11 @@ module ram1p1rwbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=64, WIDTH=44, PRE | |||||||
|           `ifdef VERILATOR |           `ifdef VERILATOR | ||||||
|             // because Verilator doesn't automatically accept $WALLY from shell
 |             // because Verilator doesn't automatically accept $WALLY from shell
 | ||||||
|             string       WALLY_DIR = getenvval("WALLY");  |             string       WALLY_DIR = getenvval("WALLY");  | ||||||
|             $readmemh({WALLY_DIR,"/fpga/src/data.mem"}, RAM, 0);  // load boot ROM for FPGA
 |             $readmemh({WALLY_DIR,"/fpga/src/data.mem"}, RAM, 0);  // load boot RAM for FPGA
 | ||||||
|           `else |           `else | ||||||
|             $readmemh({"$WALLY/fpga/src/data.mem"}, RAM, 0);  // load boot ROM for FPGA
 |             $readmemh({"$WALLY/fpga/src/data.mem"}, RAM, 0);  // load boot RAM for FPGA
 | ||||||
|           `endif |           `endif | ||||||
|         end else begin // put something in the ROM so it is not optimized away
 |         end else begin // put something in the RAM so it is not optimized away
 | ||||||
|         RAM[0] = 'h00002197; |         RAM[0] = 'h00002197; | ||||||
|         end |         end | ||||||
|       end |       end | ||||||
|  | |||||||
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