From b654e47d7057900e85b29adf4c2f031bc8b1caf1 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Wed, 15 Nov 2023 08:45:25 -0600 Subject: [PATCH 01/14] Add wrapper passing automatically for individual designs vs. Wally --- synthDC/Makefile | 40 ++++++++++++++++++++++++++++++++++------ synthDC/ppa/ppaSynth.py | 4 ++-- 2 files changed, 36 insertions(+), 8 deletions(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index d43a36b50..3e344e8d2 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -1,7 +1,28 @@ -# -# Makefile for synthesis -# Shreya Sanghai (ssanghai@hmc.edu) 2/28/2022 -# Madeleine Masser-Frye (mmasserfrye@hmc.edu) 1/27/2023 +##################### +# Makefile +# +# Written: ssanghai@hmc.edu, mmasserfrye@hmc.edu, james.stine@okstate.edu 15 November 2023 +# +# Purpose: Makefile to be used for synthesis using DC +# +# A component of the Wally configurable RISC-V project. +# +# Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https:#solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +################################################ + NAME := synth # defaults export DESIGN ?= wallypipelinedcore @@ -21,11 +42,18 @@ export MAXOPT ?= 0 export DRIVE ?= FLOP export USESRAM ?= 0 export WIDTH ?= 32 +export WRAPPER ?= 1 +export SAIFPOWER ?= 0 time := $(shell date +%F-%H-%M) hash := $(shell git rev-parse --short HEAD) -export OUTPUTDIR := runs/$(DESIGN)_$(WIDTH)_$(CONFIG)_$(TECH)_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash) -export SAIFPOWER ?= 0 +# This is done to create different naming conventions to help the PPA python +# TODO: cleanup later to utilize better parsing/lexing +ifeq ($(WRAPPER), 0) + export OUTPUTDIR := runs/$(DESIGN)_$(WIDTH)_$(CONFIG)_$(TECH)_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash) +else + export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash) +endif OLDCONFIGDIR ?= ${WALLY}/config export CONFIGDIR ?= $(OUTPUTDIR)/config diff --git a/synthDC/ppa/ppaSynth.py b/synthDC/ppa/ppaSynth.py index 30fe1254f..0c4744c26 100755 --- a/synthDC/ppa/ppaSynth.py +++ b/synthDC/ppa/ppaSynth.py @@ -11,7 +11,7 @@ from multiprocessing import Pool from ppaAnalyze import synthsfromcsv def runCommand(module, width, tech, freq): - command = "make synth DESIGN={} WIDTH={} TECH={} DRIVE=INV FREQ={} MAXOPT=1 MAXCORES=1".format(module, width, tech, freq) + command = "make synth DESIGN={} WIDTH={} TECH={} DRIVE=INV FREQ={} MAXOPT=1 MAXCORES=1 WRAPPER=0".format(module, width, tech, freq) subprocess.call(command, shell=True) def deleteRedundant(synthsToRun): @@ -95,4 +95,4 @@ if __name__ == '__main__': pool.starmap(runCommand, synthsToRun) pool.close() -pool.join() \ No newline at end of file +pool.join() From 43ff20d2f2af3781d93ce3f8708191625bda08ed Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Wed, 15 Nov 2023 08:48:07 -0600 Subject: [PATCH 02/14] missing synth.tcl added for use with wrapper --- synthDC/scripts/synth.tcl | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index cd4d6ff27..668b1c215 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -1,7 +1,27 @@ +##################### +# synth.tcl # -# Synthesis Synopsys Flow -# james.stine@okstate.edu 27 Sep 2015 +# Written: james.stine@okstate.edu 15 November 2023 # +# Purpose: Baseline DC Tcl file +# +# A component of the Wally configurable RISC-V project. +# +# Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +# +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +# +# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +# except in compliance with the License, or, at your option, the Apache License version 2.0. You +# may obtain a copy of the License at +# +# https:#solderpad.org/licenses/SHL-2.1/ +# +# Unless required by applicable law or agreed to in writing, any work distributed under the +# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +# either express or implied. See the License for the specific language governing permissions +# and limitations under the License. +################################################ # start run clock set t1 [clock seconds] @@ -26,6 +46,7 @@ set saifpower $::env(SAIFPOWER) set maxopt $::env(MAXOPT) set drive $::env(DRIVE) set width $::env(WIDTH) +set wrapper $::env(WRAPPER) eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/} @@ -33,7 +54,6 @@ eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/} # Check if a wrapper is needed and create it (to pass parameters when cvw_t parameters are used) -set wrapper 0 if {[catch {eval exec grep "cvw_t" $outputDir/hdl/$::env(DESIGN).sv}] == 0} { echo "Creating wrapper" set wrapper 1 @@ -440,7 +460,7 @@ set filename [format "%s%s" $outputDir "/reports/cell.rep"] #redirect $filename { report_cell [get_cells -hier *] } # not too useful set filename [format "%s%s" $outputDir "/reports/power.rep"] -redirect $filename { report_power -hierarchy -levels 1 } +redirect $filename { report_power -analysis_effort high -hierarchy -levels 1 } set filename [format "%s%s" $outputDir "/reports/constraint.rep"] redirect $filename { report_constraint } From b289e5275ae38a728693ee14162af1545444d9a8 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 15 Nov 2023 09:48:13 -0800 Subject: [PATCH 03/14] changed to head of riscv-arch-test --- addins/riscv-arch-test | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index 4eea0a0f0..9f9bdd62d 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit 4eea0a0f0e21f2613a114e45a5ad738e721c4044 +Subproject commit 9f9bdd62d3e37fcd8ad1b1a39d71694ccf1d74f3 From b2184c6ac065f975c105e3b518d1586ab79511dc Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Wed, 15 Nov 2023 22:35:33 -0600 Subject: [PATCH 04/14] Removed the size opt tests from the branch predictor analysis. --- bin/parseHPMC.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py index 8e274a200..86326457a 100755 --- a/bin/parseHPMC.py +++ b/bin/parseHPMC.py @@ -180,9 +180,11 @@ def ExtractSelectedData(benchmarkFirstList): benchmarkDict = { } for benchmark in benchmarkFirstList: (name, opt, config, prefixName, entries, dataDict) = benchmark - if opt == 'bd_speedopt_speed': NewName = name+'Sp' - elif opt == 'bd_sizeopt_speed': NewName = name+'Sz' - else: NewName = name + # use this code to distinguish speed opt and size opt. + #if opt == 'bd_speedopt_speed': NewName = name+'Sp' + #elif opt == 'bd_sizeopt_speed': NewName = name+'Sz' + #else: NewName = name + NewName = name #print(NewName) #NewName = name+'_'+opt if NewName in benchmarkDict: From 556fe16b0afc403116da3b415652a784b1fe2329 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 17 Nov 2023 11:21:25 -0600 Subject: [PATCH 05/14] Fixed testbench so it runs with BPRED_LOGGER but not PrintHPMCounters. --- testbench/testbench.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 186144839..070a6cad7 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -37,7 +37,7 @@ module testbench; parameter DEBUG=0; parameter TEST="none"; parameter PrintHPMCounters=0; - parameter BPRED_LOGGER=0; + parameter BPRED_LOGGER=1; parameter I_CACHE_ADDR_LOGGER=0; parameter D_CACHE_ADDR_LOGGER=0; @@ -434,7 +434,7 @@ module testbench; loggers (clk, reset, DCacheFlushStart, DCacheFlushDone, memfilename); // track the current function or global label - if (DEBUG == 1 | (PrintHPMCounters & P.ZICNTR_SUPPORTED)) begin : FunctionName + if (DEBUG == 1 | ((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED)) begin : FunctionName FunctionName #(P) FunctionName(.reset(reset_ext | TestBenchReset), .clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile)); end From 889d685524f51912794b29f8956756e7bfdcd3e3 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 17 Nov 2023 12:05:22 -0600 Subject: [PATCH 06/14] Fixed bugs in paraseHPMC.py --- bin/parseHPMC.py | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py index 86326457a..a11296b3e 100755 --- a/bin/parseHPMC.py +++ b/bin/parseHPMC.py @@ -244,7 +244,7 @@ def ReportAsText(benchmarkDict): def Inversion(lst): return [x if not args.invert else 100 - x for x in lst] -def BarGraph(seriesDict, xlabelList, BenchPerRow, FileName): +def BarGraph(seriesDict, xlabelList, BenchPerRow, FileName, IncludeLegend): index = 0 NumberInGroup = len(seriesDict) # Figure out width of bars. NumberInGroup bars + want 2 bar space @@ -262,8 +262,8 @@ def BarGraph(seriesDict, xlabelList, BenchPerRow, FileName): plt.xticks([r + barWidth*(NumberInGroup/2-0.5) for r in range(0, BenchPerRow)], xlabelList) plt.xlabel('Benchmark') if(not args.invert): plt.ylabel('Misprediction Rate (%)') - else: plt.ylabel('Prediction Accuracy (%)') - plt.legend(loc='upper left', ncol=2) + else: plt.ylabel('Prediction Accuracy (%)') + if(IncludeLegend): plt.legend(loc='upper right', ncol=2) plt.savefig(FileName) def SelectPartition(xlabelListBig, seriesDictBig, group, BenchPerRow): @@ -352,13 +352,13 @@ def ReportAsGraph(benchmarkDict, bar): # index += 1 if(not args.summary): - size = len(benchmarkDict) - sizeSqrt = math.sqrt(size) - isSquare = math.isclose(sizeSqrt, round(sizeSqrt)) - numCol = math.floor(sizeSqrt) + NumBenchmarks = len(benchmarkDict) + NumBenchmarksSqrt = math.sqrt(NumBenchmarks) + isSquare = math.isclose(NumBenchmarksSqrt, round(NumBenchmarksSqrt)) + numCol = math.floor(NumBenchmarksSqrt) numRow = numCol + (0 if isSquare else 1) index = 1 - BenchPerRow = 7 + BenchPerRow = 5 xlabelList = [] seriesDict = {} @@ -387,11 +387,11 @@ def ReportAsGraph(benchmarkDict, bar): #The next step will be to split the benchmarkDict into length BenchPerRow pieces then repeat the following code # on each piece. - for row in range(0, math.ceil(39 / BenchPerRow)): + for row in range(0, math.ceil(NumBenchmarks / BenchPerRow)): (xlabelListTrunk, seriesDictTrunk) = SelectPartition(xlabelListBig, seriesDictBig, row, BenchPerRow) FileName = 'barSegment%d.png' % row groupLen = len(xlabelListTrunk) - BarGraph(seriesDictTrunk, xlabelListTrunk, groupLen, FileName) + BarGraph(seriesDictTrunk, xlabelListTrunk, groupLen, FileName, (row == 0)) # main From 8ddfdd44f65a7c845380f77364f330fb0821bd73 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 17 Nov 2023 15:21:58 -0600 Subject: [PATCH 07/14] bpred-sim only simulates 12 jobs at once. --- sim/bpred-sim.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/sim/bpred-sim.py b/sim/bpred-sim.py index 530fab70c..60af41298 100755 --- a/sim/bpred-sim.py +++ b/sim/bpred-sim.py @@ -102,7 +102,8 @@ def main(): if(args.direction): # for direction predictor size sweep bpdSize = [6, 8, 10, 12, 14, 16] - bpdType = ['twobit', 'gshare', 'global', 'gshare_basic', 'global_basic', 'local_basic'] + #bpdType = ['twobit', 'gshare', 'global', 'gshare_basic', 'global_basic', 'local_basic'] + bpdType = ['twobit', 'gshare'] for CurrBPType in bpdType: for CurrBPSize in bpdSize: name = CurrBPType+str(CurrBPSize) From d026b0e2bf30879826027ee337986072f79a0f2c Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 17 Nov 2023 13:27:57 -0800 Subject: [PATCH 08/14] Initial version of embench_arch_sweep.py --- benchmarks/embench/embench_arch_sweep.py | 86 ++++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100755 benchmarks/embench/embench_arch_sweep.py diff --git a/benchmarks/embench/embench_arch_sweep.py b/benchmarks/embench/embench_arch_sweep.py new file mode 100755 index 000000000..ad629320a --- /dev/null +++ b/benchmarks/embench/embench_arch_sweep.py @@ -0,0 +1,86 @@ +#!/usr/bin/python3 +# embench_arch_sweep.py +# David_Harris@hmc.edu 16 November 2023 +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 + +# Run embench on a variety of architectures and collate results + +import os +from datetime import datetime +import re +import collections + +archs = ["rv32i_zicsr", "rv32im_zicsr", "rv32imc_zicsr", "rv32imc_zba_zbb_zbc_zbs_zicsr", "rv32imafdc_zba_zbb_zbc_zbs_zicsr"] + +def calcgeomean(d, arch): + progs = ["aha-mont64", "crc32", "cubic", "edn", "huffbench", "matmult-int", "minver", "nbody", "nettle-aes", "nettle-sha256", "nsichneu", "picojpeg", "qrduino", "sglib-combined", "slre", "st", "statemate", "ud", "wikisort"] + result = 1.0 + for p in progs: + #val = d[arch][p] + val = d[arch].get(p, 1.0) + result = result *float(val) + result = pow(result, (1.0/float(len(progs)))) + return result + +def tabulate_arch_sweep(directory): + for case in ["wallySizeOpt_size", "wallySpeedOpt_speed"]: + d = collections.defaultdict(dict) + for arch in archs: + file = case+"_"+arch+".json" + file_path = os.path.join(directory, file) + lines = [] + try: + f = open(file_path, "r") + lines = f.readlines() + except: + f.close() + #print(file_path+" does not exist") + for line in lines: + #print("File: "+file+" Line: "+line) + #p = re.compile('".*" : .*,') + p = r'"([^"]*)" : ([^,\n]+)' + match = re.search(p, line) + if match: + prog = match.group(1) + result = match.group(2); + d[arch][prog] = result; + #print(match.group(1)+" " + match.group(2)) + f.close() + for arch in [""] + archs: + print (arch, end="\t") + print("") + for prog in d[archs[0]]: + print(prog, end="\t") + for arch in archs: + entry = d[arch].get(prog, "n/a"); + print (entry, end="\t") + print("") + print("New geo mean", end="\t") + for arch in archs: + geomean = calcgeomean(d, arch) + print(geomean, end="\t") + print("") + +def run_arch_sweep(): + # make a folder whose name depends on the date + # Get current date + current_date = datetime.now() + # Format date as a string in the format YYYYMMDD + date_string = current_date.strftime('%Y%m%d_%H%M%S') + dir = "run_"+date_string + # Create a directory with the date string as its name + os.mkdir(dir) + + # make a directory with the current date as its name + + # sweep the runs and save the results in the run directory + for arch in archs: + os.system("make clean") + os.system("make run ARCH="+arch) + for res in ["SizeOpt_size", "SizeOpt_speed", "SpeedOpt_size", "SpeedOpt_speed"]: + os.system("mv -f wally"+res+".json "+dir+"/wally"+res+"_"+arch+".json") + return dir + +#directory = run_arch_sweep() +directory = "run_20231116_071322" +tabulate_arch_sweep(directory) \ No newline at end of file From 6c8341f59eca8f711dd30f6eaeaa949adea6d55b Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Fri, 17 Nov 2023 16:25:35 -0600 Subject: [PATCH 09/14] Revert removal of WRAPPER option that is not prudent --- synthDC/Makefile | 40 ++++++--------------------------------- synthDC/ppa/ppaSynth.py | 4 ++-- synthDC/scripts/synth.tcl | 28 ++++----------------------- 3 files changed, 12 insertions(+), 60 deletions(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index 3e344e8d2..470ec8f47 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -1,28 +1,7 @@ -##################### -# Makefile -# -# Written: ssanghai@hmc.edu, mmasserfrye@hmc.edu, james.stine@okstate.edu 15 November 2023 -# -# Purpose: Makefile to be used for synthesis using DC -# -# A component of the Wally configurable RISC-V project. -# -# Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https:#solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -################################################ - +# +# Makefile for synthesis +# Shreya Sanghai (ssanghai@hmc.edu) 2/28/2022 +# Madeleine Masser-Frye (mmasserfrye@hmc.edu) 1/27/2023 NAME := synth # defaults export DESIGN ?= wallypipelinedcore @@ -42,18 +21,11 @@ export MAXOPT ?= 0 export DRIVE ?= FLOP export USESRAM ?= 0 export WIDTH ?= 32 -export WRAPPER ?= 1 -export SAIFPOWER ?= 0 time := $(shell date +%F-%H-%M) hash := $(shell git rev-parse --short HEAD) -# This is done to create different naming conventions to help the PPA python -# TODO: cleanup later to utilize better parsing/lexing -ifeq ($(WRAPPER), 0) - export OUTPUTDIR := runs/$(DESIGN)_$(WIDTH)_$(CONFIG)_$(TECH)_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash) -else - export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash) -endif +export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(TECH)_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash) +export SAIFPOWER ?= 0 OLDCONFIGDIR ?= ${WALLY}/config export CONFIGDIR ?= $(OUTPUTDIR)/config diff --git a/synthDC/ppa/ppaSynth.py b/synthDC/ppa/ppaSynth.py index 0c4744c26..30fe1254f 100755 --- a/synthDC/ppa/ppaSynth.py +++ b/synthDC/ppa/ppaSynth.py @@ -11,7 +11,7 @@ from multiprocessing import Pool from ppaAnalyze import synthsfromcsv def runCommand(module, width, tech, freq): - command = "make synth DESIGN={} WIDTH={} TECH={} DRIVE=INV FREQ={} MAXOPT=1 MAXCORES=1 WRAPPER=0".format(module, width, tech, freq) + command = "make synth DESIGN={} WIDTH={} TECH={} DRIVE=INV FREQ={} MAXOPT=1 MAXCORES=1".format(module, width, tech, freq) subprocess.call(command, shell=True) def deleteRedundant(synthsToRun): @@ -95,4 +95,4 @@ if __name__ == '__main__': pool.starmap(runCommand, synthsToRun) pool.close() -pool.join() +pool.join() \ No newline at end of file diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 668b1c215..cd4d6ff27 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -1,27 +1,7 @@ -##################### -# synth.tcl # -# Written: james.stine@okstate.edu 15 November 2023 +# Synthesis Synopsys Flow +# james.stine@okstate.edu 27 Sep 2015 # -# Purpose: Baseline DC Tcl file -# -# A component of the Wally configurable RISC-V project. -# -# Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -# -# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -# -# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -# except in compliance with the License, or, at your option, the Apache License version 2.0. You -# may obtain a copy of the License at -# -# https:#solderpad.org/licenses/SHL-2.1/ -# -# Unless required by applicable law or agreed to in writing, any work distributed under the -# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -# either express or implied. See the License for the specific language governing permissions -# and limitations under the License. -################################################ # start run clock set t1 [clock seconds] @@ -46,7 +26,6 @@ set saifpower $::env(SAIFPOWER) set maxopt $::env(MAXOPT) set drive $::env(DRIVE) set width $::env(WIDTH) -set wrapper $::env(WRAPPER) eval file copy -force [glob ${cfg}/*.vh] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/cvw.sv] {$outputDir/hdl/} @@ -54,6 +33,7 @@ eval file copy -force [glob ${hdl_src}/*/*.sv] {$outputDir/hdl/} eval file copy -force [glob ${hdl_src}/*/*/*.sv] {$outputDir/hdl/} # Check if a wrapper is needed and create it (to pass parameters when cvw_t parameters are used) +set wrapper 0 if {[catch {eval exec grep "cvw_t" $outputDir/hdl/$::env(DESIGN).sv}] == 0} { echo "Creating wrapper" set wrapper 1 @@ -460,7 +440,7 @@ set filename [format "%s%s" $outputDir "/reports/cell.rep"] #redirect $filename { report_cell [get_cells -hier *] } # not too useful set filename [format "%s%s" $outputDir "/reports/power.rep"] -redirect $filename { report_power -analysis_effort high -hierarchy -levels 1 } +redirect $filename { report_power -hierarchy -levels 1 } set filename [format "%s%s" $outputDir "/reports/constraint.rep"] redirect $filename { report_constraint } From 19e1a09681e2328f872af748afb230736c870070 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 17 Nov 2023 15:10:57 -0800 Subject: [PATCH 10/14] Got Wally sweep running again --- synthDC/Makefile | 2 +- synthDC/ppa/ppaSynth.py | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index 470ec8f47..2183cab83 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -24,7 +24,7 @@ export WIDTH ?= 32 time := $(shell date +%F-%H-%M) hash := $(shell git rev-parse --short HEAD) -export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(TECH)_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash) +export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash) export SAIFPOWER ?= 0 OLDCONFIGDIR ?= ${WALLY}/config diff --git a/synthDC/ppa/ppaSynth.py b/synthDC/ppa/ppaSynth.py index 30fe1254f..315fa554a 100755 --- a/synthDC/ppa/ppaSynth.py +++ b/synthDC/ppa/ppaSynth.py @@ -85,7 +85,8 @@ if __name__ == '__main__': ##### Run a sweep for multiple modules/widths based on best delay found in existing syntheses modules = ['adder'] - widths = [8, 16, 32, 64, 128] +# widths = [8, 16, 32, 64, 128] + widths = [32] tech = 'sky130' synthsToRun = freqModuleSweep(widths, modules, tech) From c8f9c4672aefaa87870fffad0780372923c82d09 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 17 Nov 2023 15:11:52 -0800 Subject: [PATCH 11/14] Embench Makefile to sweep experiments across configs --- benchmarks/embench/Makefile | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/benchmarks/embench/Makefile b/benchmarks/embench/Makefile index 97c7660c5..d7a18b7e2 100644 --- a/benchmarks/embench/Makefile +++ b/benchmarks/embench/Makefile @@ -3,6 +3,7 @@ # Compile Embench for Wally embench_dir = ../../addins/embench-iot +ARCH=rv32imac_zicsr all: build run: build size sim @@ -15,7 +16,7 @@ buildsize: build_speedopt_size build_sizeopt_size # uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed and size build_speedopt_speed: - $(embench_dir)/build_all.py --builddir=bd_speedopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-O2 -nostartfiles" + $(embench_dir)/build_all.py --builddir=bd_speedopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S -march=$(ARCH)" --cflags="-O2 -nostartfiles -march=$(ARCH)" # remove files not used in embench1.0 When changing to 2.0, restore these files #rm -rf $(embench_dir)/bd_speedopt_speed/src/md5sum #rm -rf $(embench_dir)/bd_speedopt_speed/src/tarfind @@ -23,7 +24,7 @@ build_speedopt_speed: find $(embench_dir)/bd_speedopt_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done build_sizeopt_speed: - $(embench_dir)/build_all.py --builddir=bd_sizeopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-Os -nostartfiles" + $(embench_dir)/build_all.py --builddir=bd_sizeopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S -march=$(ARCH)" --cflags="-Os -nostartfiles -march=$(ARCH)" # remove files not used in embench1.0 When changing to 2.0, restore these files #rm -rf $(embench_dir)/bd_sizeopt_speed/src/md5sum #rm -rf $(embench_dir)/bd_sizeopt_speed/src/tarfind @@ -32,10 +33,10 @@ build_sizeopt_speed: # uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed and size build_speedopt_size: - $(embench_dir)/build_all.py --builddir=bd_speedopt_size --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostdlib -nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/dummy.S" --cflags="-O2 -msave-restore" --dummy-libs="libgcc libm libc crt0" + $(embench_dir)/build_all.py --builddir=bd_speedopt_size --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostdlib -nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/dummy.S -march=$(ARCH)" --cflags="-O2 -msave-restore -march=$(ARCH)" --dummy-libs="libgcc libm libc crt0" build_sizeopt_size: - $(embench_dir)/build_all.py --builddir=bd_sizeopt_size --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostdlib -nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/dummy.S" --cflags="-Os -msave-restore" --dummy-libs="libgcc libm libc crt0" + $(embench_dir)/build_all.py --builddir=bd_sizeopt_size --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostdlib -nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/dummy.S -march=$(ARCH)" --cflags="-Os -msave-restore -march=$(ARCH)" --dummy-libs="libgcc libm libc crt0" # builds dependencies, then launches modelsim and finally runs python wrapper script to present results sim: modelsim_build_memfile modelsim_run speed From aceb620dcece24e96d86d0233140a9156bd9b4a4 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 17 Nov 2023 17:02:32 -0800 Subject: [PATCH 12/14] Ignore benchmark results --- .gitignore | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index bd7e800df..3990c3823 100644 --- a/.gitignore +++ b/.gitignore @@ -10,7 +10,7 @@ __pycache__/ addins/riscv-arch-test/Makefile.include addins/riscv-tests/target addins/TestFloat-3e/build/Linux-x86_64-GCC/* -benchmarks/embench/wally*.json + #vsim work files to ignore transcript @@ -175,3 +175,6 @@ tests/fp/combined_IF_vectors/IF_vectors/*.tv sim/bp-results/*.log sim/branch*.log /tests/custom/fpga-test-sdc/bin/fpga-test-sdc +benchmarks/embench/wally*.json +benchmarks/embench/run* +sim/cfi.log From 8d2a1d93fdc21bf1e921dc7c046eecb09b0d5fc5 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 17 Nov 2023 18:31:44 -0800 Subject: [PATCH 13/14] Restored RV64GC BPRED_SIZE=10 for consistent synthesis results --- config/rv64gc/config.vh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index e00c9153d..84f4de599 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -150,7 +150,7 @@ localparam PLIC_SDC_ID = 32'd9; localparam BPRED_SUPPORTED = 1; localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT localparam BPRED_NUM_LHR = 32'd6; -localparam BPRED_SIZE = 32'd6; +localparam BPRED_SIZE = 32'd10; localparam BTB_SIZE = 32'd10; localparam RAS_SIZE = 32'd16; From cdc8a56b35ee7ffd3d41d173789853c06022c239 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 17 Nov 2023 20:25:24 -0800 Subject: [PATCH 14/14] turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep --- config/rv32gc/config.vh | 4 ++-- src/ieu/datapath.sv | 2 +- src/mdu/mdu.sv | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index 3b306a005..e095e6252 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -74,8 +74,8 @@ localparam ICACHE_LINELENINBITS = 32'd512; // Integer Divider Configuration // IDIV_BITSPERCYCLE must be 1, 2, or 4 -localparam IDIV_BITSPERCYCLE = 32'd4; -localparam IDIV_ON_FPU = 1; +localparam IDIV_BITSPERCYCLE = 32'd2; +localparam IDIV_ON_FPU = 0; // Legal number of PMP entries are 0, 16, or 64 localparam PMP_ENTRIES = 32'd16; diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index bb7638514..8c366a2ef 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -131,7 +131,7 @@ module datapath import cvw::*; #(parameter cvw_t P) ( if (P.F_SUPPORTED) begin:fpmux mux2 #(P.XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, IFResultM); mux2 #(P.XLEN) cvtresultmuxW(IFResultW, FCvtIntResW, FCvtIntW, IFCvtResultW); - if (P.IDIV_ON_FPU) begin + if (P.IDIV_ON_FPU & P.F_SUPPORTED) begin mux2 #(P.XLEN) divresultmuxW(MDUResultW, FIntDivResultW, IntDivW, MulDivResultW); end else begin assign MulDivResultW = MDUResultW; diff --git a/src/mdu/mdu.sv b/src/mdu/mdu.sv index 83327a460..e152fc6de 100644 --- a/src/mdu/mdu.sv +++ b/src/mdu/mdu.sv @@ -57,7 +57,7 @@ module mdu import cvw::*; #(parameter cvw_t P) ( // Start a divide when a new division instruction is received and the divider isn't already busy or finishing // When IDIV_ON_FPU is set, use the FPU divider instead // In ZMMUL, with M_SUPPORTED = 0, omit the divider - if ((P.IDIV_ON_FPU) || (!P.M_SUPPORTED)) begin:nodiv + if ((P.IDIV_ON_FPU & P.F_SUPPORTED) || (!P.M_SUPPORTED)) begin:nodiv assign QuotM = 0; assign RemM = 0; assign DivBusyE = 0;