From f8c656f1e053fefcd38dff77f2db87587275a4e3 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 4 Jan 2023 23:41:55 -0600 Subject: [PATCH] Simiplified global history branch predictor. --- pipelined/config/rv64gc/wally-config.vh | 3 +- pipelined/regression/wave.do | 159 +++++++++--------------- pipelined/src/ifu/bpred.sv | 10 +- pipelined/src/ifu/ifu.sv | 2 +- pipelined/testbench/tests.vh | 4 +- tests/custom/simple/global_hist_test.s | 87 +++++++++++++ tests/custom/simple/header.h | 2 + tests/custom/simple/main.c | 2 + 8 files changed, 162 insertions(+), 107 deletions(-) diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 65d27aa38..41b775e90 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -140,7 +140,8 @@ `define PLIC_UART_ID 10 `define BPRED_ENABLED 1 -`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE +//`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE +`define BPTYPE "BPGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 `define BPRED_SIZE 10 diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index b008df118..119559f65 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -84,53 +84,32 @@ add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SCOUNTEREN_REGW add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW -add wave -noupdate -group Bpred -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHR -add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF -add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]} -add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassE[0]} -add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredDirWrongE -add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check} -add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI -add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI -add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI -add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight -add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong -add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 17 -radix binary}} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel -add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext -add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN -add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr -add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr0 -add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr1 -add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateEN -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRLookup -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/RA1 -add wave -noupdate -group Bpred -expand -group prediction -radix binary /testbench/dut/core/ifu/bpred/bpred/BPPredF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BPInstrClassF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex -add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TargetPC -add wave -noupdate -group Bpred -expand -group prediction -expand -group ex -radix binary /testbench/dut/core/ifu/bpred/bpred/BPPredE -add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE -add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/BPPredDirWrongE -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePC -add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget -add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr -add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCE -add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/WA1 -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE -add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE -add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE +add wave -noupdate -expand -group Bpred -group {branch update selection inputs} -divider {class check} +add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/RA1 +add wave -noupdate -expand -group Bpred -expand -group prediction -radix binary /testbench/dut/core/ifu/bpred/bpred/BPPredF +add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF +add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BPInstrClassF +add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF +add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF +add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex +add wave -noupdate -expand -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TargetPC +add wave -noupdate -expand -group Bpred -expand -group prediction -expand -group ex -radix binary /testbench/dut/core/ifu/bpred/bpred/BPPredE +add wave -noupdate -expand -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE +add wave -noupdate -expand -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/BPPredDirWrongE +add wave -noupdate -expand -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex +add wave -noupdate -expand -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget +add wave -noupdate -expand -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN +add wave -noupdate -expand -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePC +add wave -noupdate -expand -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget +add wave -noupdate -expand -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/WA1 +add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE +add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE +add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE +add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE +add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE +add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE +add wave -noupdate -expand -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE +add wave -noupdate -expand -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F @@ -567,20 +546,20 @@ add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress -add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} -add wave -noupdate -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} -add wave -noupdate -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP DIRECTION WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BTA/JTA WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {JAL(R) INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]} -add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]} -add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]} -add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} -add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]} +add wave -noupdate -expand -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} +add wave -noupdate -expand -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} +add wave -noupdate -expand -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} +add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP DIRECTION WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]} +add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]} +add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BTA/JTA WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]} +add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {JAL(R) INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]} +add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]} +add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]} +add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]} +add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]} +add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]} +add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} +add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]} add wave -noupdate -group {ifu } -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/HREADY add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/FetchBuffer @@ -593,43 +572,27 @@ add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/VPN add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/tlb/tlb/TLBWrite add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PTE add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/VAdr -add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/FRD1E -add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/FRD2E -add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/FRD3E -add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcAE -add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcBE -add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/Funct3E -add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/MDUE -add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/W64E -add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/unpack/X -add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/unpack/Y -add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/unpack/Z -add wave -noupdate -expand -group FPU /testbench/dut/core/fpu/fpu/fregfile/rf -add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn -add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayCntEn -add wave -noupdate -expand -group uncore /testbench/dut/uncore/uncore/HADDR -add wave -noupdate -expand -group uncore /testbench/dut/uncore/uncore/HTRANS -add wave -noupdate -expand -group uncore /testbench/dut/uncore/uncore/HREADY -add wave -noupdate -expand -group uncore /testbench/dut/uncore/uncore/HSELRegions -add wave -noupdate -expand -group uncore /testbench/dut/uncore/uncore/HSELNoneD -add wave -noupdate -expand -group uncore /testbench/dut/uncore/uncore/HSELPLICD -add wave -noupdate -expand -group uncore /testbench/dut/uncore/uncore/HRDATA -add wave -noupdate /testbench/ResetCount -add wave -noupdate /testbench/InReset -add wave -noupdate /testbench/DCacheFlushDone -add wave -noupdate /testbench/DCacheFlushStart -add wave -noupdate /testbench/dut/core/fpu/fpu/XE -add wave -noupdate /testbench/dut/core/fpu/fpu/YE -add wave -noupdate /testbench/dut/core/fpu/fpu/ZE -add wave -noupdate /testbench/dut/core/fpu/fpu/PostProcResM -add wave -noupdate /testbench/dut/core/fpu/fpu/fregfile/rf -add wave -noupdate /testbench/dut/core/fpu/fpu/fhazard/ForwardXE -add wave -noupdate /testbench/dut/core/fpu/fpu/fhazard/ForwardYE -add wave -noupdate /testbench/dut/core/fpu/fpu/fhazard/ForwardZE -add wave -noupdate /testbench/dut/core/fpu/fpu/fhazard/YEnE +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD1E +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD2E +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD3E +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcAE +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcBE +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/Funct3E +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/MDUE +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/W64E +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/X +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/Y +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/Z +add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/fregfile/rf +add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HADDR +add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HTRANS +add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HREADY +add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELRegions +add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELNoneD +add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELPLICD +add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HRDATA TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {4266 ns} 0} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {4086041 ns} 0} quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -645,4 +608,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {4234 ns} {4338 ns} +WaveRestoreZoom {0 ns} {46713581 ns} diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv index f1fd1df76..6d669626f 100644 --- a/pipelined/src/ifu/bpred.sv +++ b/pipelined/src/ifu/bpred.sv @@ -49,6 +49,7 @@ module bpred ( input logic [`XLEN-1:0] PCF, // Fetch stage instruction address. input logic [`XLEN-1:0] PCD, // Decode stage instruction address. Also the address the branch predictor took. input logic [`XLEN-1:0] PCE, // Execution stage instruction address. + input logic [`XLEN-1:0] PCM, // Memory stage instruction address. // *** after reviewing the compressed instruction set I am leaning towards having the btb predict the instruction class. // *** the specifics of how this is encode is subject to change. @@ -95,10 +96,9 @@ module bpred ( .UpdatePrediction(UpdateBPPredE)); end else if (`BPTYPE == "BPGLOBAL") begin:Predictor - globalHistoryPredictor DirPredictor(.clk, .reset, .StallF, .StallE, - .PCNextF, .BPPredF, - .InstrClassE, .BPInstrClassF, .BPInstrClassD, .BPInstrClassE, .BPPredDirWrongE, - .PCE, .PCSrcE, .UpdateBPPredE); + globalhistory DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, + .PCNextF, .PCM, .DirPredictionF(BPPredF), .DirPredictionWrongE(BPPredDirWrongE), + .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); end else if (`BPTYPE == "BPGSHARE") begin:Predictor gsharePredictor DirPredictor(.clk, .reset, .StallF, .StallE, @@ -207,7 +207,7 @@ module bpred ( // The branch direction also need to checked. // However if the direction is wrong then the pc will be wrong. This is only relavent to checking the // accuracy of the direciton prediction. - assign BPPredDirWrongE = (BPPredE[1] ^ PCSrcE) & InstrClassE[0]; + //assign BPPredDirWrongE = (BPPredE[1] ^ PCSrcE) & InstrClassE[0]; // Finally we need to check if the class is wrong. When the class is wrong the BTB needs to be updated. // Also we want to track this in a performance counter. diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 2ea40b933..d08bffcfc 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -323,7 +323,7 @@ module ifu ( bpred bpred(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, - .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE, + .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE, .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM); diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 48a29303b..886d3fefa 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -1927,8 +1927,8 @@ string imperas32f[] = '{ string custom[] = '{ `CUSTOM, - "cacheTest", - "simple" + "simple", + "cacheTest" }; string testsBP64[] = '{ `IMPERASTEST, diff --git a/tests/custom/simple/global_hist_test.s b/tests/custom/simple/global_hist_test.s index 2b0ba5b20..9e3bfd7b5 100644 --- a/tests/custom/simple/global_hist_test.s +++ b/tests/custom/simple/global_hist_test.s @@ -1,3 +1,87 @@ +.section .text +.globl oneLoopTest +.type oneLoopTest, @function +oneLoopTest: + li t1, 0 + li t2, 30 + + mv t3, t1 + mv t4, t2 +oneLoopTest1: + # instruction + addi t3, t3, 1 + li t5, 10 # filler instructions + li t6, 100 + li a0, 1000 + li a1, 10000 + bne t3, t4, oneLoopTest1 # this branch toggles between taken and not taken. + + mv t3, t1 + mv t4, t2 +oneLoopTest2: + # instruction + addi t3, t3, 1 + li t5, 10 # filler instructions + li t6, 100 + li a0, 1000 + bne t3, t4, oneLoopTest2 # this branch toggles between taken and not taken. + + mv t3, t1 + mv t4, t2 +oneLoopTest3: + # instruction + addi t3, t3, 1 + li t5, 10 # filler instructions + li t6, 100 + bne t3, t4, oneLoopTest3 # this branch toggles between taken and not taken. + + mv t3, t1 + mv t4, t2 +oneLoopTest4: + # instruction + addi t3, t3, 1 + li t5, 10 # filler instructions + bne t3, t4, oneLoopTest4 # this branch toggles between taken and not taken. + + mv t3, t1 + mv t4, t2 +oneLoopTest5: + # instruction + addi t3, t3, 1 + bne t3, t4, oneLoopTest5 # this branch toggles between taken and not taken. + + ret + +.section .text +.globl global_hist_4_space_test +.type global_hist_4_space_test, @function +global_hist_4_space_test: + li t1, 1 + li t2, 200 + li t3, 0 + li t4, 1 + +loop_4: + # instruction + addi t3, t3, 1 + addi t3, t3, 1 + addi t3, t3, 1 + addi t3, t3, 1 + beqz t4, zero_4 # this branch toggles between taken and not taken. + li t4, 0 + j one_4 +zero_4: + li t4, 1 + addi t3, t3, 1 + add t1, t1, t4 + +one_4: + addi t3, t3, 1 + addi t2, t2, -1 + bnez t2, loop_4 + + ret + .section .text .globl global_hist_3_space_test .type global_hist_3_space_test, @function @@ -12,11 +96,13 @@ loop_3: addi t3, t3, 1 addi t3, t3, 1 addi t3, t3, 1 + addi t3, t3, 1 beqz t4, zero_3 # this branch toggles between taken and not taken. li t4, 0 j one_3 zero_3: li t4, 1 + addi t3, t3, 1 add t1, t1, t4 one_3: @@ -26,6 +112,7 @@ one_3: ret + .section .text .globl global_hist_2_space_test .type global_hist_2_space_test, @function diff --git a/tests/custom/simple/header.h b/tests/custom/simple/header.h index aab8973fd..7a1b51926 100644 --- a/tests/custom/simple/header.h +++ b/tests/custom/simple/header.h @@ -9,4 +9,6 @@ void global_hist_0_space_test(); void global_hist_1_space_test(); void global_hist_2_space_test(); void global_hist_3_space_test(); +void global_hist_4_space_test(); +void oneLoopTest(); #endif diff --git a/tests/custom/simple/main.c b/tests/custom/simple/main.c index 564b474e1..83d43e32d 100644 --- a/tests/custom/simple/main.c +++ b/tests/custom/simple/main.c @@ -2,6 +2,8 @@ int main(){ //int res = icache_spill_test(); + oneLoopTest(); + global_hist_4_space_test(); global_hist_3_space_test(); global_hist_2_space_test(); global_hist_1_space_test();