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Updating wallyTracer syntax to match wally style

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Huda-10xe 2024-12-22 08:40:16 -08:00
parent ab663e5bc8
commit f7eecdc56e
1 changed files with 40 additions and 40 deletions
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80
testbench/common/wallyTracer.sv
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@ -67,11 +67,11 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
logic InterruptM, InterruptW; logic InterruptM, InterruptW;
//For VM Verification //For VM Verification
logic [(P.XLEN-1):0] VAdr_iF,VAdr_iD,VAdr_iE,VAdr_iM,VAdr_iW,VAdr_dM,VAdr_dW; logic [(P.XLEN-1):0] IVAdrF,IVAdrD,IVAdrE,IVAdrM,IVAdrW,DVAdrM,DVAdrW;
logic [(P.XLEN-1):0] PTE_iF,PTE_iD,PTE_iE,PTE_iM,PTE_iW,PTE_dM,PTE_dW; logic [(P.XLEN-1):0] IPTEF,IPTED,IPTEE,IPTEM,IPTEW,DPTEM,DPTEW;
logic [(P.PA_BITS-1):0] PA_iF,PA_iD,PA_iE,PA_iM,PA_iW,PA_dM,PA_dW; logic [(P.PA_BITS-1):0] IPAF,IPAD,IPAE,IPAM,IPAW,DPAM,DPAW;
logic [(P.PPN_BITS-1):0] PPN_iF,PPN_iD,PPN_iE,PPN_iM,PPN_iW,PPN_dM,PPN_dW; logic [(P.PPN_BITS-1):0] IPPNF,IPPND,IPPNE,IPPNM,IPPNW,DPPNM,DPPNW;
logic [1:0] PageType_iF, PageType_iD, PageType_iE, PageType_iM, PageType_iW, PageType_dM, PageType_dW; logic [1:0] IPageTypeF, IPageTypeD, IPageTypeE, IPageTypeM, IPageTypeW, DPageTypeM, DPageTypeW;
logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW; logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW;
logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW; logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW;
@ -115,19 +115,19 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
end end
//For VM Verification //For VM Verification
assign VAdr_iF = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr; assign IVAdrF = testbench.dut.core.ifu.immu.immu.tlb.tlb.VAdr;
assign VAdr_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr; assign DVAdrM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.VAdr;
assign PA_iF = testbench.dut.core.ifu.immu.immu.PhysicalAddress; assign IPAF = testbench.dut.core.ifu.immu.immu.PhysicalAddress;
assign PA_dM = testbench.dut.core.lsu.dmmu.dmmu.PhysicalAddress; assign DPAM = testbench.dut.core.lsu.dmmu.dmmu.PhysicalAddress;
assign ReadAccessM = testbench.dut.core.lsu.dmmu.dmmu.ReadAccessM; assign ReadAccessM = testbench.dut.core.lsu.dmmu.dmmu.ReadAccessM;
assign WriteAccessM = testbench.dut.core.lsu.dmmu.dmmu.WriteAccessM; assign WriteAccessM = testbench.dut.core.lsu.dmmu.dmmu.WriteAccessM;
assign ExecuteAccessF = testbench.dut.core.ifu.immu.immu.ExecuteAccessF; assign ExecuteAccessF = testbench.dut.core.ifu.immu.immu.ExecuteAccessF;
assign PTE_iF = testbench.dut.core.ifu.immu.immu.PTE; assign IPTEF = testbench.dut.core.ifu.immu.immu.PTE;
assign PTE_dM = testbench.dut.core.lsu.dmmu.dmmu.PTE; assign DPTEM = testbench.dut.core.lsu.dmmu.dmmu.PTE;
assign PPN_iF = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN; assign IPPNF = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN;
assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; assign DPPNM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN;
assign PageType_iF = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal; assign IPageTypeF = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal;
assign PageType_dM = testbench.dut.core.lsu.dmmu.dmmu.PageTypeWriteVal; assign DPageTypeM = testbench.dut.core.lsu.dmmu.dmmu.PageTypeWriteVal;
logic valid; logic valid;
@ -362,35 +362,35 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
flopenrc #(1) CSRWriteWReg (clk, reset, FlushW, ~StallW, CSRWriteM, CSRWriteW); flopenrc #(1) CSRWriteWReg (clk, reset, FlushW, ~StallW, CSRWriteM, CSRWriteW);
//for VM Verification //for VM Verification
flopenrc #(P.XLEN) VAdr_iDReg (clk, reset, 1'b0, SelHPTW, VAdr_iF, VAdr_iD); //Virtual Address for IMMU flopenrc #(P.XLEN) IVAdrDReg (clk, reset, 1'b0, SelHPTW, IVAdrF, IVAdrD); //Virtual Address for IMMU
flopenrc #(P.XLEN) VAdr_iEReg (clk, reset, 1'b0, ~StallE, VAdr_iD, VAdr_iE); //Virtual Address for IMMU flopenrc #(P.XLEN) IVAdrEReg (clk, reset, 1'b0, ~StallE, IVAdrD, IVAdrE); //Virtual Address for IMMU
flopenrc #(P.XLEN) VAdr_iMReg (clk, reset, 1'b0, ~StallM, VAdr_iE, VAdr_iM); //Virtual Address for IMMU flopenrc #(P.XLEN) IVAdrMReg (clk, reset, 1'b0, ~StallM, IVAdrE, IVAdrM); //Virtual Address for IMMU
flopenrc #(P.XLEN) VAdr_iWReg (clk, reset, 1'b0, SelHPTW, VAdr_iM, VAdr_iW); //Virtual Address for IMMU flopenrc #(P.XLEN) IVAdrWReg (clk, reset, 1'b0, SelHPTW, IVAdrM, IVAdrW); //Virtual Address for IMMU
flopenrc #(P.XLEN) VAdr_dWReg (clk, reset, 1'b0, SelHPTW, VAdr_dM, VAdr_dW); //Virtual Address for DMMU flopenrc #(P.XLEN) DVAdrWReg (clk, reset, 1'b0, SelHPTW, DVAdrM, DVAdrW); //Virtual Address for DMMU
flopenrc #(P.PA_BITS) PA_iDReg (clk, reset, 1'b0, SelHPTW, PA_iF, PA_iD); //Physical Address for IMMU flopenrc #(P.PA_BITS) IPADReg (clk, reset, 1'b0, SelHPTW, IPAF, IPAD); //Physical Address for IMMU
flopenrc #(P.PA_BITS) PA_iEReg (clk, reset, 1'b0, ~StallE, PA_iD, PA_iE); //Physical Address for IMMU flopenrc #(P.PA_BITS) IPAEReg (clk, reset, 1'b0, ~StallE, IPAD, IPAE); //Physical Address for IMMU
flopenrc #(P.PA_BITS) PA_iMReg (clk, reset, 1'b0, ~StallM, PA_iE, PA_iM); //Physical Address for IMMU flopenrc #(P.PA_BITS) IPAMReg (clk, reset, 1'b0, ~StallM, IPAE, IPAM); //Physical Address for IMMU
flopenrc #(P.PA_BITS) PA_iWReg (clk, reset, 1'b0, SelHPTW, PA_iM, PA_iW); //Physical Address for IMMU flopenrc #(P.PA_BITS) IPAWReg (clk, reset, 1'b0, SelHPTW, IPAM, IPAW); //Physical Address for IMMU
flopenrc #(P.PA_BITS) PA_dWReg (clk, reset, 1'b0, SelHPTW, PA_dM, PA_dW); //Physical Address for DMMU flopenrc #(P.PA_BITS) DPAWReg (clk, reset, 1'b0, SelHPTW, DPAM, DPAW); //Physical Address for DMMU
flopenrc #(P.XLEN) PTE_iDReg (clk, reset, 1'b0, SelHPTW, PTE_iF, PTE_iD); //PTE for IMMU flopenrc #(P.XLEN) IPTEDReg (clk, reset, 1'b0, SelHPTW, IPTEF, IPTED); //PTE for IMMU
flopenrc #(P.XLEN) PTE_iEReg (clk, reset, 1'b0, ~StallE, PTE_iD, PTE_iE); //PTE for IMMU flopenrc #(P.XLEN) IPTEEReg (clk, reset, 1'b0, ~StallE, IPTED, IPTEE); //PTE for IMMU
flopenrc #(P.XLEN) PTE_iMReg (clk, reset, 1'b0, ~StallM, PTE_iE, PTE_iM); //PTE for IMMU flopenrc #(P.XLEN) IPTEMReg (clk, reset, 1'b0, ~StallM, IPTEE, IPTEM); //PTE for IMMU
flopenrc #(P.XLEN) PTE_iWReg (clk, reset, 1'b0, SelHPTW, PTE_iM, PTE_iW); //PTE for IMMU flopenrc #(P.XLEN) IPTEWReg (clk, reset, 1'b0, SelHPTW, IPTEM, IPTEW); //PTE for IMMU
flopenrc #(P.XLEN) PTE_dWReg (clk, reset, 1'b0, SelHPTW, PTE_dM, PTE_dW); //PTE for DMMU flopenrc #(P.XLEN) DPTEWReg (clk, reset, 1'b0, SelHPTW, DPTEM, DPTEW); //PTE for DMMU
flopenrc #(2) PageType_iDReg (clk, reset, 1'b0, SelHPTW, PageType_iF, PageType_iD); //PageType (kilo, mega, giga, tera) from IMMU flopenrc #(2) IPageTypeDReg (clk, reset, 1'b0, SelHPTW, IPageTypeF, IPageTypeD); //PageType (kilo, mega, giga, tera) from IMMU
flopenrc #(2) PageType_iEReg (clk, reset, 1'b0, ~StallE, PageType_iD, PageType_iE); //PageType (kilo, mega, giga, tera) from IMMU flopenrc #(2) IPageTypeEReg (clk, reset, 1'b0, ~StallE, IPageTypeD, IPageTypeE); //PageType (kilo, mega, giga, tera) from IMMU
flopenrc #(2) PageType_iMReg (clk, reset, 1'b0, ~StallM, PageType_iE, PageType_iM); //PageType (kilo, mega, giga, tera) from IMMU flopenrc #(2) IPageTypeMReg (clk, reset, 1'b0, ~StallM, IPageTypeE, IPageTypeM); //PageType (kilo, mega, giga, tera) from IMMU
flopenrc #(2) PageType_iWReg (clk, reset, 1'b0, SelHPTW, PageType_iM, PageType_iW); //PageType (kilo, mega, giga, tera) from IMMU flopenrc #(2) IPageTypeWReg (clk, reset, 1'b0, SelHPTW, IPageTypeM, IPageTypeW); //PageType (kilo, mega, giga, tera) from IMMU
flopenrc #(2) PageType_dWReg (clk, reset, 1'b0, SelHPTW, PageType_dM, PageType_dW); //PageType (kilo, mega, giga, tera) from DMMU flopenrc #(2) DPageTypeWReg (clk, reset, 1'b0, SelHPTW, DPageTypeM, DPageTypeW); //PageType (kilo, mega, giga, tera) from DMMU
flopenrc #(P.PPN_BITS) PPN_iDReg (clk, reset, 1'b0, ~StallD, PPN_iF, PPN_iD); //Physical Page Number for IMMU flopenrc #(P.PPN_BITS) IPPNDReg (clk, reset, 1'b0, ~StallD, IPPNF, IPPND); //Physical Page Number for IMMU
flopenrc #(P.PPN_BITS) PPN_iEReg (clk, reset, 1'b0, ~StallE, PPN_iD, PPN_iE); //Physical Page Number for IMMU flopenrc #(P.PPN_BITS) IPPNEReg (clk, reset, 1'b0, ~StallE, IPPND, IPPNE); //Physical Page Number for IMMU
flopenrc #(P.PPN_BITS) PPN_iMReg (clk, reset, 1'b0, ~StallM, PPN_iE, PPN_iM); //Physical Page Number for IMMU flopenrc #(P.PPN_BITS) IPPNMReg (clk, reset, 1'b0, ~StallM, IPPNE, IPPNM); //Physical Page Number for IMMU
flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, 1'b0, ~StallW, PPN_iM, PPN_iW); //Physical Page Number for IMMU flopenrc #(P.PPN_BITS) IPPNWReg (clk, reset, 1'b0, ~StallW, IPPNM, IPPNW); //Physical Page Number for IMMU
flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, 1'b0, ~StallW, PPN_dM, PPN_dW); //Physical Page Number for DMMU flopenrc #(P.PPN_BITS) DPPNWReg (clk, reset, 1'b0, ~StallW, DPPNM, DPPNW); //Physical Page Number for DMMU
flopenrc #(1) ReadAccessWReg (clk, reset, 1'b0, ~GatedStallW, ReadAccessM, ReadAccessW); //LoadAccess flopenrc #(1) ReadAccessWReg (clk, reset, 1'b0, ~GatedStallW, ReadAccessM, ReadAccessW); //LoadAccess
flopenrc #(1) WriteAccessWReg (clk, reset, 1'b0, ~GatedStallW, WriteAccessM, WriteAccessW); //StoreAccess flopenrc #(1) WriteAccessWReg (clk, reset, 1'b0, ~GatedStallW, WriteAccessM, WriteAccessW); //StoreAccess