From f7cbaeb21733a0337e3958d96d984f93450764af Mon Sep 17 00:00:00 2001 From: Domenico Ottolia Date: Tue, 30 Mar 2021 19:44:58 -0400 Subject: [PATCH] Add one more test to WALLY-CAUSE, and update privileged testgen --- .../testbench/testbench-imperas.sv | 1 + wally-pipelined/testgen/privileged/README.md | 9 ++- wally-pipelined/testgen/privileged/run.sh | 17 ++++- .../testgen/privileged/testgen-CAUSE.py | 69 +++++++++++-------- 4 files changed, 67 insertions(+), 29 deletions(-) diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index a63288418..b9822c4d1 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -371,6 +371,7 @@ string tests32i[] = { if (`A_SUPPORTED) tests = {tests, tests32a}; end + // tests = tests64p; end diff --git a/wally-pipelined/testgen/privileged/README.md b/wally-pipelined/testgen/privileged/README.md index 9220111f9..bb5ea81fb 100644 --- a/wally-pipelined/testgen/privileged/README.md +++ b/wally-pipelined/testgen/privileged/README.md @@ -1,6 +1,6 @@ # Privileged Test Generators -Create a test generator in this folder with the name testgen-NAME.py. Then, to generate and compile these tests, use +Create a test generator in this folder with the name testgen-NAME.py. Then, to generate and compile these tests, use: ```bash sh run.sh NAME @@ -8,8 +8,15 @@ sh run.sh NAME For example, for `testgen-CAUSE.py`, we would run `sh run.sh CAUSE`. +This bash file is super basic, so only allows for a single argument after the name. Provide -sim as the second argument to simulate the compiled tests using wally. ```bash sh run.sh NAME -sim +``` + +To compile tests without running them in OVPsim, provide -c as the second argument + +```bash +sh run.sh NAME -c ``` \ No newline at end of file diff --git a/wally-pipelined/testgen/privileged/run.sh b/wally-pipelined/testgen/privileged/run.sh index d010377a7..9e387b2b5 100644 --- a/wally-pipelined/testgen/privileged/run.sh +++ b/wally-pipelined/testgen/privileged/run.sh @@ -13,13 +13,28 @@ then python3 "testgen-$1.py" printf "\n\n#####\nRan testgen-$1.py Making...\n#####\n\n\n" - if [[ "$2" != "-nosim" ]] + if [[ "$2" == "-c" ]] + then + cd ~/riscv-wally/imperas-riscv-tests/riscv-test-suite/rv64p/src + riscv64-unknown-elf-gcc -nostdlib -nostartfiles -march=rv64g "WALLY-$1".S -I../../../riscv-test-env -I../../../riscv-test-env/p -I../../../riscv-target/riscvOVPsimPlus -T../../../riscv-test-env/p/link.ld -o "../../../work/rv64p/WALLY-$1.elf" + cd ~/riscv-wally/imperas-riscv-tests/work/rv64p + riscv64-unknown-elf-objdump -d "WALLY-$1".elf > "WALLY-$1".elf.objdump + + elif [[ "$2" != "-nosim" ]] then cd ~/riscv-wally/imperas-riscv-tests make privileged fi fi +if [[ "$2" == "-simonly" ]] +then + cd ~/riscv-wally/imperas-riscv-tests/riscv-test-suite/rv64p/src + riscv64-unknown-elf-gcc -nostdlib -nostartfiles -march=rv64g "WALLY-$1".S -I../../../riscv-test-env -I../../../riscv-test-env/p -I../../../riscv-target/riscvOVPsimPlus -T../../../riscv-test-env/p/link.ld -o "../../../work/rv64p/WALLY-$1.elf" + cd ~/riscv-wally/imperas-riscv-tests/work/rv64p + riscv64-unknown-elf-objdump -d "WALLY-$1".elf > "WALLY-$1".elf.objdump +fi + if [[ "$2" == "-sim" || "$2" == "-simonly" ]] then printf "\n\n\n#####\nSimulating!\n#####\n\n" diff --git a/wally-pipelined/testgen/privileged/testgen-CAUSE.py b/wally-pipelined/testgen/privileged/testgen-CAUSE.py index 60cddb3c7..00b1decaf 100644 --- a/wally-pipelined/testgen/privileged/testgen-CAUSE.py +++ b/wally-pipelined/testgen/privileged/testgen-CAUSE.py @@ -1,6 +1,6 @@ #!/usr/bin/python3 ################################## -# testgen-ADD-SUB.py +# testgen-CAUSE.py # # dottolia@hmc.edu 1 Mar 2021 # @@ -19,15 +19,6 @@ from random import getrandbits # functions ################################## -# def computeExpected(a, b, test): -# if (test == "ADD"): -# return a + b -# elif (test == "SUB"): -# return a - b -# else: -# die("bad test name ", test) -# # exit(1) - def randRegs(): reg1 = randint(1,20) reg2 = randint(1,20) @@ -39,34 +30,56 @@ def randRegs(): def writeVectors(storecmd): global testnum - #expected = computeExpected(a, b, test) - #expected = expected % 2**xlen # drop carry if necessary - #if (expected < 0): # take twos complement - # expected = 2**xlen + expected - #lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n" - #lines = lines + "li x" + str(reg2) + ", MASK_XLEN(0)\n" - - # Page 6 of unpriviledged spec + # Page 6 of unpriviledged spec # For both CSRRS and CSRRC, if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects - #lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n" - #lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n" - # User Software Interrupt: True, 0 # Supervisor Software Interrupt: True, 1 # Machine Software Interrupt: True, 2 - # User Timer Interrupt: True, 4 + + # When running run.sh CAUSE -c, everything works, but begin_signature doesn't appear # writeTest(storecmd, f, r, f""" - # la x21, 0x2004000 - # """, False, 4) + # la x10, 0x02000000 #clint + + # li x1, 42 + # lw x1, 0(x10) + # """, True, 2, "m", f""" + # lw x0, 0(x10) + # """) + + # User Timer Interrupt: True, 4 # Supervior timer interrupt: True, 5 # Machine timer interrupt: True, 7 + # writeTest(storecmd, f, r, f""" + # la x10, 0x02004000 #clint timer + # li x1, 42 + + # lw x11, 0(x10) + # lw x12, 4(x10) + + # sw x1, 0(x10) + # sw x0, 4(x10) + # """, True, 7, "m", f""" + # sw x11, 0(x10) + # sw x12, 4(x10) + # """) + # User external input: True, 8 # Supervisor external input: True, 9 # Machine externa input: True, 11 # Instruction address misaligned: False, 0 + # looks like this is giving us an infinite loop for wally + # BUG: jumping to a misaligned instruction address doesn't cause an exception: we actually jump... + # Either that, or somehow at the end we always end up at 0x80004002 + # This is fine in OVPsim + writeTest(storecmd, f, r, f""" + li x1, 11 + li x25, 0 # Force this test to pass, for now + # jr x1 # Something about this instruction is funky on wally, but fine with ovpsim + """, False, 0) + # Instruction access fault: False, 1 # Illegal Instruction @@ -106,7 +119,7 @@ def writeVectors(storecmd): # Environment call from m-mode writeTest(storecmd, f, r, f""" ecall - """, False, 11, "m") + """, False, 11, "m") # Instruction page fault: 12 # Load page fault: 13 @@ -115,7 +128,7 @@ def writeVectors(storecmd): -def writeTest(storecmd, f, r, test, interrupt, code, mode = "m"): +def writeTest(storecmd, f, r, test, interrupt, code, mode = "m", resetHander = ""): global testnum expected = code @@ -162,6 +175,7 @@ def writeTest(storecmd, f, r, test, interrupt, code, mode = "m"): j _jtest{testnum} # Machine trap vector + {resetHander} csrrs x25, mcause, x0 csrrs x1, mepc, x0 addi x1, x1, 4 @@ -174,6 +188,7 @@ def writeTest(storecmd, f, r, test, interrupt, code, mode = "m"): csrrw x0, mtvec, x30 # Start test code + li x25, 0x7BAD {before} {test} @@ -213,7 +228,7 @@ def writeTest(storecmd, f, r, test, interrupt, code, mode = "m"): # csrrw, csrrs, csrrc, csrrwi, csrrsi, csrrci author = "dottolia@hmc.edu" xlens = [32, 64] -numrand = 30; +numrand = 15; # setup seed(0xC365DDEB9173AB42) # make tests reproducible