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Ross Thompson 2023-01-20 13:09:42 -06:00
parent c7f4970597
commit f78bfc4940
2 changed files with 21 additions and 21 deletions
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2
pipelined/src/cache/cachefsm.sv vendored
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@ -56,8 +56,8 @@ module cachefsm (
input logic FlushWayFlag, // On the last way for any set of a cache flush input logic FlushWayFlag, // On the last way for any set of a cache flush
output logic SelAdr, // [0] SRAM reads from NextAdr, [1] SRAM reads from PAdr output logic SelAdr, // [0] SRAM reads from NextAdr, [1] SRAM reads from PAdr
output logic ClearValid, // Clear the valid bit in the selected way and set output logic ClearValid, // Clear the valid bit in the selected way and set
output logic ClearDirty, // Clear the dirty bit in the selected way and set
output logic SetValid, // Set the dirty bit in the selected way and set output logic SetValid, // Set the dirty bit in the selected way and set
output logic ClearDirty, // Clear the dirty bit in the selected way and set
output logic SetDirty, // Set the dirty bit in the selected way and set output logic SetDirty, // Set the dirty bit in the selected way and set
output logic SelWriteback, // Overrides cached tag check to select a specific way and set for writeback output logic SelWriteback, // Overrides cached tag check to select a specific way and set for writeback
output logic LRUWriteEn, // Update the LRU state output logic LRUWriteEn, // Update the LRU state

40
pipelined/src/cache/cacheway.sv vendored
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@ -29,28 +29,28 @@
module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
OFFSETLEN = 5, INDEXLEN = 9, DIRTY_BITS = 1) ( OFFSETLEN = 5, INDEXLEN = 9, DIRTY_BITS = 1) (
input logic clk, input logic clk,
input logic CacheEn,
input logic reset, input logic reset,
input logic [$clog2(NUMLINES)-1:0] CAdr, input logic FlushStage, // Pipeline flush of second stage (prevent writes and bus operations)
input logic [`PA_BITS-1:0] PAdr, input logic CacheEn, // Enable the cache memory arrays. Disable hold read data constant
input logic [LINELEN-1:0] LineWriteData, input logic [$clog2(NUMLINES)-1:0] CAdr, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr
input logic SetValid, input logic [`PA_BITS-1:0] PAdr, // Physical address
input logic ClearValid, input logic [LINELEN-1:0] LineWriteData, // Final data written to cache (D$ only)
input logic SetDirty, input logic SetValid, // Set the dirty bit in the selected way and set
input logic ClearDirty, input logic ClearValid, // Clear the valid bit in the selected way and set
input logic SelWriteback, input logic SetDirty, // Set the dirty bit in the selected way and set
input logic SelFlush, input logic ClearDirty, // Clear the dirty bit in the selected way and set
input logic VictimWay, input logic SelWriteback, // Overrides cached tag check to select a specific way and set for writeback
input logic FlushWay, input logic SelFlush, // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr
input logic InvalidateCache, input logic VictimWay, // LRU selected this way as victim to evict
input logic FlushStage, input logic FlushWay, // This way is selected for flush and possible writeback if dirty
input logic [LINELEN/8-1:0] LineByteMask, input logic InvalidateCache,//Clear all valid bits
input logic [LINELEN/8-1:0] LineByteMask, // Final byte enables to cache (D$ only)
output logic [LINELEN-1:0] ReadDataLineWay, output logic [LINELEN-1:0] ReadDataLineWay,// This way's read data if valid
output logic HitWay, output logic HitWay, // This way hits
output logic ValidWay, output logic ValidWay, // This way is valid
output logic DirtyWay, output logic DirtyWay, // This way is dirty
output logic [TAGLEN-1:0] TagWay); output logic [TAGLEN-1:0] TagWay); // THis way's tag if valid
localparam integer WORDSPERLINE = LINELEN/`XLEN; localparam integer WORDSPERLINE = LINELEN/`XLEN;
localparam integer BYTESPERLINE = LINELEN/8; localparam integer BYTESPERLINE = LINELEN/8;