mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/openhwgroup/cvw
This commit is contained in:
Kevin Thomas
commit
f7838b869b
@ -54,47 +54,67 @@ module fdivsqrtpreproc (
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logic [`DIVb:0] PreSqrtX;
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logic [`DIVb+3:0] DivX, DivXShifted, SqrtX, PreShiftX; // Variations of dividend, to be muxed
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logic [`NE+1:0] QeE; // Quotient Exponent (FP only)
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logic [`DIVb-1:0] IFNormLenX, IFNormLenD; // Correctly-sized inputs for iterator
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logic [`DIVb-1:0] IFX, IFD; // Correctly-sized inputs for iterator, selected from int or fp input
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logic [`DIVBLEN:0] mE, ell; // Leading zeros of inputs
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logic NumerZeroE; // Numerator is zero (X or A)
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logic AZeroE, BZeroE; // A or B is Zero for integer division
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logic signedDiv; // signed division
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logic NegQuotE; // Integer quotient is negative
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logic AsE, BsE; // Signs of integer inputs
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logic [`XLEN-1:0] AE; // input A after W64 adjustment
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if (`IDIV_ON_FPU) begin:intpreproc // Int Supported
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logic signedDiv, NegQuotE;
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logic AsBit, BsBit, AsE, BsE, ALTBE;
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logic [`XLEN-1:0] AE, BE, PosA, PosB;
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logic [`DIVBLEN:0] ZeroDiff, p;
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logic [`XLEN-1:0] BE, PosA, PosB;
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// Extract inputs, signs, zero, depending on W64 mode if applicable
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assign signedDiv = ~Funct3E[0];
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assign NegQuotE = AsE ^ BsE; // Quotient is negative
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// Source handling
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if (`XLEN==64) begin // 64-bit, supports W64
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mux2 #(1) azeromux(~(|ForwardedSrcAE), ~(|ForwardedSrcAE[31:0]), W64E, AZeroE);
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mux2 #(1) bzeromux(~(|ForwardedSrcBE), ~(|ForwardedSrcBE[31:0]), W64E, BZeroE);
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mux2 #(1) abitmux(ForwardedSrcAE[63], ForwardedSrcAE[31], W64E, AsBit);
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mux2 #(1) bbitmux(ForwardedSrcBE[63], ForwardedSrcBE[31], W64E, BsBit);
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mux2 #(64) amux(ForwardedSrcAE, {{(`XLEN-32){AsE}}, ForwardedSrcAE[31:0]}, W64E, AE);
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mux2 #(64) bmux(ForwardedSrcBE, {{(`XLEN-32){BsE}}, ForwardedSrcBE[31:0]}, W64E, BE);
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assign AsE = signedDiv & AsBit;
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assign BsE = signedDiv & BsBit;
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mux2 #(64) amux(ForwardedSrcAE, {{32{ForwardedSrcAE[31] & signedDiv}}, ForwardedSrcAE[31:0]}, W64E, AE);
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mux2 #(64) bmux(ForwardedSrcBE, {{32{ForwardedSrcBE[31] & signedDiv}}, ForwardedSrcBE[31:0]}, W64E, BE);
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end else begin // 32 bits only
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assign AsE = signedDiv & ForwardedSrcAE[31];
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assign BsE = signedDiv & ForwardedSrcBE[31];
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assign AE = ForwardedSrcAE;
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assign BE = ForwardedSrcBE;
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assign AZeroE = ~(|ForwardedSrcAE);
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assign BZeroE = ~(|ForwardedSrcBE);
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end
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assign AZeroE = ~(|AE);
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assign BZeroE = ~(|BE);
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assign AsE = AE[`XLEN-1] & signedDiv;
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assign BsE = BE[`XLEN-1] & signedDiv;
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assign NegQuotE = AsE ^ BsE; // Integer Quotient is negative
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// Force integer inputs to be postiive
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mux2 #(`XLEN) posamux(AE, -AE, AsE, PosA);
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mux2 #(`XLEN) posbmux(BE, -BE, BsE, PosB);
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// Select integer or floating point inputs
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mux2 #(`DIVb) ifxmux({Xm, {(`DIVb-`NF-1){1'b0}}}, {PosA, {(`DIVb-`XLEN){1'b0}}}, IntDivE, IFNormLenX);
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mux2 #(`DIVb) ifdmux({Ym, {(`DIVb-`NF-1){1'b0}}}, {PosB, {(`DIVb-`XLEN){1'b0}}}, IntDivE, IFNormLenD);
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mux2 #(`DIVb) ifxmux({Xm, {(`DIVb-`NF-1){1'b0}}}, {PosA, {(`DIVb-`XLEN){1'b0}}}, IntDivE, IFX);
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mux2 #(`DIVb) ifdmux({Ym, {(`DIVb-`NF-1){1'b0}}}, {PosB, {(`DIVb-`XLEN){1'b0}}}, IntDivE, IFD);
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end else begin // Int not supported
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assign IFX = {Xm, {(`DIVb-`NF-1){1'b0}}};
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assign IFD = {Ym, {(`DIVb-`NF-1){1'b0}}};
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end
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// count leading zeros for Subnorm FP and to normalize integer inputs
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lzc #(`DIVb) lzcX (IFX, ell);
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lzc #(`DIVb) lzcY (IFD, mE);
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// Normalization shift
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assign XPreproc = IFX << (ell + {{`DIVBLEN{1'b0}}, 1'b1}); // *** try to remove this +1
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assign DPreproc = IFD << (mE + {{`DIVBLEN{1'b0}}, 1'b1});
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// append leading 1 (for normal inputs)
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// shift square root to be in range [1/4, 1)
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// Normalized numbers are shifted right by 1 if the exponent is odd
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// Denormalized numbers have Xe = 0 and an unbiased exponent of 1-BIAS. They are shifted right if the number of leading zeros is odd.
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mux2 #(`DIVb+1) sqrtxmux({~XZeroE, XPreproc}, {1'b0, ~XZeroE, XPreproc[`DIVb-1:1]}, (Xe[0] ^ ell[0]), PreSqrtX);
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assign DivX = {3'b000, ~NumerZeroE, XPreproc};
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if (`IDIV_ON_FPU) begin:intrightshift // Int Supported
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logic [`DIVBLEN:0] ZeroDiff, p;
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logic ALTBE;
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// calculate number of fractional bits p
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assign ZeroDiff = mE - ell; // Difference in number of leading zeros
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@ -138,29 +158,11 @@ module fdivsqrtpreproc (
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flopen #(`XLEN) srcareg(clk, IFDivStartE, AE, AM);
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if (`XLEN==64)
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flopen #(1) w64reg(clk, IFDivStartE, W64E, W64M);
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end else begin // Int not supported
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assign IFNormLenX = {Xm, {(`DIVb-`NF-1){1'b0}}};
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assign IFNormLenD = {Ym, {(`DIVb-`NF-1){1'b0}}};
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end else begin
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assign NumerZeroE = XZeroE;
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assign X = PreShiftX;
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end
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// count leading zeros for Subnorm FP and to normalize integer inputs
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lzc #(`DIVb) lzcX (IFNormLenX, ell);
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lzc #(`DIVb) lzcY (IFNormLenD, mE);
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// Normalization shift
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assign XPreproc = IFNormLenX << (ell + {{`DIVBLEN{1'b0}}, 1'b1}); // *** try to remove this +1
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assign DPreproc = IFNormLenD << (mE + {{`DIVBLEN{1'b0}}, 1'b1});
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// append leading 1 (for normal inputs)
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// shift square root to be in range [1/4, 1)
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// Normalized numbers are shifted right by 1 if the exponent is odd
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// Denormalized numbers have Xe = 0 and an unbiased exponent of 1-BIAS. They are shifted right if the number of leading zeros is odd.
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mux2 #(`DIVb+1) sqrtxmux({~XZeroE, XPreproc}, {1'b0, ~XZeroE, XPreproc[`DIVb-1:1]}, (Xe[0] ^ ell[0]), PreSqrtX);
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assign DivX = {3'b000, ~NumerZeroE, XPreproc};
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// Sqrt is initialized on step one as R(X-1), so depends on Radix
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if (`RADIX == 2) assign SqrtX = {3'b111, PreSqrtX};
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else assign SqrtX = {2'b11, PreSqrtX, 1'b0};
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@ -122,11 +122,14 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) (
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if(ce1) rd1 <= #1 mem[ra1]; */
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// Write divided into part for bytes and part for extra msbs
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// coverage off
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// when byte write enables are tied high, the last IF is always taken
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if(WIDTH >= 8)
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always @(posedge clk)
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if (ce2 & we2)
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for(i = 0; i < WIDTH/8; i++)
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if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8];
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// coverage on
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if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
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always @(posedge clk)
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@ -71,6 +71,7 @@ module hazard (
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// Similarly, CSR writes and fences flush all subsequent instructions and refetch them in light of the new operating modes and cache/TLB contents
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// Branch misprediction is found in the Execute stage and must flush the next two instructions.
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// However, an active division operation resides in the Execute stage, and when the BP incorrectly mispredicts the divide as a taken branch, the divde must still complete
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// When a WFI is interrupted and causes a trap, it flushes the rest of the pipeline but not the W stage, because the WFI needs to commit
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assign FlushDCause = TrapM | RetM | CSRWriteFenceM | BPWrongE;
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assign FlushECause = TrapM | RetM | CSRWriteFenceM |(BPWrongE & ~(DivBusyE | FDivBusyE));
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assign FlushMCause = TrapM | RetM | CSRWriteFenceM;
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@ -62,7 +62,7 @@ module RASPredictor #(parameter int StackSize = 16 )(
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assign PushE = CallE & ~StallM & ~FlushM;
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assign WrongPredReturnD = (BPReturnWrongD) & ~StallE & ~FlushE;
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assign FlushedReturnDE = (~StallE & FlushE & ReturnD) | (~StallM & FlushM & ReturnE); // flushed return
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assign FlushedReturnDE = (~StallE & FlushE & ReturnD) | (FlushM & ReturnE); // flushed return
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assign RepairD = WrongPredReturnD | FlushedReturnDE ;
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@ -130,7 +130,7 @@ module ifu (
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logic CacheableF; // PMA indicates instruction address is cacheable
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logic SelSpillNextF; // In a spill, stall pipeline and gate local stallF
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logic BusStall; // Bus interface busy with multicycle operation
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logic IFUCacheBusStallD; // EIther I$ or bus busy with multicycle operation
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logic IFUCacheBusStallF; // EIther I$ or bus busy with multicycle operation
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logic GatedStallD; // StallD gated by selected next spill
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// branch predictor signal
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logic [`XLEN-1:0] PC1NextF; // Branch predictor next PCF
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@ -147,7 +147,7 @@ module ifu (
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if(`C_SUPPORTED) begin : Spill
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spill #(`ICACHE_SUPPORTED) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF,
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.InstrUpdateDAF, .IFUCacheBusStallD, .ITLBMissF, .PCSpillNextF, .PCSpillF, .SelSpillNextF, .PostSpillInstrRawF, .CompressedF);
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.InstrUpdateDAF, .IFUCacheBusStallF, .ITLBMissF, .PCSpillNextF, .PCSpillF, .SelSpillNextF, .PostSpillInstrRawF, .CompressedF);
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end else begin : NoSpill
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assign PCSpillNextF = PCNextF;
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assign PCSpillF = PCF;
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@ -288,8 +288,8 @@ module ifu (
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assign InstrRawF = IROMInstrF;
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end
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assign IFUCacheBusStallD = ICacheStallF | BusStall;
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assign IFUStallF = IFUCacheBusStallD | SelSpillNextF;
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assign IFUCacheBusStallF = ICacheStallF | BusStall;
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assign IFUStallF = IFUCacheBusStallF | SelSpillNextF;
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assign GatedStallD = StallD & ~SelSpillNextF;
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flopenl #(32) AlignedInstrRawDFlop(clk, reset | FlushD, ~StallD, PostSpillInstrRawF, nop, InstrRawD);
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@ -40,7 +40,7 @@ module spill #(
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input logic [`XLEN-1:2] PCPlus4F, // PCF + 4
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input logic [`XLEN-1:0] PCNextF, // The next PCF
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input logic [31:0] InstrRawF, // Instruction from the IROM, I$, or bus. Used to check if the instruction if compressed
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input logic IFUCacheBusStallD, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched
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input logic IFUCacheBusStallF, // I$ or bus are stalled. Transition to second fetch of spill after the first is fetched
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input logic ITLBMissF, // ITLB miss, ignore memory request
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input logic InstrUpdateDAF, // Ignore memory request if the hptw support write and a DA page fault occurs (hptw is still active)
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output logic [`XLEN-1:0] PCSpillNextF, // The next PCF for one of the two memory addresses of the spill
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@ -78,7 +78,7 @@ module spill #(
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////////////////////////////////////////////////////////////////////////////////////////////////////
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assign SpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1];
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assign TakeSpillF = SpillF & ~IFUCacheBusStallD & ~(ITLBMissF | (`SVADU_SUPPORTED & InstrUpdateDAF));
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assign TakeSpillF = SpillF & ~IFUCacheBusStallF & ~(ITLBMissF | (`SVADU_SUPPORTED & InstrUpdateDAF));
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always_ff @(posedge clk)
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if (reset | FlushD) CurrState <= #1 STATE_READY;
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@ -88,14 +88,14 @@ module spill #(
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case (CurrState)
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STATE_READY: if (TakeSpillF) NextState = STATE_SPILL;
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else NextState = STATE_READY;
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STATE_SPILL: if(IFUCacheBusStallD | StallD) NextState = STATE_SPILL;
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STATE_SPILL: if(StallD) NextState = STATE_SPILL;
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else NextState = STATE_READY;
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default: NextState = STATE_READY;
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endcase
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end
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assign SelSpillF = (CurrState == STATE_SPILL);
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assign SelSpillNextF = (CurrState == STATE_READY & TakeSpillF) | (CurrState == STATE_SPILL & IFUCacheBusStallD);
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assign SelSpillNextF = (CurrState == STATE_READY & TakeSpillF) | (CurrState == STATE_SPILL & IFUCacheBusStallF);
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assign SpillSaveF = (CurrState == STATE_READY) & TakeSpillF & ~FlushD;
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////////////////////////////////////////////////////////////////////////////////////////////////////
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@ -33,7 +33,9 @@
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`include "wally-config.vh"
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module csrc #(parameter
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MHPMCOUNTERBASE = 12'hB00,
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MTIME = 12'hB01, // this is a memory-mapped register; no such CSR exists, and access should fault
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MHPMCOUNTERHBASE = 12'hB80,
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MTIMEH = 12'hB81, // this is a memory-mapped register; no such CSR exists, and access should fault
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MHPMEVENTBASE = 12'h320,
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HPMCOUNTERBASE = 12'hC00,
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HPMCOUNTERHBASE = 12'hC80,
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@ -152,8 +154,10 @@ module csrc #(parameter
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/* verilator lint_off WIDTH */
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if (CSRAdrM == TIME) CSRCReadValM = MTIME_CLINT; // TIME register is a shadow of the memory-mapped MTIME from the CLINT
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/* verilator lint_on WIDTH */
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else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
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else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
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else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+`COUNTERS & CSRAdrM != MTIME)
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CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
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else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+`COUNTERS)
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CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
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else begin
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CSRCReadValM = 0;
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IllegalCSRCAccessM = 1; // requested CSR doesn't exist
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@ -164,10 +168,14 @@ module csrc #(parameter
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if (CSRAdrM == TIME) CSRCReadValM = MTIME_CLINT[31:0];// TIME register is a shadow of the memory-mapped MTIME from the CLINT
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else if (CSRAdrM == TIMEH) CSRCReadValM = MTIME_CLINT[63:32];
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/* verilator lint_on WIDTH */
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else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
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else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
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else if (CSRAdrM >= MHPMCOUNTERHBASE & CSRAdrM < MHPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
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else if (CSRAdrM >= HPMCOUNTERHBASE & CSRAdrM < HPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
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else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+`COUNTERS & CSRAdrM != MTIME)
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CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
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else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+`COUNTERS)
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CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
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else if (CSRAdrM >= MHPMCOUNTERHBASE & CSRAdrM < MHPMCOUNTERHBASE+`COUNTERS & CSRAdrM != MTIMEH)
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CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
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else if (CSRAdrM >= HPMCOUNTERHBASE & CSRAdrM < HPMCOUNTERHBASE+`COUNTERS)
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CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
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else begin
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CSRCReadValM = 0;
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IllegalCSRCAccessM = 1; // requested CSR doesn't exist
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@ -49,7 +49,9 @@ string tvpaths[] = '{
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"csrwrites",
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"priv",
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"ifu",
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"fpu"
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"fpu",
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"lsu",
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"vm64check"
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};
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string coremark[] = '{
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@ -1052,6 +1054,28 @@ string imperas32f[] = '{
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string arch64f[] = '{
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`RISCVARCHTEST,
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"rv64i_m/F/src/fdiv_b1-01.S",
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"rv64i_m/F/src/fdiv_b20-01.S",
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"rv64i_m/F/src/fdiv_b2-01.S",
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"rv64i_m/F/src/fdiv_b21-01.S",
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"rv64i_m/F/src/fdiv_b3-01.S",
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"rv64i_m/F/src/fdiv_b4-01.S",
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"rv64i_m/F/src/fdiv_b5-01.S",
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"rv64i_m/F/src/fdiv_b6-01.S",
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"rv64i_m/F/src/fdiv_b7-01.S",
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"rv64i_m/F/src/fdiv_b8-01.S",
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"rv64i_m/F/src/fdiv_b9-01.S",
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"rv64i_m/F/src/fsqrt_b1-01.S",
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"rv64i_m/F/src/fsqrt_b20-01.S",
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"rv64i_m/F/src/fsqrt_b2-01.S",
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"rv64i_m/F/src/fsqrt_b3-01.S",
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"rv64i_m/F/src/fsqrt_b4-01.S",
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"rv64i_m/F/src/fsqrt_b5-01.S",
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"rv64i_m/F/src/fsqrt_b7-01.S",
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"rv64i_m/F/src/fsqrt_b8-01.S",
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"rv64i_m/F/src/fsqrt_b9-01.S",
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||||
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"rv64i_m/F/src/fadd_b10-01.S",
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"rv64i_m/F/src/fadd_b1-01.S",
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"rv64i_m/F/src/fadd_b11-01.S",
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@ -1203,6 +1227,28 @@ string imperas32f[] = '{
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string arch64d[] = '{
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`RISCVARCHTEST,
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// for speed
|
||||
"rv64i_m/D/src/fdiv.d_b1-01.S",
|
||||
"rv64i_m/D/src/fdiv.d_b20-01.S",
|
||||
"rv64i_m/D/src/fdiv.d_b2-01.S",
|
||||
"rv64i_m/D/src/fdiv.d_b21-01.S",
|
||||
"rv64i_m/D/src/fdiv.d_b3-01.S",
|
||||
"rv64i_m/D/src/fdiv.d_b4-01.S",
|
||||
"rv64i_m/D/src/fdiv.d_b5-01.S",
|
||||
"rv64i_m/D/src/fdiv.d_b6-01.S",
|
||||
"rv64i_m/D/src/fdiv.d_b7-01.S",
|
||||
"rv64i_m/D/src/fdiv.d_b8-01.S",
|
||||
"rv64i_m/D/src/fdiv.d_b9-01.S",
|
||||
"rv64i_m/D/src/fsqrt.d_b1-01.S",
|
||||
"rv64i_m/D/src/fsqrt.d_b20-01.S",
|
||||
"rv64i_m/D/src/fsqrt.d_b2-01.S",
|
||||
"rv64i_m/D/src/fsqrt.d_b3-01.S",
|
||||
"rv64i_m/D/src/fsqrt.d_b4-01.S",
|
||||
"rv64i_m/D/src/fsqrt.d_b5-01.S",
|
||||
"rv64i_m/D/src/fsqrt.d_b7-01.S",
|
||||
"rv64i_m/D/src/fsqrt.d_b8-01.S",
|
||||
"rv64i_m/D/src/fsqrt.d_b9-01.S",
|
||||
|
||||
"rv64i_m/D/src/fadd.d_b10-01.S",
|
||||
"rv64i_m/D/src/fadd.d_b1-01.S",
|
||||
"rv64i_m/D/src/fadd.d_b11-01.S",
|
||||
|
||||
@ -36,6 +36,7 @@ rvtest_entry_point:
|
||||
csrw mtvec, t0 # Initialize MTVEC to trap_handler
|
||||
csrw mideleg, zero # Don't delegate interrupts
|
||||
csrw medeleg, zero # Don't delegate exceptions
|
||||
li t0, 0x80
|
||||
csrw mie, t0 # Enable machine timer interrupt
|
||||
la t0, topoftrapstack
|
||||
csrw mscratch, t0 # MSCRATCH holds trap stack pointer
|
||||
@ -65,9 +66,8 @@ interrupt: # must be a timer interrupt
|
||||
j trap_return # clean up and return
|
||||
|
||||
exception:
|
||||
csrr t1, mepc # add 4 to MEPC to determine return Address
|
||||
addi t1, t1, 4
|
||||
csrw mepc, t1
|
||||
li t0, 2
|
||||
csrr t1, mcause
|
||||
li t1, 8 # is it an ecall trap?
|
||||
andi t0, t0, 0xFC # if CAUSE = 8, 9, or 11
|
||||
bne t0, t1, trap_return # ignore other exceptions
|
||||
@ -86,6 +86,20 @@ changeprivilege:
|
||||
csrs mstatus, a0 # set mstatus.MPP with desired privilege
|
||||
|
||||
trap_return: # return from trap handler
|
||||
csrr t0, mepc # get address of instruction that caused exception
|
||||
lh t0, 0(t0) # get instruction that caused exception
|
||||
li t1, 3
|
||||
and t0, t0, t1 # mask off upper bits
|
||||
beq t0, t1, instr32 # if lower 2 bits are 11, instruction is uncompresssed
|
||||
li t0, 2 # increment PC by 2 for compressed instruction
|
||||
j updateepc
|
||||
instr32:
|
||||
li t0, 4
|
||||
updateepc:
|
||||
csrr t1, mepc # add 2 or 4 (from t0) to MEPC to determine return Address
|
||||
add t1, t1, t0
|
||||
csrw mepc, t1
|
||||
|
||||
ld t1, -8(tp) # restore t1 and t0
|
||||
ld t0, 0(tp)
|
||||
csrrw tp, mscratch, tp # restore tp
|
||||
|
||||
@ -27,9 +27,11 @@
|
||||
#include "WALLY-init-lib.h"
|
||||
|
||||
main:
|
||||
li t0, -5
|
||||
csrw stimecmp, t0 # initialize so ImperasDV agrees
|
||||
csrrw t0, stimecmp, t0
|
||||
csrrw t0, satp, t0
|
||||
csrrw t0, stvec, t0
|
||||
csrrw t0, sscratch, t0
|
||||
csrrw t0, satp, zero
|
||||
csrrw t0, stvec, zero
|
||||
csrrw t0, sscratch, zero
|
||||
|
||||
j done
|
||||
|
||||
@ -42,6 +42,7 @@ main:
|
||||
clz t1, t0
|
||||
|
||||
# Test forwarding from store conditional
|
||||
mv a0, sp
|
||||
lr.w t0, 0(a0)
|
||||
sc.w t0, a1, 0(a0)
|
||||
addi t0, t0, 1
|
||||
|
||||
@ -43,4 +43,7 @@ main:
|
||||
|
||||
//.hword 0x9C01 //# Illegal compressed instruction with op = 01, instr[15:10] = 100111, and 0's everywhere else
|
||||
|
||||
|
||||
|
||||
|
||||
j done
|
||||
|
||||
@ -33,7 +33,8 @@ main:
|
||||
ecall
|
||||
|
||||
# Test read to stimecmp fails when MCOUNTEREN_TM is not set
|
||||
addi t0, zero, 0
|
||||
li t1, -3
|
||||
csrw stimecmp, t1
|
||||
csrr t0, stimecmp
|
||||
|
||||
|
||||
|
||||
173
tests/coverage/vm64check.S
Normal file
173
tests/coverage/vm64check.S
Normal file
@ -0,0 +1,173 @@
|
||||
///////////////////////////////////////////
|
||||
// vm64check.S
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 7 April 2023
|
||||
//
|
||||
// Purpose: vm64check coverage
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Cover IMMU vm64check block by jumping to illegal virtual addresses
|
||||
// Need a nonstandard trap handler to deal with returns from theses jumps
|
||||
// assign eq_46_38 = &(VAdr[46:38]) | ~|(VAdr[46:38]);
|
||||
// assign eq_63_47 = &(VAdr[63:47]) | ~|(VAdr[63:47]);
|
||||
// assign UpperBitsUnequal = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47;
|
||||
|
||||
.section .text.init
|
||||
.global rvtest_entry_point
|
||||
|
||||
rvtest_entry_point:
|
||||
la sp, topofstack # Initialize stack pointer (not used)
|
||||
|
||||
# Set up interrupts
|
||||
la t0, trap_handler
|
||||
csrw mtvec, t0 # Initialize MTVEC to trap_handler
|
||||
# set up PMP so user and supervisor mode can access full address space
|
||||
csrw pmpcfg0, 0xF # configure PMP0 to TOR RWX
|
||||
li t0, 0xFFFFFFFF
|
||||
csrw pmpaddr0, t0 # configure PMP0 top of range to 0xFFFFFFFF to allow all 32-bit addresses
|
||||
|
||||
# SATP in non-39 mode
|
||||
csrw satp, zero
|
||||
|
||||
// vm64check coverage
|
||||
check1:
|
||||
// check virtual addresses with bits 63:47 and/or 46:38 being equal or unequal
|
||||
li t0, 0x00000001800F0000 # unimplemented memory with upper and lower all zero
|
||||
la ra, check2
|
||||
jalr t0
|
||||
|
||||
check2:
|
||||
li t0, 0xFFFFFFF1800F0000 # unimplemented memory with upper and lower all one
|
||||
la ra, check3
|
||||
jalr t0
|
||||
|
||||
check3:
|
||||
li t0, 0xFFF81001800F0000 # unimplemented memory with upper all one, lower mixed
|
||||
la ra, check4
|
||||
jalr t0
|
||||
|
||||
check4:
|
||||
li t0, 0x03001001800F0000 # unimplemented memory with upper mixed, lower mixed
|
||||
la ra, check5
|
||||
jalr t0
|
||||
|
||||
check5:
|
||||
li t0, 0x00001001800F0000 # unimplemented memory with upper all zero, lower mixed
|
||||
la ra, check11
|
||||
jalr t0
|
||||
|
||||
check11:
|
||||
# SATP in SV39 mode
|
||||
li t0, 0x8000000000000000
|
||||
csrw satp, t0
|
||||
|
||||
// check virtual addresses with bits 63:47 and/or 46:38 being equal or unequal
|
||||
li t0, 0x00000001800F0000 # unimplemented memory with upper and lower all zero
|
||||
la ra, check12
|
||||
jalr t0
|
||||
|
||||
check12:
|
||||
li t0, 0xFFFFFFF1800F0000 # unimplemented memory with upper and lower all one
|
||||
la ra, check13
|
||||
jalr t0
|
||||
|
||||
check13:
|
||||
li t0, 0xFFF81001800F0000 # unimplemented memory with upper all one, lower mixed
|
||||
la ra, check14
|
||||
jalr t0
|
||||
|
||||
check14:
|
||||
li t0, 0x03001001800F0000 # unimplemented memory with upper mixed, lower mixed
|
||||
la ra, check15
|
||||
jalr t0
|
||||
|
||||
check15:
|
||||
li t0, 0x00001001800F0000 # unimplemented memory with upper all zero, lower mixed
|
||||
la ra, check16
|
||||
jalr t0
|
||||
|
||||
check16:
|
||||
|
||||
write_tohost:
|
||||
la t1, tohost
|
||||
li t0, 1 # 1 for success, 3 for failure
|
||||
sd t0, 0(t1) # send success code
|
||||
|
||||
self_loop:
|
||||
j self_loop # wait
|
||||
|
||||
.align 4 # trap handlers must be aligned to multiple of 4
|
||||
trap_handler:
|
||||
csrw mepc, ra # return to address in ra
|
||||
mret
|
||||
|
||||
.section .tohost
|
||||
tohost: # write to HTIF
|
||||
.dword 0
|
||||
fromhost:
|
||||
.dword 0
|
||||
|
||||
|
||||
# Initialize stack with room for 512 bytes
|
||||
.bss
|
||||
.space 512
|
||||
topofstack:
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
j done
|
||||
|
||||
lw t1, 0(t0)
|
||||
li t0, 0xFFFFFFFF80000000
|
||||
lw t1, 0(t0)
|
||||
li t1, 0xFFF8000080000000
|
||||
lw t1, 0(t0)
|
||||
li t1, 0x1000000080000000
|
||||
lw t1, 0(t0)
|
||||
li t1, 0x0000010080000000
|
||||
lw t1, 0(t0)
|
||||
li t0, 0x8000000000000000
|
||||
csrw satp, t0 # SV39 mode
|
||||
li t0, 0x0000000080000000
|
||||
lw t1, 0(t0)
|
||||
li t0, 0xFFFFFFFF80000000
|
||||
lw t1, 0(t0)
|
||||
li t1, 0xFFF8000080000000
|
||||
lw t1, 0(t0)
|
||||
li t1, 0x1000000080000000
|
||||
lw t1, 0(t0)
|
||||
li t1, 0x0000010080000000
|
||||
lw t1, 0(t0)
|
||||
li t0, 0x9000000000000000
|
||||
csrw satp, t0 # SV48 mode
|
||||
li t0, 0x0000000080000000
|
||||
lw t1, 0(t0)
|
||||
li t0, 0xFFFFFFFF80000000
|
||||
lw t1, 0(t0)
|
||||
li t1, 0xFFF8000080000000
|
||||
lw t1, 0(t0)
|
||||
li t1, 0x1000000080000000
|
||||
lw t1, 0(t0)
|
||||
li t1, 0x0000010080000000
|
||||
lw t1, 0(t0)
|
||||
li t0, 0x0000000000000000
|
||||
csrw satp, t0 # disable virtual memory
|
||||
Loading…
Reference in New Issue
Block a user