From f7522ad53c1b91daeef19d95fe3acf8579abb91e Mon Sep 17 00:00:00 2001
From: Harshini Srinath <93847878+harshinisrinath1001@users.noreply.github.com>
Date: Mon, 12 Jun 2023 19:32:04 -0700
Subject: [PATCH] Update csri.sv

Program clean up
---
 src/privileged/csri.sv | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/privileged/csri.sv b/src/privileged/csri.sv
index 7da8985d5..46723a209 100644
--- a/src/privileged/csri.sv
+++ b/src/privileged/csri.sv
@@ -30,7 +30,7 @@
 module csri import cvw::*;  #(parameter cvw_t P) (
   input  logic              clk, reset, 
   input  logic              CSRMWriteM, CSRSWriteM,
-  input  logic [P.XLEN-1:0]  CSRWriteValM,
+  input  logic [P.XLEN-1:0] CSRWriteValM,
   input  logic [11:0]       CSRAdrM,
   input  logic              MExtInt, SExtInt, MTimerInt, STimerInt, MSwInt,
   input  logic [11:0]       MIDELEG_REGW,
@@ -81,7 +81,6 @@ module csri import cvw::*;  #(parameter cvw_t P) (
     else if (WriteMIEM) MIE_REGW <= (CSRWriteValM[11:0] & MIE_WRITE_MASK); // MIE controls M and S fields
     else if (WriteSIEM) MIE_REGW <= (CSRWriteValM[11:0] & 12'h222 & MIDELEG_REGW) | (MIE_REGW & 12'h888); // only S fields
 
-
   assign MIP_REGW = {MExtInt,   1'b0, SExtInt|MIP_REGW_writeable[9],  1'b0,
                      MTimerInt, 1'b0, STIP,                           1'b0,
                      MSwInt,    1'b0, MIP_REGW_writeable[1],          1'b0};