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quick fix to endianness wapping 64 bit reads in 32 bit confgs

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Kip Macsai-Goren 2022-10-11 23:08:02 +00:00
parent b2f71b8255
commit f711eb0bcf
1 changed files with 5 additions and 1 deletions
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pipelined/src/lsu/lsu.sv
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@ -350,9 +350,13 @@ module lsu (
// hart works little-endian internally // hart works little-endian internally
// swap the bytes when read from big-endian memory // swap the bytes when read from big-endian memory
///////////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////////////////////////
if (`BIGENDIAN_SUPPORTED) begin:endian if (`BIGENDIAN_SUPPORTED) begin:endian
logic [`LLEN-1:0] ReadDataWordMuxSwapM; // *** swap the top and bottom XLEN bits based on endianness // Ross doesn't like this
if (`LLEN == 2*`XLEN) assign ReadDataWordMuxSwapM = BigEndianM ? {ReadDataWordMuxM[`XLEN-1:0], ReadDataWordMuxM[`LLEN-1:`XLEN]} : ReadDataWordMuxM;
else assign ReadDataWordMuxSwapM = ReadDataWordMuxM;
endianswap #(`LLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM)); endianswap #(`LLEN) storeswap(.BigEndianM, .a(LittleEndianWriteDataM), .y(LSUWriteDataM));
endianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxM), .y(LittleEndianReadDataWordM)); endianswap #(`LLEN) loadswap(.BigEndianM, .a(ReadDataWordMuxSwapM), .y(LittleEndianReadDataWordM));
end else begin end else begin
assign LSUWriteDataM = LittleEndianWriteDataM; assign LSUWriteDataM = LittleEndianWriteDataM;
assign LittleEndianReadDataWordM = ReadDataWordMuxM; assign LittleEndianReadDataWordM = ReadDataWordMuxM;