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Commented out unused comparators
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@ -30,6 +30,29 @@
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`include "wally-config.vh"
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`include "wally-config.vh"
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// This comparator is best
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module comparator_dc_flip #(parameter WIDTH=64) (
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input logic [WIDTH-1:0] a, b,
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input logic sgnd,
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output logic [1:0] flags);
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logic eq, lt, ltu;
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logic [WIDTH-1:0] af, bf;
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// For signed numbers, flip most significant bit
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assign af = {a[WIDTH-1] ^ sgnd, a[WIDTH-2:0]};
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assign bf = {b[WIDTH-1] ^ sgnd, b[WIDTH-2:0]};
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// behavioral description gives best results
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assign eq = (a == b);
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assign lt = (af < bf);
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assign flags = {eq, lt};
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endmodule
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/*
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Other comparators evaluated
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module donedet #(parameter WIDTH=64) (
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module donedet #(parameter WIDTH=64) (
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input logic [WIDTH-1:0] a, b,
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input logic [WIDTH-1:0] a, b,
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output logic eq);
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output logic eq);
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@ -80,24 +103,6 @@ module comparator #(parameter WIDTH=64) (
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assign flags = {eq, lt, ltu};
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assign flags = {eq, lt, ltu};
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endmodule
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endmodule
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// This comparator is best
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module comparator_dc_flip #(parameter WIDTH=64) (
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input logic [WIDTH-1:0] a, b,
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input logic sgnd,
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output logic [1:0] flags);
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logic eq, lt, ltu;
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logic [WIDTH-1:0] af, bf;
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// For signed numbers, flip most significant bit
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assign af = {a[WIDTH-1] ^ sgnd, a[WIDTH-2:0]};
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assign bf = {b[WIDTH-1] ^ sgnd, b[WIDTH-2:0]};
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// behavioral description gives best results
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assign eq = (a == b);
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assign lt = (af < bf);
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assign flags = {eq, lt};
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endmodule
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module comparator2 #(parameter WIDTH=64) (
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module comparator2 #(parameter WIDTH=64) (
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input logic clk, reset,
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input logic clk, reset,
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@ -106,7 +111,7 @@ module comparator2 #(parameter WIDTH=64) (
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logic eq, lt, ltu;
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logic eq, lt, ltu;
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/* verilator lint_off UNOPTFLAT */
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/* verilator lint_off UNOPTFLAT /
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// prefix implementation
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// prefix implementation
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localparam levels=$clog2(WIDTH);
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localparam levels=$clog2(WIDTH);
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genvar i;
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genvar i;
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@ -133,7 +138,7 @@ module comparator2 #(parameter WIDTH=64) (
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// A < B signed if less than unsigned and msb is not < unsigned, or if A negative and B positive
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// A < B signed if less than unsigned and msb is not < unsigned, or if A negative and B positive
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assign lt2 = ltu2 & ~l[0][WIDTH-1] | a[WIDTH-1] & ~b[WIDTH-1];
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assign lt2 = ltu2 & ~l[0][WIDTH-1] | a[WIDTH-1] & ~b[WIDTH-1];
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assign flags = {eq2, lt2, ltu2};
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assign flags = {eq2, lt2, ltu2};
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/* verilator lint_on UNOPTFLAT */
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/* verilator lint_on UNOPTFLAT /
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endmodule
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endmodule
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@ -143,7 +148,7 @@ module comparator_prefix #(parameter WIDTH=64) (
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logic eq, lt, ltu;
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logic eq, lt, ltu;
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/* verilator lint_off UNOPTFLAT */
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/* verilator lint_off UNOPTFLAT
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// prefix implementation
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// prefix implementation
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localparam levels=$clog2(WIDTH);
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localparam levels=$clog2(WIDTH);
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genvar i;
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genvar i;
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@ -170,7 +175,7 @@ module comparator_prefix #(parameter WIDTH=64) (
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// A < B signed if less than unsigned and msb is not < unsigned, or if A negative and B positive
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// A < B signed if less than unsigned and msb is not < unsigned, or if A negative and B positive
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assign lt2 = ltu2 & ~l[0][WIDTH-1] | a[WIDTH-1] & ~b[WIDTH-1];
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assign lt2 = ltu2 & ~l[0][WIDTH-1] | a[WIDTH-1] & ~b[WIDTH-1];
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assign flags = {eq2, lt2, ltu2};
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assign flags = {eq2, lt2, ltu2};
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/* verilator lint_on UNOPTFLAT */
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/* verilator lint_on UNOPTFLAT /
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endmodule
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endmodule
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@ -317,3 +322,4 @@ module stinecomp64 (FCC, A, B, Sel);
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assign FCC = {LT, EQ};
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assign FCC = {LT, EQ};
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endmodule // comp64
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endmodule // comp64
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*/
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