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Modify register before fpdivsqrt to be synthesizable for FPGAs and better in tune for ASIC clocking

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This commit is contained in:
James E. Stine 2021-10-22 13:41:50 -05:00
parent 7c7c0f538a
commit f6e8e45901
3 changed files with 184 additions and 91 deletions
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9
wally-pipelined/src/fpu/fpdiv_pipe.sv
View File

@ -42,6 +42,7 @@ module fpdiv_pipe (
output logic done,
output logic FDivBusyE,
output logic load_preload,
output logic [63:0] AS_Result,
output logic [4:0] Flags);
@ -137,18 +138,18 @@ module fpdiv_pipe (
.sel_muxa, .sel_muxb, .sel_muxr, .reset, .clk,
.load_rega, .load_regb, .load_regc, .load_regd,
.load_regr, .load_regs, .load_regp,
.P(P1), .op_type(op_type1), .exp_odd(exp_odd1));
.P(P), .op_type(op_type1), .exp_odd(exp_odd1));
// FSM : control divider
fsm_fpdiv_pipe control (.clk, .reset, .start(start), .op_type(op_type1), .P(P1),
fsm_fpdiv_pipe control (.clk, .reset, .start(start), .op_type(op_type1), .P(P),
.done, .load_rega, .load_regb, .load_regc, .load_regd,
.load_regr, .load_regs, .load_regp,
.load_regr, .load_regs, .load_regp, .load_preload,
.sel_muxa, .sel_muxb, .sel_muxr, .divBusy(FDivBusyE));
// Round the mantissa to a 52-bit value, with the leading one
// removed. The rounding units also handles special cases and
// set the exception flags.
rounder_div round1 (.rm, .P(P1), .OvEn(1'b0), .UnEn(1'b0), .exp_diff(expF1),
rounder_div round1 (.rm, .P(P), .OvEn(1'b0), .UnEn(1'b0), .exp_diff(expF1),
.sel_inv(sel_inv1), .Invalid(Invalid1), .SignR(signResult1),
.Float1(op1), .Float2(op2),
.XNaNQ, .YNaNQ, .XZeroQ, .YZeroQ,

26
wally-pipelined/src/fpu/fpu.sv
View File

@ -104,6 +104,7 @@ module fpu (
logic XNormE; // is normal
logic FmtQ;
logic FDivStartQ;
logic FOpCtrlQ;
// result and flag signals
logic [63:0] FDivResM, FDivResW; // divide/squareroot result
@ -128,6 +129,7 @@ module fpu (
logic FDivSqrtDoneE; // is divide done
logic [63:0] DivInput1E, DivInput2E; // inputs to divide/squareroot unit
logic FDivClk; // clock for divide/squareroot unit
logic load_preload; // enable for FF on fpdivsqrt
logic [63:0] AlignedSrcAE; // align SrcA to the floating point format
// DECODE STAGE
@ -194,19 +196,19 @@ module fpu (
.FMAFlgM, .FMAResM);
// fpdivsqrt using Goldschmidt's iteration
floprc #(64) reg_input1 (.d({XSgnE, XExpE, XManE[51:0]}), .q(DivInput1E),
.clear(FDivSqrtDoneE),
.reset(reset), .clk(FDivBusyE));
floprc #(64) reg_input2 (.d({YSgnE, YExpE, YManE[51:0]}), .q(DivInput2E),
.clear(FDivSqrtDoneE),
.reset(reset), .clk(FDivBusyE));
floprc #(7) reg_input3 (.d({XNaNE, YNaNE, XInfE, YInfE, XZeroE, YZeroE, FmtE}),
.q({XNaNQ, YNaNQ, XInfQ, YInfQ, XZeroQ, YZeroQ, FmtQ}),
.clear(FDivSqrtDoneE),
.reset(reset), .clk(FDivBusyE));
fpdiv_pipe fdivsqrt (.op1(DivInput1E), .op2(DivInput2E), .rm(FrmE[1:0]), .op_type(FOpCtrlE[0]),
flopenrc #(64) reg_input1 (.d({XSgnE, XExpE, XManE[51:0]}), .q(DivInput1E),
.clear(FDivSqrtDoneE), .en(load_preload),
.reset(reset), .clk(clk));
flopenrc #(64) reg_input2 (.d({YSgnE, YExpE, YManE[51:0]}), .q(DivInput2E),
.clear(FDivSqrtDoneE), .en(load_preload),
.reset(reset), .clk(clk));
flopenrc #(8) reg_input3 (.d({XNaNE, YNaNE, XInfE, YInfE, XZeroE, YZeroE, FmtE, FOpCtrlE[0]}),
.q({XNaNQ, YNaNQ, XInfQ, YInfQ, XZeroQ, YZeroQ, FmtQ, FOpCtrlQ}),
.clear(FDivSqrtDoneE), .en(load_preload),
.reset(reset), .clk(clk));
fpdiv_pipe fdivsqrt (.op1(DivInput1E), .op2(DivInput2E), .rm(FrmE[1:0]), .op_type(FOpCtrlQ),
.reset, .clk(clk), .start(FDivStartE), .P(~FmtQ), .OvEn(1'b1), .UnEn(1'b1),
.XNaNQ, .YNaNQ, .XInfQ, .YInfQ, .XZeroQ, .YZeroQ,
.XNaNQ, .YNaNQ, .XInfQ, .YInfQ, .XZeroQ, .YZeroQ, .load_preload,
.FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM));
// convert from signle to double and vice versa

96
wally-pipelined/src/fpu/fsm_fpdiv_pipe.sv
View File

@ -29,6 +29,7 @@ module fsm_fpdiv_pipe (
input logic op_type,
input logic P,
output logic done,
output logic load_preload,
output logic load_rega,
output logic load_regb,
output logic load_regc,
@ -52,7 +53,7 @@ module fsm_fpdiv_pipe (
S30, S31, S32, S33, S34, S35, S36, S37, S38, S39,
S40, S41, S42, S43, S44, S45, S46, S47, S48, S49,
S50, S51, S52, S53, S54, S55, S56, S57, S58, S59,
S60, S61, S62, S63, S64, S65} statetype;
S60, S61, S62, S63, S64, S65, S66} statetype;
statetype current_state, next_state;
@ -73,6 +74,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b0;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -89,6 +91,25 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b1;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
load_regd = 1'b0;
load_regr = 1'b0;
load_regs = 1'b0;
load_regp = 1'b0;
sel_muxa = 3'b000;
sel_muxb = 3'b000;
sel_muxr = 1'b0;
next_state = S66;
end
end // case: S0
S66:
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -100,14 +121,14 @@ module fsm_fpdiv_pipe (
sel_muxb = 3'b000;
sel_muxr = 1'b0;
next_state = S65;
end
end
end // if (start==1'b0)
S65:
begin
if (op_type==1'b0 && P==1'b0)
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1;
load_regb = 1'b0;
load_regc = 1'b1;
@ -124,6 +145,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1;
load_regb = 1'b0;
load_regc = 1'b1;
@ -140,6 +162,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -156,6 +179,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -172,6 +196,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b0;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -190,6 +215,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b1;
load_regc = 1'b0;
@ -206,6 +232,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1;
load_regb = 1'b0;
load_regc = 1'b1;
@ -222,6 +249,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b1;
load_regc = 1'b0;
@ -238,6 +266,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1;
load_regb = 1'b0;
load_regc = 1'b1;
@ -254,6 +283,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b1;
load_regc = 1'b0;
@ -270,6 +300,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1;
load_regb = 1'b0;
load_regc = 1'b1;
@ -286,6 +317,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b1;
load_regc = 1'b0;
@ -302,6 +334,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -318,6 +351,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -334,6 +368,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -350,6 +385,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -366,6 +402,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -382,6 +419,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b1;
divBusy = 1'b0;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -398,6 +436,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b0;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -415,6 +454,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -431,6 +471,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1;
load_regb = 1'b0;
load_regc = 1'b1;
@ -447,6 +488,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b1;
load_regc = 1'b0;
@ -463,6 +505,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -479,6 +522,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -495,6 +539,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1;
load_regb = 1'b0;
load_regc = 1'b1;
@ -511,6 +556,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b1;
load_regc = 1'b0;
@ -527,6 +573,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -543,6 +590,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -559,6 +607,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1;
load_regb = 1'b0;
load_regc = 1'b1;
@ -575,6 +624,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b1;
load_regc = 1'b0;
@ -591,6 +641,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -607,6 +658,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -623,6 +675,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1;
load_regb = 1'b0;
load_regc = 1'b1;
@ -639,6 +692,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b1;
load_regc = 1'b0;
@ -655,6 +709,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -671,6 +726,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -687,6 +743,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -703,6 +760,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -719,6 +777,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b1;
divBusy = 1'b0;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -735,6 +794,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b0;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -752,6 +812,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b1;
load_regc = 1'b0;
@ -768,6 +829,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1;
load_regb = 1'b0;
load_regc = 1'b1;
@ -784,6 +846,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b1;
load_regc = 1'b0;
@ -800,6 +863,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1;
load_regb = 1'b0;
load_regc = 1'b1;
@ -816,6 +880,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b1;
load_regc = 1'b0;
@ -832,6 +897,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -848,6 +914,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -864,6 +931,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -880,6 +948,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -896,6 +965,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -912,6 +982,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b1;
divBusy = 1'b0;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -928,6 +999,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b0;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -945,6 +1017,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -961,6 +1034,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1;
load_regb = 1'b0;
load_regc = 1'b1;
@ -977,6 +1051,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b1;
load_regc = 1'b0;
@ -993,6 +1068,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -1009,6 +1085,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -1025,6 +1102,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1;
load_regb = 1'b0;
load_regc = 1'b1;
@ -1041,6 +1119,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b1;
load_regc = 1'b0;
@ -1057,6 +1136,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -1073,6 +1153,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -1089,6 +1170,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b1;
load_regb = 1'b0;
load_regc = 1'b1;
@ -1105,6 +1187,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b1;
load_regc = 1'b0;
@ -1121,6 +1204,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -1137,6 +1221,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -1153,6 +1238,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -1169,6 +1255,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b1;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -1185,6 +1272,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b1;
divBusy = 1'b0;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -1201,6 +1289,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b0;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;
@ -1217,6 +1306,7 @@ module fsm_fpdiv_pipe (
begin
done = 1'b0;
divBusy = 1'b0;
load_preload = 1'b0;
load_rega = 1'b0;
load_regb = 1'b0;
load_regc = 1'b0;