diff --git a/config/shared/config-shared.vh b/config/shared/config-shared.vh index 54a6675ee..48f02b848 100644 --- a/config/shared/config-shared.vh +++ b/config/shared/config-shared.vh @@ -24,6 +24,7 @@ localparam SV48 = 4'd9; localparam A_SUPPORTED = ((MISA >> 0) % 2 == 1); localparam B_SUPPORTED = ((ZBA_SUPPORTED | ZBB_SUPPORTED | ZBC_SUPPORTED | ZBS_SUPPORTED));// not based on MISA localparam C_SUPPORTED = ((MISA >> 2) % 2 == 1); +localparam COMPRESSED_SUPPORTED = C_SUPPORTED | ZCA_SUPPORTED; localparam D_SUPPORTED = ((MISA >> 3) % 2 == 1); localparam E_SUPPORTED = ((MISA >> 4) % 2 == 1); localparam F_SUPPORTED = ((MISA >> 5) % 2 == 1); diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index f3f216062..ee46001e1 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -118,6 +118,7 @@ localparam cvw_t P = '{ A_SUPPORTED : A_SUPPORTED, B_SUPPORTED : B_SUPPORTED, C_SUPPORTED : C_SUPPORTED, + COMPRESSED_SUPPORTED : COMPRESSED_SUPPORTED, D_SUPPORTED : D_SUPPORTED, E_SUPPORTED : E_SUPPORTED, F_SUPPORTED : F_SUPPORTED, diff --git a/src/cvw.sv b/src/cvw.sv index 01e0d6376..f4e0d941d 100644 --- a/src/cvw.sv +++ b/src/cvw.sv @@ -196,6 +196,7 @@ typedef struct packed { logic A_SUPPORTED; logic B_SUPPORTED; logic C_SUPPORTED; + logic COMPRESSED_SUPPORTED; // C or ZCA logic D_SUPPORTED; logic E_SUPPORTED; logic F_SUPPORTED; diff --git a/src/ifu/bpred/icpred.sv b/src/ifu/bpred/icpred.sv index 70136bdaf..e4895d4b7 100644 --- a/src/ifu/bpred/icpred.sv +++ b/src/ifu/bpred/icpred.sv @@ -54,7 +54,7 @@ module icpred import cvw::*; #(parameter cvw_t P, logic cjal, cj, cjr, cjalr, CJumpF, CBranchF; logic NCJumpF, NCBranchF; - if(P.C_SUPPORTED) begin + if(P.COMPRESSED_SUPPORTED) begin logic [4:0] CompressedOpcF; assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]}; assign cjal = CompressedOpcF == 5'h09 & P.XLEN == 32; @@ -70,13 +70,13 @@ module icpred import cvw::*; #(parameter cvw_t P, assign NCJumpF = PostSpillInstrRawF[6:0] == 7'h67 | PostSpillInstrRawF[6:0] == 7'h6F; assign NCBranchF = PostSpillInstrRawF[6:0] == 7'h63; - assign BPBranchF = NCBranchF | (P.C_SUPPORTED & CBranchF); - assign BPJumpF = NCJumpF | (P.C_SUPPORTED & (CJumpF)); + assign BPBranchF = NCBranchF | (P.COMPRESSED_SUPPORTED & CBranchF); + assign BPJumpF = NCJumpF | (P.COMPRESSED_SUPPORTED & (CJumpF)); assign BPReturnF = (NCJumpF & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 & PostSpillInstrRawF[11:7] == 5'b0) | // return must return to ra or r5 - (P.C_SUPPORTED & cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01)); + (P.COMPRESSED_SUPPORTED & cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01)); assign BPCallF = (NCJumpF & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // call(r) must link to ra or x5 - (P.C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01))); + (P.COMPRESSED_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01))); end else begin // This section connects the BTB's instruction class prediction. diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 80d146617..a93b24f9d 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -144,7 +144,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( // Spill Support ///////////////////////////////////////////////////////////////////////////////////////////// - if(P.C_SUPPORTED) begin : Spill + if(P.COMPRESSED_SUPPORTED) begin : Spill spill #(P) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF, .InstrUpdateDAF, .CacheableF, .IFUCacheBusStallF, .ITLBMissF, .PCSpillNextF, .PCSpillF, .SelSpillNextF, .PostSpillInstrRawF, .CompressedF); end else begin : NoSpill @@ -366,7 +366,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( flopenrc #(P.XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD); // expand 16-bit compressed instructions to 32 bits - if (P.C_SUPPORTED | P.ZCA_SUPPORTED) begin + if (P.COMPRESSED_SUPPORTED) begin logic IllegalCompInstrD; decompress #(P) decomp(.InstrRawD, .InstrD, .IllegalCompInstrD); assign IllegalIEUInstrD = IllegalBaseInstrD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr @@ -386,7 +386,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( // only IALIGN=32, the two low bits (mepc[1:0]) are always zero. // Spec 3.1.14 // Traps: Can’t happen. The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4. See 3.1.7 of the privileged spec. - assign BranchMisalignedFaultE = (IEUAdrE[1] & ~P.C_SUPPORTED) & PCSrcE; + assign BranchMisalignedFaultE = (IEUAdrE[1] & ~P.COMPRESSED_SUPPORTED) & PCSrcE; flopenr #(1) InstrMisalignedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM); // Instruction and PC/PCLink pipeline registers diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index b25c3b905..7b590c077 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -203,7 +203,7 @@ module csr import cvw::*; #(parameter cvw_t P) ( assign CSRAdrM = InstrM[31:20]; assign UnalignedNextEPCM = TrapM ? PCM : CSRWriteValM; - assign NextEPCM = P.C_SUPPORTED ? {UnalignedNextEPCM[P.XLEN-1:1], 1'b0} : {UnalignedNextEPCM[P.XLEN-1:2], 2'b00}; // 3.1.15 alignment + assign NextEPCM = P.COMPRESSED_SUPPORTED ? {UnalignedNextEPCM[P.XLEN-1:1], 1'b0} : {UnalignedNextEPCM[P.XLEN-1:2], 2'b00}; // 3.1.15 alignment assign NextCauseM = TrapM ? {InterruptM, CauseM}: {CSRWriteValM[P.XLEN-1], CSRWriteValM[3:0]}; assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM; assign UngatedCSRMWriteM = CSRWriteM & (PrivilegeModeW == P.M_MODE); diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index ad489c208..2d714bf6a 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -94,8 +94,8 @@ module csrm import cvw::*; #(parameter cvw_t P) ( localparam DSCRATCH1 = 12'h7B3; // Constants localparam ZERO = {(P.XLEN){1'b0}}; - // when C is supported, there can't be misaligned instructions - localparam MEDELEG_MASK = P.C_SUPPORTED ? 16'hB3FE : 16'hB3FF; + // when compressed instructions are supported, there can't be misaligned instructions + localparam MEDELEG_MASK = P.COMPRESSED_SUPPORTED ? 16'hB3FE : 16'hB3FF; localparam MIDELEG_MASK = 12'h222; // we choose to not make machine interrupts delegable // There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output index d5a114ab3..e45c4d947 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-01.reference_output @@ -55,7 +55,7 @@ FFFFFFFF # stimecmp readback 8000000b # mcause value from m ext interrupt 00000000 # mtval for mext interrupt (0x0) 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 -0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable) +0000b3fe # medeleg after attempted write of all 1's (only some bits are writeable) 00000222 # mideleg after attempted write of all 1's (only some bits are writeable) # skipping instruction address fault since they're impossible with compressed instrs enabled 00000001 # mcause from an instruction access fault 00000000 # mtval of faulting instruction address (0x0) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output index 575427b04..54d13773a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -48,7 +48,7 @@ 00000009 # scause from S mode ecall 00000000 # stval of ecall (*** defined to be zero for now) 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 -0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable) +0000b3fe # medeleg after attempted write of all 1's (only some bits are writeable) 00000222 # mideleg after attempted write of all 1's (only some bits are writeable) 0000000b # scause from M mode ecall 00000000 # stval of ecall (*** defined to be zero for now) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output index 8529cbe64..9492779df 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-u-01.reference_output @@ -45,7 +45,7 @@ 00000008 # scause from U mode ecall 00000000 # stval of ecall (*** defined to be zero for now) 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 -0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable) +0000b3fe # medeleg after attempted write of all 1's (only some bits are writeable) 00000222 # mideleg after attempted write of all 1's (only some bits are writeable) 0000000b # scause from M mode ecall 00000000 # stval of ecall (*** defined to be zero for now) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output index 5c9b816fb..557341ad4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output @@ -112,7 +112,7 @@ FFFFFFFF # stimecmp low bits 00000000 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0 00000000 -0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable) +0000b3fe # medeleg after attempted write of all 1's (only some bits are writeable) 00000000 00000222 # mideleg after attempted write of all 1's (only some bits are writeable) 00000000 # skipping instruction address fault since they're impossible with compressed instrs enabled diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output index 9f3ddc647..bca764a76 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -98,7 +98,7 @@ 00000000 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 -0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable) +0000b3fe # medeleg after attempted write of all 1's (only some bits are writeable) 00000000 00000222 # mideleg after attempted write of all 1's (only some bits are writeable) 00000000 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output index 36f08113a..1670f68d7 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output @@ -92,7 +92,7 @@ 00000000 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 -0000b3ff # medeleg after attempted write of all 1's (only some bits are writeable) +0000b3fe # medeleg after attempted write of all 1's (only some bits are writeable) 00000000 00000222 # mideleg after attempted write of all 1's (only some bits are writeable) 00000000