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https://github.com/openhwgroup/cvw
synced 2025-02-03 10:15:19 +00:00
fixed bug in testvector extract script
-old script skips first 2 lines in rv32m case, new script only skips first line - prior code skipped every other line in the reference file, so it only generated half the test vectors, with half of them having the wrong answer - prior code also opened test vector file to be written to in "append" mode, and I changed to write mode (so that the script overwrites instead of adding to an existing file)
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@ -1,7 +1,7 @@
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#! /usr/bin/python3
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#! /usr/bin/python3
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# author: Alessandro Maiuolo
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# author: Alessandro Maiuolo, Kevin Kim
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# contact: amaiuolo@g.hmc.edu
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# contact: amaiuolo@g.hmc.edu, kekim@hmc.edu
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# date created: 3-29-2023
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# date created: 3-29-2023
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# extract all arch test vectors
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# extract all arch test vectors
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@ -77,7 +77,7 @@ def create_vectors(my_config):
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rounding_mode = "X"
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rounding_mode = "X"
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flags = "XX"
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flags = "XX"
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# use name to create our new tv
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# use name to create our new tv
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dest_file = open("{}cvw_{}_{}.tv".format(dest_dir, my_config.bits, vector1[:-2]), 'a')
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dest_file = open("{}cvw_{}_{}.tv".format(dest_dir, my_config.bits, vector1[:-2]), 'w')
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# open vectors
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# open vectors
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src_file1 = open(source_dir1 + vector1,'r')
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src_file1 = open(source_dir1 + vector1,'r')
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src_file2 = open(source_dir2 + vector2,'r')
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src_file2 = open(source_dir2 + vector2,'r')
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@ -179,13 +179,56 @@ def create_vectors(my_config):
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else:
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else:
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# print("read false")
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# print("read false")
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reading = False
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reading = False
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elif my_config.letter == "M" and my_config.bits == 32:
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reading = True
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while reading:
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# print("trigger 64M")
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# get answer from Ref...signature
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# answers span two lines and are reversed
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answer = src_file2.readline().strip()
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print(f"Answer: {answer}")
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#print(answer1,answer2)
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if not (answer == "6f5ca309"): # if there is still stuff to read
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# parse through .S file
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detected = False
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done = False
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op1val = "0"
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op2val = "0"
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while not (detected or done):
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# print("det1")
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line = src_file1.readline()
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# print(line)
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if "op1val" in line:
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# print("det2")
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# parse line
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op1val = line.split("op1val")[1].split("x")[1].split(";")[0]
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if "-" in line.split("op1val")[1].split("x")[0]: # neg sign handling
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op1val = twos_comp(my_config.bits, op1val)
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if my_config.op != "fsqrt": # sqrt doesn't have two input vals, unnec here but keeping for later
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op2val = line.split("op2val")[1].split("x")[1].strip()
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if op2val[-1] == ";": op2val = op2val[:-1] # remove ; if it's there
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if "-" in line.split("op2val")[1].split("x")[0]: # neg sign handling
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op2val = twos_comp(my_config.bits, op2val)
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# go to next test in vector
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detected = True
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elif "RVTEST_CODE_END" in line:
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done = True
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# ints don't have flags
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flags = "XX"
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# put it all together
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if not done:
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translation = "{}_{}_{}_{}_{}_{}".format(operation, ext_bits(op1val), ext_bits(op2val), ext_bits(answer.strip()), flags.strip(), rounding_mode)
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dest_file.write(translation + "\n")
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else:
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# print("read false")
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reading = False
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else:
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else:
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while reading:
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while reading:
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# get answer and flags from Ref...signature
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# get answer and flags from Ref...signature
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answer = src_file2.readline()
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answer = src_file2.readline()
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# print(answer)
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print(answer)
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packed = src_file2.readline()[6:]
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packed = src_file2.readline()[6:]
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# print(packed)
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print("Packed: ", packed)
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if len(packed.strip())>0: # if there is still stuff to read
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if len(packed.strip())>0: # if there is still stuff to read
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# print("packed")
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# print("packed")
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# parse through .S file
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# parse through .S file
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@ -229,7 +272,7 @@ def create_vectors(my_config):
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src_file2.close()
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src_file2.close()
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config_list = [
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config_list = [
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Config(32, "M", "div", "div_", 0),
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Config(32, "M", "div", "div-", 0),
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Config(32, "F", "fdiv", "fdiv", 1),
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Config(32, "F", "fdiv", "fdiv", 1),
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Config(32, "F", "fsqrt", "fsqrt", 2),
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Config(32, "F", "fsqrt", "fsqrt", 2),
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Config(32, "M", "rem", "rem-", 3),
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Config(32, "M", "rem", "rem-", 3),
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