From c1e6283201f736c43ae81e69c320ff4e59405f39 Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Tue, 3 Dec 2024 03:54:36 -0800 Subject: [PATCH 1/5] Added another signal for VM Coverage --- testbench/common/wallyTracer.sv | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 51f0d302a..7f7919ee3 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -69,6 +69,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); logic [(P.XLEN-1):0] PTE_iM,PTE_dM,PTE_iW,PTE_dW; logic [(P.PA_BITS-1):0] PAIM,PADM,PAIW,PADW; logic [(P.PPN_BITS-1):0] PPN_iM,PPN_dM,PPN_iW,PPN_dW; + logic [1:0] PageType_iM, PageType_iW, PageType_dM, PageType_dW; logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW; logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW; @@ -121,6 +122,8 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign PTE_dM = testbench.dut.core.lsu.dmmu.dmmu.PTE; assign PPN_iM = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN; assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; + assign PageType_iM = testbench.dut.core.lsu.PageType; + assign PageType_dM = testbench.dut.core.lsu.PageType; logic valid; @@ -359,10 +362,12 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); flopenrc #(P.XLEN) VAdrDWReg (clk, reset, FlushW, ~StallW, VAdrDM, VAdrDW); flopenrc #(P.PA_BITS) PAIWReg (clk, reset, FlushW, ~StallW, PAIM, PAIW); flopenrc #(P.PA_BITS) PADWReg (clk, reset, FlushW, ~StallW, PADM, PADW); - flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, ~StallW, PTE_iM, PTE_iW); - flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, ~StallW, PTE_dM, PTE_dW); + flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, StallW, PTE_iM, PTE_iW); + flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, StallW, PTE_dM, PTE_dW); flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~StallW, PPN_iM, PPN_iW); flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~StallW, PPN_dM, PPN_dW); + flopenrc #(2) PageType_iWReg (clk, reset, FlushW, ~StallW, PageType_iM, PageType_iW); + flopenrc #(2) PageType_dWReg (clk, reset, FlushW, ~StallW, PageType_dM, PageType_dW); flopenrc #(1) ReadAccessWReg (clk, reset, FlushW, ~StallW, ReadAccessM, ReadAccessW); flopenrc #(1) WriteAccessWReg (clk, reset, FlushW, ~StallW, WriteAccessM, WriteAccessW); // *** what is this used for? From 4591d625d52abee228c5a478f94d22f1596a4d0e Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Tue, 3 Dec 2024 03:54:36 -0800 Subject: [PATCH 2/5] Added another signal for VM Coverage --- testbench/common/wallyTracer.sv | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 51f0d302a..7f7919ee3 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -69,6 +69,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); logic [(P.XLEN-1):0] PTE_iM,PTE_dM,PTE_iW,PTE_dW; logic [(P.PA_BITS-1):0] PAIM,PADM,PAIW,PADW; logic [(P.PPN_BITS-1):0] PPN_iM,PPN_dM,PPN_iW,PPN_dW; + logic [1:0] PageType_iM, PageType_iW, PageType_dM, PageType_dW; logic ReadAccessM,WriteAccessM,ReadAccessW,WriteAccessW; logic ExecuteAccessF,ExecuteAccessD,ExecuteAccessE,ExecuteAccessM,ExecuteAccessW; @@ -121,6 +122,8 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign PTE_dM = testbench.dut.core.lsu.dmmu.dmmu.PTE; assign PPN_iM = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN; assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; + assign PageType_iM = testbench.dut.core.lsu.PageType; + assign PageType_dM = testbench.dut.core.lsu.PageType; logic valid; @@ -359,10 +362,12 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); flopenrc #(P.XLEN) VAdrDWReg (clk, reset, FlushW, ~StallW, VAdrDM, VAdrDW); flopenrc #(P.PA_BITS) PAIWReg (clk, reset, FlushW, ~StallW, PAIM, PAIW); flopenrc #(P.PA_BITS) PADWReg (clk, reset, FlushW, ~StallW, PADM, PADW); - flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, ~StallW, PTE_iM, PTE_iW); - flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, ~StallW, PTE_dM, PTE_dW); + flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, StallW, PTE_iM, PTE_iW); + flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, StallW, PTE_dM, PTE_dW); flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~StallW, PPN_iM, PPN_iW); flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~StallW, PPN_dM, PPN_dW); + flopenrc #(2) PageType_iWReg (clk, reset, FlushW, ~StallW, PageType_iM, PageType_iW); + flopenrc #(2) PageType_dWReg (clk, reset, FlushW, ~StallW, PageType_dM, PageType_dW); flopenrc #(1) ReadAccessWReg (clk, reset, FlushW, ~StallW, ReadAccessM, ReadAccessW); flopenrc #(1) WriteAccessWReg (clk, reset, FlushW, ~StallW, WriteAccessM, WriteAccessW); // *** what is this used for? From ffdaca2760c390e15a8827b4c9190203f759f3a0 Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Tue, 3 Dec 2024 04:09:11 -0800 Subject: [PATCH 3/5] Removing debug signals --- testbench/common/wallyTracer.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 7f7919ee3..0e691741c 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -122,8 +122,8 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign PTE_dM = testbench.dut.core.lsu.dmmu.dmmu.PTE; assign PPN_iM = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN; assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; - assign PageType_iM = testbench.dut.core.lsu.PageType; - assign PageType_dM = testbench.dut.core.lsu.PageType; + assign PageType_iM = testbench.dut.core.lsu.dmmu.dmmu.PageTypeWriteVal; + assign PageType_dM = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal; logic valid; @@ -362,8 +362,8 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); flopenrc #(P.XLEN) VAdrDWReg (clk, reset, FlushW, ~StallW, VAdrDM, VAdrDW); flopenrc #(P.PA_BITS) PAIWReg (clk, reset, FlushW, ~StallW, PAIM, PAIW); flopenrc #(P.PA_BITS) PADWReg (clk, reset, FlushW, ~StallW, PADM, PADW); - flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, StallW, PTE_iM, PTE_iW); - flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, StallW, PTE_dM, PTE_dW); + flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, ~StallW, PTE_iM, PTE_iW); + flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, ~StallW, PTE_dM, PTE_dW); flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~StallW, PPN_iM, PPN_iW); flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~StallW, PPN_dM, PPN_dW); flopenrc #(2) PageType_iWReg (clk, reset, FlushW, ~StallW, PageType_iM, PageType_iW); From 54e09df77cdbf5c2a6acf77661f8e211340ed3d6 Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Tue, 3 Dec 2024 04:10:22 -0800 Subject: [PATCH 4/5] Removing debug signals --- testbench/common/wallyTracer.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 0e691741c..fbe5d0163 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -122,8 +122,8 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); assign PTE_dM = testbench.dut.core.lsu.dmmu.dmmu.PTE; assign PPN_iM = testbench.dut.core.ifu.immu.immu.tlb.tlb.PPN; assign PPN_dM = testbench.dut.core.lsu.dmmu.dmmu.tlb.tlb.PPN; - assign PageType_iM = testbench.dut.core.lsu.dmmu.dmmu.PageTypeWriteVal; - assign PageType_dM = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal; + assign PageType_iM = testbench.dut.core.ifu.immu.immu.PageTypeWriteVal; + assign PageType_dM = testbench.dut.core.lsu.dmmu.dmmu.PageTypeWriteVal; logic valid; From c1eab9e77894f8cb8072867cbcd3d5eb61604043 Mon Sep 17 00:00:00 2001 From: Huda-10xe Date: Thu, 5 Dec 2024 06:55:23 -0800 Subject: [PATCH 5/5] Updates to WallyTracer --- testbench/common/wallyTracer.sv | 39 +++++++++++++++++++-------------- 1 file changed, 22 insertions(+), 17 deletions(-) diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 70ed2b159..f74fb3d06 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -360,23 +360,28 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); flopenrc #(1) CSRWriteWReg (clk, reset, FlushW, ~StallW, CSRWriteM, CSRWriteW); //for VM Verification - flopenrc #(P.XLEN) VAdrIWReg (clk, reset, FlushW, ~StallW, VAdrIM, VAdrIW); - flopenrc #(P.XLEN) VAdrDWReg (clk, reset, FlushW, ~StallW, VAdrDM, VAdrDW); - flopenrc #(P.PA_BITS) PAIWReg (clk, reset, FlushW, ~StallW, PAIM, PAIW); - flopenrc #(P.PA_BITS) PADWReg (clk, reset, FlushW, ~StallW, PADM, PADW); - flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, ~GatedStallW, PTE_iM, PTE_iW); - flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, ~GatedStallW, PTE_dM, PTE_dW); - flopenrc #(2) PageType_iWReg (clk, reset, FlushW, ~GatedStallW, PageType_iM, PageType_iW); - flopenrc #(2) PageType_dWReg (clk, reset, FlushW, ~GatedStallW, PageType_dM, PageType_dW); - flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~GatedStallW, PPN_iM, PPN_iW); - flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~GatedStallW, PPN_dM, PPN_dW); - flopenrc #(1) ReadAccessWReg (clk, reset, FlushW, ~GatedStallW, ReadAccessM, ReadAccessW); - flopenrc #(1) WriteAccessWReg (clk, reset, FlushW, ~GatedStallW, WriteAccessM, WriteAccessW); - // *** what is this used for? - flopenrc #(1) ExecuteAccessDReg (clk, reset, FlushE, ~StallD, ExecuteAccessF, ExecuteAccessD); - flopenrc #(1) ExecuteAccessEReg (clk, reset, FlushE, ~StallE, ExecuteAccessD, ExecuteAccessE); - flopenrc #(1) ExecuteAccessMReg (clk, reset, FlushM, ~StallM, ExecuteAccessE, ExecuteAccessM); - flopenrc #(1) ExecuteAccessWReg (clk, reset, FlushW, ~StallW, ExecuteAccessM, ExecuteAccessW); + flopenrc #(P.XLEN) VAdrIWReg (clk, reset, FlushW, ~StallW, VAdrIM, VAdrIW); //Virtual Address for IMMU + flopenrc #(P.XLEN) VAdrDWReg (clk, reset, FlushW, ~StallW, VAdrDM, VAdrDW); //Virtual Address for DMMU + + flopenrc #(P.PA_BITS) PAIWReg (clk, reset, FlushW, ~StallW, PAIM, PAIW); //Physical Address for IMMU + flopenrc #(P.PA_BITS) PADWReg (clk, reset, FlushW, ~StallW, PADM, PADW); //Physical Address for DMMU + + flopenrc #(P.XLEN) PTE_iWReg (clk, reset, FlushW, ~GatedStallW, PTE_iM, PTE_iW); //PTE for IMMU + flopenrc #(P.XLEN) PTE_dWReg (clk, reset, FlushW, ~GatedStallW, PTE_dM, PTE_dW); //PTE for DMMU + + flopenrc #(2) PageType_iWReg (clk, reset, FlushW, ~GatedStallW, PageType_iM, PageType_iW); //Page Type (kilo, mega, giga, tera) from IMMU + flopenrc #(2) PageType_dWReg (clk, reset, FlushW, ~GatedStallW, PageType_dM, PageType_dW); //Page Type (kilo, mega, giga, tera) from DMMU + + flopenrc #(P.PPN_BITS) PPN_iWReg (clk, reset, FlushW, ~GatedStallW, PPN_iM, PPN_iW); //Physical Page Number for IMMU + flopenrc #(P.PPN_BITS) PPN_dWReg (clk, reset, FlushW, ~GatedStallW, PPN_dM, PPN_dW); //Physical Page Number for DMMU + + flopenrc #(1) ReadAccessWReg (clk, reset, FlushW, ~GatedStallW, ReadAccessM, ReadAccessW); //LoadAccess + flopenrc #(1) WriteAccessWReg (clk, reset, FlushW, ~GatedStallW, WriteAccessM, WriteAccessW); //StoreAccess + + flopenrc #(1) ExecuteAccessDReg (clk, reset, FlushE, ~StallD, ExecuteAccessF, ExecuteAccessD); //Instruction Fetch Access + flopenrc #(1) ExecuteAccessEReg (clk, reset, FlushE, ~StallE, ExecuteAccessD, ExecuteAccessE); //Instruction Fetch Access + flopenrc #(1) ExecuteAccessMReg (clk, reset, FlushM, ~StallM, ExecuteAccessE, ExecuteAccessM); //Instruction Fetch Access + flopenrc #(1) ExecuteAccessWReg (clk, reset, FlushW, ~StallW, ExecuteAccessM, ExecuteAccessW); //Instruction Fetch Access // Initially connecting the writeback stage signals, but may need to use M stage // and gate on ~FlushW.