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https://github.com/openhwgroup/cvw
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Added branch outcome logger to testbench
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parent
39731f99f4
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@ -33,6 +33,7 @@
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`include "tests.vh"
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`include "tests.vh"
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`define PrintHPMCounters 0
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`define PrintHPMCounters 0
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`define BPRED_LOGGER 1
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module testbench;
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module testbench;
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parameter DEBUG=0;
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parameter DEBUG=0;
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@ -475,6 +476,19 @@ logic [3:0] dummy;
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release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
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release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
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end
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end
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end
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end
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if (`BPRED_LOGGER) begin
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string direction;
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int file;
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initial
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file = $fopen("branch.log", "w");
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always @(posedge clk) begin
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if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
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direction = dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcM ? "t" : "n";
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$fwrite(file, "%h %s\n", dut.core.PCM, direction);
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end
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end
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end
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end
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end
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// check for hange up.
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// check for hange up.
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