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https://github.com/openhwgroup/cvw
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cleaned up cacheway and sram1rw.sv. also noticed possible bug in sram1rw.sv.
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4
pipelined/src/cache/cacheway.sv
vendored
4
pipelined/src/cache/cacheway.sv
vendored
@ -73,14 +73,14 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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genvar words;
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genvar words;
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for(words = 0; words < LINELEN/`XLEN; words++) begin: word
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for(words = 0; words < LINELEN/`XLEN; words++) begin: word
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sram1rw #(.DEPTH(`XLEN), .WIDTH(NUMLINES))
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sram1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN))
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CacheDataMem(.clk(clk), .Addr(RAdr),
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CacheDataMem(.clk(clk), .Addr(RAdr),
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.ReadData(ReadDataLineWay[(words+1)*`XLEN-1:words*`XLEN] ),
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.ReadData(ReadDataLineWay[(words+1)*`XLEN-1:words*`XLEN] ),
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.WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
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.WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
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.WriteEnable(WriteEnable & WriteWordEnable[words]));
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.WriteEnable(WriteEnable & WriteWordEnable[words]));
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end
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end
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sram1rw #(.DEPTH(TAGLEN), .WIDTH(NUMLINES))
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sram1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN))
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CacheTagMem(.clk(clk),
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CacheTagMem(.clk(clk),
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.Addr(RAdr),
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.Addr(RAdr),
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.ReadData(ReadTag),
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.ReadData(ReadTag),
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82
pipelined/src/cache/sram1rw.sv
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82
pipelined/src/cache/sram1rw.sv
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@ -1,73 +1,61 @@
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/* -----\/----- EXCLUDED -----\/-----
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///////////////////////////////////////////
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// Depth is number of bits in one "word" of the memory, width is number of such words
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// 1 port sram.
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//
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// Written: ross1728@gmail.com May 3, 2021
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// Basic sram with 1 read write port.
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// When clk rises Addr and WriteData are sampled.
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// Following the clk edge read data is output from the sampled Addr.
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// Write
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//
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// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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/-* verilator lint_off ASSIGNDLY *-/
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// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
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module sram1rw #(parameter DEPTH=128, WIDTH=256) (
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module sram1rw #(parameter DEPTH=128, WIDTH=256) (
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input logic clk,
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input logic clk,
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// port 1 is read only
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// port 1 is read only
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input logic [$clog2(WIDTH)-1:0] Addr,
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input logic [$clog2(DEPTH)-1:0] Addr,
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output logic [DEPTH-1:0] ReadData,
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output logic [WIDTH-1:0] ReadData,
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// port 2 is write only
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// port 2 is write only
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input logic [DEPTH-1:0] WriteData,
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input logic [WIDTH-1:0] WriteData,
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input logic WriteEnable
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input logic WriteEnable
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);
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);
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logic [WIDTH-1:0][DEPTH-1:0] StoredData;
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logic [DEPTH-1:0][WIDTH-1:0] StoredData;
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logic [$clog2(WIDTH)-1:0] AddrD;
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logic [$clog2(DEPTH)-1:0] AddrD;
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logic [WIDTH-1:0] WriteDataD;
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always_ff @(posedge clk) begin
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AddrD <= Addr;
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if (WriteEnable) begin
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StoredData[Addr] <= #1 WriteData;
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end
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end
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assign ReadData = StoredData[AddrD];
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endmodule
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/-* verilator lint_on ASSIGNDLY *-/
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-----/\----- EXCLUDED -----/\----- */
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// Depth is number of bits in one "word" of the memory, width is number of such words
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/* verilator lint_off ASSIGNDLY */
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module sram1rw #(parameter DEPTH=128, WIDTH=256) (
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input logic clk,
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// port 1 is read only
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input logic [$clog2(WIDTH)-1:0] Addr,
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output logic [DEPTH-1:0] ReadData,
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// port 2 is write only
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input logic [DEPTH-1:0] WriteData,
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input logic WriteEnable
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);
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logic [WIDTH-1:0][DEPTH-1:0] StoredData;
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logic [$clog2(WIDTH)-1:0] AddrD;
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logic [DEPTH-1:0] WriteDataD;
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logic WriteEnableD;
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logic WriteEnableD;
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always_ff @(posedge clk) begin
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always_ff @(posedge clk) begin
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AddrD <= Addr;
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AddrD <= Addr;
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WriteDataD <= WriteData;
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WriteDataD <= WriteData; /// ****** this is not right. there should not need to be a delay.
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WriteEnableD <= WriteEnable;
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WriteEnableD <= WriteEnable;
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if (WriteEnableD) begin
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if (WriteEnableD) begin
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StoredData[AddrD] <= #1 WriteDataD;
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StoredData[AddrD] <= #1 WriteDataD;
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end
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end
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end
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end
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assign ReadData = StoredData[AddrD];
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assign ReadData = StoredData[AddrD];
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endmodule
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endmodule
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/* verilator lint_on ASSIGNDLY */
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