diff --git a/config/derivlist.txt b/config/derivlist.txt
index 2fac6bcc2..1edd20b7b 100644
--- a/config/derivlist.txt
+++ b/config/derivlist.txt
@@ -1661,6 +1661,7 @@ derive imperas rv64gc
 ICACHE_SUPPORTED    0
 DCACHE_SUPPORTED    0
 VIRTMEM_SUPPORTED   0
+ZICCLSM_SUPPORTED   0
 ZAAMO_SUPPORTED     0
 ZALRSC_SUPPORTED    0
 ZICBOM_SUPPORTED    0
@@ -1669,3 +1670,4 @@ SVPBMT_SUPPORTED    0
 SVNAPOT_SUPPORTED   0
 BOOTROM_BASE        64'h700012340010
 BOOTROM_RANGE       64'h10
+
diff --git a/testbench/common/riscvassertions.sv b/testbench/common/riscvassertions.sv
index 404353909..0872ab1de 100644
--- a/testbench/common/riscvassertions.sv
+++ b/testbench/common/riscvassertions.sv
@@ -66,6 +66,7 @@ module riscvassertions import cvw::*; #(parameter cvw_t P);
     assert ((P.ZCF_SUPPORTED == 0) | ((P.F_SUPPORTED == 1) & (P.XLEN == 32))) else $fatal(1, "ZCF requires F and XLEN == 32");
     assert ((P.ZCD_SUPPORTED == 0) | (P.D_SUPPORTED == 1)) else $fatal(1, "ZCD requires D");
     assert ((P.LLEN == P.XLEN) | (P.DCACHE_SUPPORTED & P.DTIM_SUPPORTED == 0)) else $fatal(1, "LLEN > XLEN (D on RV32 or Q on RV64) requires data cache");
+    assert ((P.ZICCLSM_SUPPORTED == 0) | (P.DCACHE_SUPPORTED == 1)) else $fatal(1, "ZICCLSM requires DCACHE_SUPPORTED");
   end
 
 endmodule