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Check for non-negative W in int sign handling

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This commit is contained in:
David Harris 2022-12-27 06:35:17 -08:00
parent d41b07aa85
commit f5cc23cae9
2 changed files with 6 additions and 5 deletions
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10
pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
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@ -56,7 +56,7 @@ module fdivsqrtpostproc(
logic [`DIVb:0] NormQuotM; logic [`DIVb:0] NormQuotM;
logic [`DIVb+3:0] IntQuotM, IntRemM, NormRemM; logic [`DIVb+3:0] IntQuotM, IntRemM, NormRemM;
logic signed [`DIVb+3:0] PreResultM, PreFPIntDivResultM; logic signed [`DIVb+3:0] PreResultM, PreFPIntDivResultM;
logic [`XLEN-1:0] W64FPIntDivResultM; logic [`XLEN-1:0] SpecialFPIntDivResultM;
////////////////////////// //////////////////////////
// Execute Stage: Detect early termination for an exact result // Execute Stage: Detect early termination for an exact result
@ -113,8 +113,7 @@ module fdivsqrtpostproc(
NormRemM = W; NormRemM = W;
end end
else else
// if (NegStickyM | weq0) begin // *** old code, replaced by the one below in the right stage and more comprehensive if (NegStickyM) begin
if (NegStickyM | WZeroM) begin
NormQuotM = FirstUM; NormQuotM = FirstUM;
NormRemM = -(W + DM); NormRemM = -(W + DM);
end else begin end else begin
@ -166,8 +165,9 @@ module fdivsqrtpostproc(
// division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted // division takes the result from the next cycle, which is shifted to the left one more time so the square root also needs to be shifted
assign PreFPIntDivResultM = $signed(PreResultM >>> NormShiftM); assign PreFPIntDivResultM = $signed(PreResultM >>> NormShiftM);
assign W64FPIntDivResultM = (W64M ? {{(`XLEN-32){PreFPIntDivResultM[31]}}, PreFPIntDivResultM[31:0]} : PreFPIntDivResultM[`XLEN-1:0]); // Sign extending in case of W64 assign SpecialFPIntDivResultM = BZeroM ? (RemOpM ? ForwardedSrcAM : {(`XLEN){1'b1}}) : PreFPIntDivResultM[`XLEN-1:0]; // special cases
assign FPIntDivResultM = BZeroM ? (RemOpM ? ForwardedSrcAM : {(`XLEN){1'b1}}) : W64FPIntDivResultM; // special cases // *** conditional on RV64
assign FPIntDivResultM = (W64M ? {{(`XLEN-32){SpecialFPIntDivResultM[31]}}, SpecialFPIntDivResultM[31:0]} : SpecialFPIntDivResultM[`XLEN-1:0]); // Sign extending in case of W64
assign PreQmM = NegStickyM ? FirstUM : FirstU; // Select U or U-1 depending on negative sticky bit assign PreQmM = NegStickyM ? FirstUM : FirstU; // Select U or U-1 depending on negative sticky bit
assign QmM = SqrtM ? (PreQmM << 1) : PreQmM; assign QmM = SqrtM ? (PreQmM << 1) : PreQmM;

1
pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
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@ -69,6 +69,7 @@ module fdivsqrtpreproc (
// ***can probably merge X LZC with conversion // ***can probably merge X LZC with conversion
// cout the number of leading zeros // cout the number of leading zeros
// *** W64 muxes conditional on RV64
assign AsE = ~Funct3E[0] & (W64E ? ForwardedSrcAE[31] : ForwardedSrcAE[`XLEN-1]); assign AsE = ~Funct3E[0] & (W64E ? ForwardedSrcAE[31] : ForwardedSrcAE[`XLEN-1]);
assign BsE = ~Funct3E[0] & (W64E ? ForwardedSrcBE[31] : ForwardedSrcBE[`XLEN-1]); assign BsE = ~Funct3E[0] & (W64E ? ForwardedSrcBE[31] : ForwardedSrcBE[`XLEN-1]);
assign A64 = W64E ? {{(`XLEN-32){AsE}}, ForwardedSrcAE[31:0]} : ForwardedSrcAE; assign A64 = W64E ? {{(`XLEN-32){AsE}}, ForwardedSrcAE[31:0]} : ForwardedSrcAE;