diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index b9e6ae2a5..761fe5ae1 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -74,7 +74,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( logic ClearValid; logic ClearDirty; logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0]; - logic [NUMWAYS-1:0] WayHit; + logic [NUMWAYS-1:0] WayHit, WayHitSaved, WayHitFinal; logic CacheHit; logic FSMWordWriteEn; logic FSMLineWriteEn; @@ -97,7 +97,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( logic LRUWriteEn; logic SelFlush; logic ResetOrFlushAdr, ResetOrFlushWay; - logic [NUMWAYS-1:0] WayHitSaved, WayHitFinal; logic [NUMWAYS-1:0] SelectedWay; logic [NUMWAYS-1:0] SetValidWay, ClearValidWay, SetDirtyWay, ClearDirtyWay; logic [NUMWAYS-1:0] WriteWordWayEn, WriteLineWayEn; @@ -110,7 +109,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( // and FlushAdr when handling D$ flushes mux3 #(SETLEN) AdrSelMux( .d0(NextAdr[SETTOP-1:OFFSETLEN]), .d1(PAdr[SETTOP-1:OFFSETLEN]), .d2(FlushAdr), - .s({SelFlush, SelAdr}), .y(RAdr)); + .s({SelFlush, SelAdr}), .y(RAdr)); // Array of cache ways, along with victim, hit, dirty, and read merging logic cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) CacheWays[NUMWAYS-1:0]( @@ -130,7 +129,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( or_rows #(NUMWAYS, LINELEN) ReadDataAOMux(.a(ReadDataLineWay), .y(ReadDataLine)); or_rows #(NUMWAYS, TAGLEN) VictimTagAOMux(.a(VictimTagWay), .y(VictimTag)); - // Because of the sram clocked read when the ieu is stalled the read data maybe lost. // There are two ways to resolve. 1. We can replay the read of the sram or we can save // the data. Replay is eaiser but creates a longer critical path. @@ -143,38 +141,34 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path: Write data and address. Muxes between writes from bus and writes from CPU. ///////////////////////////////////////////////////////////////////////////////////////////// - mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}), .d1(CacheMemWriteData), .s(FSMLineWriteEn), .y(CacheWriteData)); mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .d1({VictimTag, PAdr[SETTOP-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}), - .s({SelFlush, SelEvict}), - .y(CacheBusAdr)); + .s({SelFlush, SelEvict}), .y(CacheBusAdr)); ///////////////////////////////////////////////////////////////////////////////////////////// // Flush address and way generation during flush ///////////////////////////////////////////////////////////////////////////////////////////// - + // *** this could be improved. reduce to a single adder of size $clog2(numway+numlines) assign ResetOrFlushAdr = reset | FlushAdrCntRst; - flopenr #(SETLEN) FlushAdrReg(.clk, .reset(ResetOrFlushAdr), - .en(FlushAdrCntEn), .d(FlushAdrP1), .q(FlushAdr)); + flopenr #(SETLEN) FlushAdrReg(.clk, .reset(ResetOrFlushAdr), .en(FlushAdrCntEn), + .d(FlushAdrP1), .q(FlushAdr)); assign FlushAdrP1 = FlushAdr + 1'b1; assign FlushAdrFlag = (FlushAdr == FlushAdrThreshold[SETLEN-1:0]); assign ResetOrFlushWay = reset | FlushWayCntRst; - flopenl #(NUMWAYS) FlushWayReg(.clk, .load(ResetOrFlushWay), - .en(FlushWayCntEn), .val({{NUMWAYS-1{1'b0}}, 1'b1}), - .d(NextFlushWay), .q(FlushWay)); + flopenl #(NUMWAYS) FlushWayReg(.clk, .load(ResetOrFlushWay), .en(FlushWayCntEn), + .val({{NUMWAYS-1{1'b0}}, 1'b1}), .d(NextFlushWay), .q(FlushWay)); assign FlushWayFlag = FlushWay[NUMWAYS-1]; assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]}; ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path: Write Enables ///////////////////////////////////////////////////////////////////////////////////////////// - - // *** change to structural - mux3 #(NUMWAYS) selectwaymux(WayHitFinal, VictimWay, FlushWay, {SelFlush, FSMLineWriteEn}, SelectedWay); + mux3 #(NUMWAYS) selectwaymux(WayHitFinal, VictimWay, FlushWay, + {SelFlush, FSMLineWriteEn}, SelectedWay); assign SetValidWay = FSMLineWriteEn ? SelectedWay : '0; assign ClearValidWay = ClearValid ? SelectedWay : '0; assign SetDirtyWay = FSMWordWriteEn ? SelectedWay : '0; @@ -186,7 +180,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( ///////////////////////////////////////////////////////////////////////////////////////////// // Cache FSM ///////////////////////////////////////////////////////////////////////////////////////////// - cachefsm cachefsm(.clk, .reset, .CacheFetchLine, .CacheWriteLine, .CacheBusAck, .RW, .Atomic, .CPUBusy, .IgnoreRequestTLB, .IgnoreRequestTrapM, .CacheHit, .VictimDirty, .CacheStall, .CacheCommitted, diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 388908c25..820738cab 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -224,9 +224,9 @@ module cachefsm (CurrState == STATE_READY & (RW[1] & CacheHit) & (CPUBusy & `REPLAY)) | (CurrState == STATE_MISS_FETCH_WDV) | - (CurrState == STATE_MISS_FETCH_DONE) | + (CurrState == STATE_MISS_FETCH_DONE) | (CurrState == STATE_MISS_EVICT_DIRTY) | - (CurrState == STATE_MISS_WRITE_CACHE_LINE) | + (CurrState == STATE_MISS_WRITE_CACHE_LINE) | (CurrState == STATE_MISS_READ_WORD) | (CurrState == STATE_MISS_READ_WORD_DELAY & (AMO | (CPUBusy & `REPLAY))) | (CurrState == STATE_MISS_WRITE_WORD) | diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index a5bb52812..c3429eebb 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -59,21 +59,18 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, localparam LOGWPL = $clog2(WORDSPERLINE); localparam LOGXLENBYTES = $clog2(`XLEN/8); - logic [NUMLINES-1:0] ValidBits; - logic [NUMLINES-1:0] DirtyBits; - logic [LINELEN-1:0] ReadDataLine; - logic [TAGLEN-1:0] ReadTag; - logic Valid; - logic Dirty; - logic SelData; - logic SelTag; - - logic [$clog2(NUMLINES)-1:0] RAdrD; - - logic [2**LOGWPL-1:0] MemPAdrDecoded; - logic [LINELEN/`XLEN-1:0] SelectedWriteWordEn; + logic [NUMLINES-1:0] ValidBits; + logic [NUMLINES-1:0] DirtyBits; + logic [LINELEN-1:0] ReadDataLine; + logic [TAGLEN-1:0] ReadTag; + logic Valid; + logic Dirty; + logic SelData; + logic SelTag; + logic [$clog2(NUMLINES)-1:0] RAdrD; + logic [2**LOGWPL-1:0] MemPAdrDecoded; + logic [LINELEN/`XLEN-1:0] SelectedWriteWordEn; - ///////////////////////////////////////////////////////////////////////////////////////////// // Write Enable demux ///////////////////////////////////////////////////////////////////////////////////////////// @@ -118,9 +115,9 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, ///////////////////////////////////////////////////////////////////////////////////////////// always_ff @(posedge clk) begin // Valid bit array, - if (reset | InvalidateAll) ValidBits <= #1 '0; - else if (SetValidWay) ValidBits[RAdr] <= #1 1'b1; - else if (ClearValidWay) ValidBits[RAdr] <= #1 1'b0; + if (reset | InvalidateAll) ValidBits <= #1 '0; + else if (SetValidWay) ValidBits[RAdr] <= #1 1'b1; + else if (ClearValidWay) ValidBits[RAdr] <= #1 1'b0; end flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD); assign Valid = ValidBits[RAdrD]; @@ -132,8 +129,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, // Dirty bits if (DIRTY_BITS) begin:dirty always_ff @(posedge clk) begin - if (reset) DirtyBits <= #1 {NUMLINES{1'b0}}; - else if (SetDirtyWay) DirtyBits[RAdr] <= #1 1'b1; + if (reset) DirtyBits <= #1 {NUMLINES{1'b0}}; + else if (SetDirtyWay) DirtyBits[RAdr] <= #1 1'b1; else if (ClearDirtyWay) DirtyBits[RAdr] <= #1 1'b0; end assign Dirty = DirtyBits[RAdrD];