diff --git a/sim/regression-wally b/sim/regression-wally
index 67159eb1d..7c389be70 100755
--- a/sim/regression-wally
+++ b/sim/regression-wally
@@ -220,48 +220,48 @@ if (nightly):
 
         ### branch predictor simulation
 
-        ["bpred_TWOBIT_6_16_10_0_rv32gc", ["embench"]],
-        ["bpred_TWOBIT_8_16_10_0_rv32gc", ["embench"]],
-        ["bpred_TWOBIT_10_16_10_0_rv32gc", ["embench"]],        
-        ["bpred_TWOBIT_12_16_10_0_rv32gc", ["embench"]],
-        ["bpred_TWOBIT_14_16_10_0_rv32gc", ["embench"]],        
-        ["bpred_TWOBIT_16_16_10_0_rv32gc", ["embench"]],
-        ["bpred_TWOBIT_6_16_10_1_rv32gc", ["embench"]],
-        ["bpred_TWOBIT_8_16_10_1_rv32gc", ["embench"]],
-        ["bpred_TWOBIT_10_16_10_1_rv32gc", ["embench"]],        
-        ["bpred_TWOBIT_12_16_10_1_rv32gc", ["embench"]],
-        ["bpred_TWOBIT_14_16_10_1_rv32gc", ["embench"]],        
-        ["bpred_TWOBIT_16_16_10_1_rv32gc", ["embench"]],
-        ["bpred_GSHARE_10_16_10_0_rv32gc", ["embench"]],
-        ["bpred_GSHARE_10_16_10_1_rv32gc", ["embench"]],
-        ["bpred_GSHARE_10_2_10_0_rv32gc", ["embench"]],
-        ["bpred_GSHARE_10_2_10_1_rv32gc", ["embench"]],
-        ["bpred_GSHARE_10_2_12_0_rv32gc", ["embench"]],
-        ["bpred_GSHARE_10_2_12_1_rv32gc", ["embench"]],
-        ["bpred_GSHARE_10_2_14_0_rv32gc", ["embench"]],
-        ["bpred_GSHARE_10_2_14_1_rv32gc", ["embench"]],
-        ["bpred_GSHARE_10_2_16_0_rv32gc", ["embench"]],
-        ["bpred_GSHARE_10_2_16_1_rv32gc", ["embench"]],
-        ["bpred_GSHARE_10_2_6_0_rv32gc", ["embench"]],
-        ["bpred_GSHARE_10_2_6_1_rv32gc", ["embench"]],
-        ["bpred_GSHARE_10_2_8_0_rv32gc", ["embench"]],
-        ["bpred_GSHARE_10_2_8_1_rv32gc", ["embench"]],
-        ["bpred_GSHARE_10_3_10_0_rv32gc", ["embench"]],
-        ["bpred_GSHARE_10_3_10_1_rv32gc", ["embench"]],
-        ["bpred_GSHARE_10_4_10_0_rv32gc", ["embench"]],
-        ["bpred_GSHARE_10_4_10_1_rv32gc", ["embench"]],
-        ["bpred_GSHARE_10_6_10_0_rv32gc", ["embench"]],
-        ["bpred_GSHARE_10_6_10_1_rv32gc", ["embench"]],
-        ["bpred_GSHARE_12_16_10_0_rv32gc", ["embench"]],
-        ["bpred_GSHARE_12_16_10_1_rv32gc", ["embench"]],
-        ["bpred_GSHARE_14_16_10_0_rv32gc", ["embench"]],
-        ["bpred_GSHARE_14_16_10_1_rv32gc", ["embench"]],
-        ["bpred_GSHARE_16_16_10_0_rv32gc", ["embench"]],
-        ["bpred_GSHARE_16_16_10_1_rv32gc", ["embench"]],
-        ["bpred_GSHARE_6_16_10_0_rv32gc", ["embench"]],
-        ["bpred_GSHARE_6_16_10_1_rv32gc", ["embench"]],
-        ["bpred_GSHARE_8_16_10_0_rv32gc", ["embench"]],
-        ["bpred_GSHARE_8_16_10_1_rv32gc", ["embench"]],
+        ["bpred_TWOBIT_6_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_TWOBIT_8_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_TWOBIT_10_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],        
+        ["bpred_TWOBIT_12_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_TWOBIT_14_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],        
+        ["bpred_TWOBIT_16_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_TWOBIT_6_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_TWOBIT_8_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_TWOBIT_10_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],        
+        ["bpred_TWOBIT_12_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_TWOBIT_14_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],        
+        ["bpred_TWOBIT_16_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_10_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_10_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_10_2_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_10_2_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_10_2_12_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_10_2_12_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_10_2_14_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_10_2_14_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_10_2_16_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_10_2_16_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_10_2_6_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_10_2_6_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_10_2_8_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_10_2_8_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_10_3_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_10_3_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_10_4_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_10_4_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_10_6_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_10_6_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_12_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_12_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_14_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_14_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_16_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_16_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_6_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_6_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_8_16_10_0_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
+        ["bpred_GSHARE_8_16_10_1_rv32gc", ["embench"], "+define+PrintHPMCounters=1"],
 
 #  enable floating-point tests when lint is fixed
 #        ["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma"]],
@@ -280,11 +280,13 @@ if (nightly):
     for test in derivconfigtests:
         config = test[0];
         tests = test[1];
+        if(len(test) >= 3): defines = test[2]
+        else: defines = ""
         for t in tests:
             tc = TestCase(
                     name=t,
                     variant=config,
-                    cmd="vsim > {} -c <<!\ndo wally-batch.do "+config+" "+t+"\n!",
+                    cmd="vsim > {} -c <<!\ndo wally-batch.do "+config+" "+t+" "+defines+"\n!",
                     grepstr="All tests ran without failures")
             configs.append(tc)