From f56b26ec400add075116f44f61c2e8b0f1399d05 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 1 Aug 2022 15:43:48 -0700 Subject: [PATCH] lza cleanup --- pipelined/src/fpu/fma.sv | 5 +++-- pipelined/src/fpu/fmalza.sv | 9 ++++----- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/pipelined/src/fpu/fma.sv b/pipelined/src/fpu/fma.sv index 68a509677..dec492eba 100644 --- a/pipelined/src/fpu/fma.sv +++ b/pipelined/src/fpu/fma.sv @@ -84,8 +84,9 @@ module fma( // /////////////////////////////////////////////////////////////////////////////// fmaadd add(.Am, .Pm, .Ze, .Pe, .Ps, .As, .KillProd, .ZmSticky, .AmInv, .PmKilled, .NegSum, .InvA, .Sm, .Se, .Ss); - - fmalza lza(.A(AmInv), .Pm({PmKilled, 1'b0, InvA&Ps&ZmSticky&KillProd}), .Cin(InvA & ~(ZmSticky & ~KillProd)), .sub(InvA), .SCnt); + + + fmalza lza(.A(AmInv[3*`NF+5:0]), .Pm({PmKilled, 1'b0, InvA&Ps&ZmSticky&KillProd}), .Cin(InvA & ~(ZmSticky & ~KillProd)), .sub(InvA), .SCnt); endmodule diff --git a/pipelined/src/fpu/fmalza.sv b/pipelined/src/fpu/fmalza.sv index c86459edb..d70f0267c 100644 --- a/pipelined/src/fpu/fmalza.sv +++ b/pipelined/src/fpu/fmalza.sv @@ -30,7 +30,7 @@ `include "wally-config.vh" module fmalza( // [Schmookler & Nowka, Leading zero anticipation and detection, IEEE Sym. Computer Arithmetic, 2001] - input logic [3*`NF+6:0] A, // addend + input logic [3*`NF+5:0] A, // addend input logic [2*`NF+3:0] Pm, // product input logic Cin, // carry in input logic sub, @@ -45,12 +45,11 @@ module fmalza( // [Schmookler & Nowka, Leading zero anticipation and detection, assign B = {{(`NF+2){1'b0}}, Pm}; // Zero extend product - assign P = A[WIDTH-2:0]^B[WIDTH-2:0]; - assign G = A[WIDTH-2:0]&B[WIDTH-2:0]; - assign K= ~A[WIDTH-2:0]&~B[WIDTH-2:0]; + assign P = A[WIDTH-2:0]^B; + assign G = A[WIDTH-2:0]&B; + assign K= ~A[WIDTH-2:0]&~B; assign Pp1 = {sub, P[WIDTH-2:1]}; -// assign Pp1 = {A[WIDTH-1], P[WIDTH-2:1]}; assign Gm1 = {G[WIDTH-3:0], Cin}; assign Km1 = {K[WIDTH-3:0], ~Cin};