diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index d1694b8b4..a711b9443 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -85,7 +85,7 @@ module hazard( assign StallECause = (DivBusyE | FDivBusyE) & ~FlushECause; assign StallMCause = WFIStallM & ~FlushMCause; // Need to gate IFUStallF when the equivalent FlushFCause = FlushDCause = 1. - //assign StallWCause = ((IFUStallF & ~FlushDCause) | LSUStallM) & ~FlushWCause; + // assign StallWCause = ((IFUStallF & ~FlushDCause) | LSUStallM) & ~FlushWCause; // Because FlushWCause is a strict subset of FlushDCause, FlushWCause is factored out. assign StallWCause = (IFUStallF & ~FlushDCause) | (LSUStallM & ~FlushWCause);