diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do
index 7721c9b94..a30eb3863 100644
--- a/sim/coverage-exclusions-rv64gc.do
+++ b/sim/coverage-exclusions-rv64gc.do
@@ -234,6 +234,12 @@ coverage exclude -scope /dut/core/ifu -linerange $line-$line -item c 1 -feccondr
 set line [GetLineNum ../src/generic/flop/floprc.sv "reset \\| clear"]
 coverage exclude -scope /dut/core/priv/priv/pmd/wfi/wficountreg -linerange $line-$line -item c 1 -feccondrow 2
 
+# Exclude system reset case in ebu
+set line [GetLineNum ../src/ebu/ebufsmarb.sv "BeatCounter\\("]
+coverage exclude -scope /dut/core/ebu/ebu/ebufsmarb -linerange $line-$line -item e 1 -fecexprrow 1
+set line [GetLineNum ../src/ebu/ebufsmarb.sv "FinalBeatReg\\("]
+coverage exclude -scope /dut/core/ebu/ebu/ebufsmarb -linerange $line-$line -item e 1 -fecexprrow 1
+
 # TLB not recently used never has all RU bits = 1 because it will then clear all to 0
 # This is a blunt instrument; perhaps there is a more graceful exclusion
 coverage exclude -srcfile priorityonehot.sv 
diff --git a/src/lsu/align.sv b/src/lsu/align.sv
index ecc135009..8710b1d6a 100644
--- a/src/lsu/align.sv
+++ b/src/lsu/align.sv
@@ -131,7 +131,7 @@ module align import cvw::*;  #(parameter cvw_t P) (
   assign SelSpillE = (CurrState == STATE_READY & ValidSpillM) | (CurrState == STATE_SPILL & CacheBusHPWTStall) | (CurrState == STATE_STORE_DELAY);
   assign SpillSaveM = (CurrState == STATE_READY) & ValidSpillM & ~FlushM;
   assign SelStoreDelay = (CurrState == STATE_STORE_DELAY);  // *** Can this be merged into the PreLSURWM logic?
-  assign SpillStallM = SelSpillE | CurrState == STATE_STORE_DELAY;
+  assign SpillStallM = SelSpillE;
 
   ////////////////////////////////////////////////////////////////////////////////////////////////////
   // Merge spilled data