diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index 2ea40b933..d70b367dc 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -128,8 +128,8 @@ module ifu (
   /////////////////////////////////////////////////////////////////////////////////////////////
 
   if(`C_SUPPORTED) begin : SpillSupport
-    spillsupport #(`ICACHE) spillsupport(.clk, .reset, .StallF, .Flush(FlushD), .PCF, .PCPlus4F, .PCNextF, .InstrRawF(InstrRawF),
-      .InstrDAPageFaultF, .IFUCacheBusStallD, .ITLBMissF, .PCNextFSpill, .PCFSpill,
+    spillsupport #(`ICACHE) spillsupport(.clk, .reset, .StallF, .Flush(FlushD), .PCF, .PCPlus4F, .PCNextF, .InstrRawF,
+      .IFUCacheBusStallD, .ITLBMissF, .PCNextFSpill, .PCFSpill,
       .SelNextSpillF, .PostSpillInstrRawF, .CompressedF);
   end else begin : NoSpillSupport
     assign PCNextFSpill = PCNextF;
diff --git a/pipelined/src/ifu/spillsupport.sv b/pipelined/src/ifu/spillsupport.sv
index b63a8cd57..4b36d0f61 100644
--- a/pipelined/src/ifu/spillsupport.sv
+++ b/pipelined/src/ifu/spillsupport.sv
@@ -42,7 +42,6 @@ module spillsupport #(parameter CACHE_ENABLED)
    input logic [31:0]       InstrRawF,
    input logic              IFUCacheBusStallD,
    input logic              ITLBMissF, 
-   input logic              InstrDAPageFaultF, 
    output logic [`XLEN-1:0] PCNextFSpill,
    output logic [`XLEN-1:0] PCFSpill,
    output logic             SelNextSpillF,
@@ -68,7 +67,7 @@ module spillsupport #(parameter CACHE_ENABLED)
   
   assign PossibleSpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1];
   assign SpillF = PossibleSpillF & ~FirstHalfCompressedF & ~IFUCacheBusStallD;
-  assign TakeSpillF = SpillF & ~IFUCacheBusStallD & ~(ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF));
+  assign TakeSpillF = SpillF & ~ITLBMissF;
   
   always_ff @(posedge clk)
     if (reset | Flush)    CurrState <= #1 STATE_READY;