From f48b12b089b98974f8d2c3a999ab422a7fa91e4a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 21 Feb 2022 09:31:29 -0600 Subject: [PATCH] Moved mux into lsuvirtmem. --- pipelined/src/lsu/atomic.sv | 6 +++--- pipelined/src/lsu/lsu.sv | 21 ++++++++++----------- pipelined/src/lsu/lsuvirtmen.sv | 3 +++ 3 files changed, 16 insertions(+), 14 deletions(-) diff --git a/pipelined/src/lsu/atomic.sv b/pipelined/src/lsu/atomic.sv index 77db25e1c..1191df350 100644 --- a/pipelined/src/lsu/atomic.sv +++ b/pipelined/src/lsu/atomic.sv @@ -34,7 +34,7 @@ module atomic ( input logic clk, input logic reset, FlushW, CPUBusy, input logic [`XLEN-1:0] ReadDataM, - input logic [`XLEN-1:0] WriteDataM, + input logic [`XLEN-1:0] LSUWriteDataM, input logic [`PA_BITS-1:0] LSUPAdrM, input logic [6:0] LSUFunct7M, input logic [2:0] LSUFunct3M, @@ -49,9 +49,9 @@ module atomic ( logic [`XLEN-1:0] AMOResult; logic MemReadM; - amoalu amoalu(.srca(ReadDataM), .srcb(WriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]), + amoalu amoalu(.srca(ReadDataM), .srcb(LSUWriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]), .result(AMOResult)); - mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, LSUAtomicM[1], FinalAMOWriteDataM); + mux2 #(`XLEN) wdmux(LSUWriteDataM, AMOResult, LSUAtomicM[1], FinalAMOWriteDataM); assign MemReadM = PreLSURWM[1] & ~(IgnoreRequest) & ~DTLBMissM; lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM, .SquashSCW, .LSURWM); diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index ce12e0283..2c49e9c90 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -103,7 +103,8 @@ module lsu ( logic BusCommittedM, DCacheCommittedM; logic LSUBusWriteCrit; logic DataDAPageFaultM; - + logic [`XLEN-1:0] LSUWriteDataM; + flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM); assign IEUAdrExtM = {2'b00, IEUAdrM}; assign LSUStallM = DCacheStallM | InterlockStall | BusStall; @@ -118,8 +119,8 @@ module lsu ( .DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM, .TrapM, .DCacheStallM, .SATP_REGW, .PCF, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW, - .ReadDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, .IEUAdrM, - .IEUAdrExtM, .PTE, .PageType, .PreLSURWM, .LSUAtomicM, .IEUAdrE, + .ReadDataM, .WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, .IEUAdrM, + .IEUAdrExtM, .PTE, .LSUWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM, .IEUAdrE, .LSUAdrE, .PreLSUPAdrM, .CPUBusy, .InterlockStall, .SelHPTW, .IgnoreRequestTLB, .IgnoreRequestTrapM); @@ -129,6 +130,7 @@ module lsu ( assign LSUAdrE = PreLSUAdrE; assign PreLSUAdrE = IEUAdrE[11:0]; assign PreLSUPAdrM = IEUAdrExtM[`PA_BITS-1:0]; assign LSUFunct3M = Funct3M; assign LSUFunct7M = Funct7M; assign LSUAtomicM = AtomicM; + assign LSUWriteDataM = WriteDataM; end // CommittedM tells the CPU's privilege unit the current instruction @@ -176,7 +178,7 @@ module lsu ( // Memory System // Either Data Cache or Data Tightly Integrated Memory or just bus interface ///////////////////////////////////////////////////////////////////////////////////////////// - logic [`XLEN-1:0] FinalAMOWriteDataM, FinalWriteDataM, PostSWWWriteDataM; + logic [`XLEN-1:0] FinalAMOWriteDataM, FinalWriteDataM; logic [`XLEN-1:0] ReadDataWordM; logic [`XLEN-1:0] ReadDataWordMuxM; logic IgnoreRequest; @@ -252,26 +254,23 @@ module lsu ( assign ReadDataWordMaskedM = SelUncachedAdr ? '0 : ReadDataWordM; // AND-gate subwordwrite subwordwrite(.HRDATA(ReadDataWordMaskedM), .HADDRD(LSUPAdrM[2:0]), .HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}), - .HWDATAIN(FinalAMOWriteDataM), .HWDATA(PostSWWWriteDataM)); + .HWDATAIN(FinalAMOWriteDataM), .HWDATA(FinalWriteDataM)); end else - assign PostSWWWriteDataM = FinalAMOWriteDataM; + assign FinalWriteDataM = FinalAMOWriteDataM; subwordread subwordread(.ReadDataWordMuxM, .LSUPAdrM(LSUPAdrM[2:0]), .Funct3M(LSUFunct3M), .ReadDataM); - - assign FinalWriteDataM = SelHPTW ? PTE : PostSWWWriteDataM; - ///////////////////////////////////////////////////////////////////////////////////////////// // Atomic operations ///////////////////////////////////////////////////////////////////////////////////////////// // *** why does this need DTLBMissM? if (`A_SUPPORTED) begin:atomic - atomic atomic(.clk, .reset, .FlushW, .CPUBusy, .ReadDataM, .WriteDataM, .LSUPAdrM, + atomic atomic(.clk, .reset, .FlushW, .CPUBusy, .ReadDataM, .LSUWriteDataM, .LSUPAdrM, .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, .DTLBMissM, .FinalAMOWriteDataM, .SquashSCW, .LSURWM); end else begin:lrsc - assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign FinalAMOWriteDataM = WriteDataM; + assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign FinalAMOWriteDataM = LSUWriteDataM; end endmodule diff --git a/pipelined/src/lsu/lsuvirtmen.sv b/pipelined/src/lsu/lsuvirtmen.sv index 735fc0df5..34c645b51 100644 --- a/pipelined/src/lsu/lsuvirtmen.sv +++ b/pipelined/src/lsu/lsuvirtmen.sv @@ -47,6 +47,7 @@ module lsuvirtmem( input logic [1:0] PrivilegeModeW, input logic [`XLEN-1:0] PCF, input logic [`XLEN-1:0] ReadDataM, + input logic [`XLEN-1:0] WriteDataM, input logic [2:0] Funct3M, output logic [2:0] LSUFunct3M, input logic [6:0] Funct7M, @@ -54,6 +55,7 @@ module lsuvirtmem( input logic [`XLEN-1:0] IEUAdrE, input logic [`XLEN-1:0] IEUAdrM, output logic [`XLEN-1:0] PTE, + output logic [`XLEN-1:0] LSUWriteDataM, output logic [1:0] PageType, output logic [1:0] PreLSURWM, output logic [1:0] LSUAtomicM, @@ -100,6 +102,7 @@ module lsuvirtmem( mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, PreLSUAdrE); mux2 #(12) replaymux(PreLSUAdrE, IEUAdrM[11:0], SelReplayCPURequest, LSUAdrE); // replay cpu request after hptw. mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, PreLSUPAdrM); + mux2 #(`XLEN) lsuwritedatamux(WriteDataM, PTE, SelHPTW, LSUWriteDataM); // always block interrupts when using the hardware page table walker. assign CPUBusy = StallW & ~SelHPTW;