Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts.

This solves the committedM issue.

wally-pipelined/src/cache/dcache.sv

@@ -47,7 +47,8 @@ module dcache
    output logic 	       CommittedM,
 
    // inputs from TLB and PMA/P
-   input logic 		       FaultM,
+   input logic 		       ExceptionM,
+   input logic 		       PendingInterruptM,   
    input logic 		       DTLBMissM,
    input logic 		       CacheableM,
    // ahb side
@@ -409,7 +410,7 @@ module dcache
 	  NextState = STATE_PTW_MISS_FETCH_WDV;
 	end
 	// amo hit
-	else if(|AtomicM & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin
+	else if(|AtomicM & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
 	  NextState = STATE_AMO_UPDATE;
 	  DCacheStall = 1'b1;
 
@@ -417,7 +418,7 @@ module dcache
 	  else NextState = STATE_READY;
 	end
 	// read hit valid cached
-	else if(MemRWM[1] & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin
+	else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
 	  NextState = STATE_READY;
 	  DCacheStall = 1'b0;
 
@@ -425,7 +426,7 @@ module dcache
 	  else NextState = STATE_READY;
 	end
 	// write hit valid cached
-	else if (MemRWM[0] & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin
+	else if (MemRWM[0] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
 	  SelAdrM = 1'b1;
 	  DCacheStall = 1'b0;
 	  SRAMWordWriteEnableM = 1'b1;
@@ -435,27 +436,27 @@ module dcache
 	  else NextState = STATE_READY;
 	end
 	// read or write miss valid cached
-	else if((|MemRWM) & CacheableM & ~FaultM & ~CacheHit & ~DTLBMissM) begin
+	else if((|MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & ~CacheHit & ~DTLBMissM) begin
 	  NextState = STATE_MISS_FETCH_WDV;
 	  CntReset = 1'b1;
 	  DCacheStall = 1'b1;
 	end
 	// uncached write
-	else if(MemRWM[0] & ~CacheableM & ~FaultM & ~DTLBMissM) begin
+	else if(MemRWM[0] & ~CacheableM & ~ExceptionM & ~DTLBMissM) begin
 	  NextState = STATE_UNCACHED_WRITE;
 	  CntReset = 1'b1;
 	  DCacheStall = 1'b1;
 	  AHBWrite = 1'b1;
 	end
 	// uncached read
-	else if(MemRWM[1] & ~CacheableM & ~FaultM & ~DTLBMissM) begin
+	else if(MemRWM[1] & ~CacheableM & ~ExceptionM & ~DTLBMissM) begin
 	  NextState = STATE_UNCACHED_READ;
 	  CntReset = 1'b1;
 	  DCacheStall = 1'b1;
 	  AHBRead = 1'b1;	  
 	end
 	// fault
-	else if(AnyCPUReqM & FaultM & ~DTLBMissM) begin
+	else if(AnyCPUReqM & (ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
 	  NextState = STATE_READY;
 	end
 	else NextState = STATE_READY;

wally-pipelined/src/lsu/lsu.sv

@@ -40,6 +40,8 @@ module lsu
    input logic [2:0] 	       Funct3M,
    input logic [6:0] 	       Funct7M, 
    input logic [1:0] 	       AtomicM,
+   input logic 		       ExceptionM,
+   input logic 		       PendingInterruptM,
    output logic 	       CommittedM, 
    output logic 	       SquashSCW,
    output logic 	       DataMisalignedM,
@@ -319,7 +321,8 @@ module lsu
 		.ReadDataW(ReadDataWfromDCache),
 		.DCacheStall(DCacheStall),
 		.CommittedM(CommittedM),
-		.FaultM(LoadMisalignedFaultM | StoreMisalignedFaultM), // this is wrong needs to be all faults.
+		.ExceptionM(ExceptionM),
+		.PendingInterruptM(PendingInterruptM),		
 		.DTLBMissM(DTLBMissM),
 		.CacheableM(CacheableM), 
 

wally-pipelined/src/privileged/privileged.sv

@@ -64,6 +64,8 @@ module privileged (
   input logic LoadAccessFaultM,
   input logic StoreAccessFaultM,
 
+  output logic 		   ExceptionM,
+  output logic 		   PendingInterruptM,
   output logic		   IllegalFPUInstrE,
   output logic [1:0]       PrivilegeModeW,
   output logic [`XLEN-1:0] SATP_REGW,

wally-pipelined/src/privileged/trap.sv

@@ -44,6 +44,9 @@ module trap (
   input logic 		   InstrValidM, CommittedM,
   output logic 		   NonBusTrapM, TrapM, MTrapM, STrapM, UTrapM, RetM,
   output logic 		   InterruptM,
+  output logic 		   ExceptionM,
+  output logic 		   PendingInterruptM,
+
   output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM
 //  output logic [11:0]     MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW,
 //  input  logic            WriteMIPM, WriteSIPM, WriteUIPM, WriteMIEM, WriteSIEM, WriteUIEM
@@ -59,7 +62,10 @@ module trap (
   assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9
   assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) || STATUS_SIE; // if S ints enabled or lower priv 3.1.9
   assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222));
-  assign InterruptM = (|PendingIntsM) & InstrValidM & ~CommittedM;
+  assign PendingInterruptM = (|PendingIntsM) & InstrValidM;  
+  assign InterruptM = PendingInterruptM & ~CommittedM;
+  assign ExceptionM = BusTrapM | NonBusTrapM;
+  
   // interrupt if any sources are pending
   // & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage)
   // & with ~CommittedM to make sure MEPC isn't chosen so as to rerun the same instr twice

wally-pipelined/src/wally/wallypipelinedhart.sv

@@ -161,6 +161,8 @@ module wallypipelinedhart
   logic 		    InstrAccessFaultF;
   logic [2:0] 		    DCtoAHBSizeM;
   
+  logic 		    ExceptionM;
+  logic 		    PendingInterruptM;
 
   
   ifu ifu(.InstrInF(InstrRData),
@@ -180,6 +182,8 @@ module wallypipelinedhart
 	  .Funct3M(Funct3M),
 	  .Funct7M(InstrM[31:25]),
 	  .AtomicM(AtomicM),    
+	  .ExceptionM(ExceptionM),
+	  .PendingInterruptM(PendingInterruptM),		
 	  .CommittedM(CommittedM),          
 	  .SquashSCW(SquashSCW),            
 	  .DataMisalignedM(DataMisalignedM),