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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts.
This solves the committedM issue.
This commit is contained in:
parent
9b756d6a94
commit
f4295ff097
wally-pipelined/src
17
wally-pipelined/src/cache/dcache.sv
vendored
17
wally-pipelined/src/cache/dcache.sv
vendored
@ -47,7 +47,8 @@ module dcache
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output logic CommittedM,
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output logic CommittedM,
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// inputs from TLB and PMA/P
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// inputs from TLB and PMA/P
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input logic FaultM,
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input logic ExceptionM,
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input logic PendingInterruptM,
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input logic DTLBMissM,
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input logic DTLBMissM,
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input logic CacheableM,
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input logic CacheableM,
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// ahb side
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// ahb side
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@ -409,7 +410,7 @@ module dcache
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NextState = STATE_PTW_MISS_FETCH_WDV;
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NextState = STATE_PTW_MISS_FETCH_WDV;
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end
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end
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// amo hit
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// amo hit
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else if(|AtomicM & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin
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else if(|AtomicM & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
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NextState = STATE_AMO_UPDATE;
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NextState = STATE_AMO_UPDATE;
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DCacheStall = 1'b1;
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DCacheStall = 1'b1;
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@ -417,7 +418,7 @@ module dcache
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else NextState = STATE_READY;
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else NextState = STATE_READY;
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end
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end
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// read hit valid cached
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// read hit valid cached
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else if(MemRWM[1] & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin
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else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
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NextState = STATE_READY;
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NextState = STATE_READY;
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DCacheStall = 1'b0;
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DCacheStall = 1'b0;
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@ -425,7 +426,7 @@ module dcache
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else NextState = STATE_READY;
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else NextState = STATE_READY;
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end
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end
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// write hit valid cached
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// write hit valid cached
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else if (MemRWM[0] & CacheableM & ~FaultM & CacheHit & ~DTLBMissM) begin
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else if (MemRWM[0] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
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SelAdrM = 1'b1;
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SelAdrM = 1'b1;
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DCacheStall = 1'b0;
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DCacheStall = 1'b0;
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SRAMWordWriteEnableM = 1'b1;
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SRAMWordWriteEnableM = 1'b1;
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@ -435,27 +436,27 @@ module dcache
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else NextState = STATE_READY;
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else NextState = STATE_READY;
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end
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end
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// read or write miss valid cached
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// read or write miss valid cached
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else if((|MemRWM) & CacheableM & ~FaultM & ~CacheHit & ~DTLBMissM) begin
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else if((|MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & ~CacheHit & ~DTLBMissM) begin
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NextState = STATE_MISS_FETCH_WDV;
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NextState = STATE_MISS_FETCH_WDV;
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CntReset = 1'b1;
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CntReset = 1'b1;
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DCacheStall = 1'b1;
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DCacheStall = 1'b1;
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end
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end
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// uncached write
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// uncached write
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else if(MemRWM[0] & ~CacheableM & ~FaultM & ~DTLBMissM) begin
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else if(MemRWM[0] & ~CacheableM & ~ExceptionM & ~DTLBMissM) begin
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NextState = STATE_UNCACHED_WRITE;
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NextState = STATE_UNCACHED_WRITE;
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CntReset = 1'b1;
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CntReset = 1'b1;
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DCacheStall = 1'b1;
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DCacheStall = 1'b1;
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AHBWrite = 1'b1;
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AHBWrite = 1'b1;
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end
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end
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// uncached read
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// uncached read
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else if(MemRWM[1] & ~CacheableM & ~FaultM & ~DTLBMissM) begin
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else if(MemRWM[1] & ~CacheableM & ~ExceptionM & ~DTLBMissM) begin
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NextState = STATE_UNCACHED_READ;
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NextState = STATE_UNCACHED_READ;
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CntReset = 1'b1;
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CntReset = 1'b1;
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DCacheStall = 1'b1;
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DCacheStall = 1'b1;
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AHBRead = 1'b1;
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AHBRead = 1'b1;
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end
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end
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// fault
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// fault
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else if(AnyCPUReqM & FaultM & ~DTLBMissM) begin
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else if(AnyCPUReqM & (ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
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NextState = STATE_READY;
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NextState = STATE_READY;
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end
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end
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else NextState = STATE_READY;
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else NextState = STATE_READY;
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@ -40,6 +40,8 @@ module lsu
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input logic [2:0] Funct3M,
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input logic [2:0] Funct3M,
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input logic [6:0] Funct7M,
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input logic [6:0] Funct7M,
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input logic [1:0] AtomicM,
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input logic [1:0] AtomicM,
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input logic ExceptionM,
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input logic PendingInterruptM,
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output logic CommittedM,
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output logic CommittedM,
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output logic SquashSCW,
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output logic SquashSCW,
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output logic DataMisalignedM,
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output logic DataMisalignedM,
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@ -319,7 +321,8 @@ module lsu
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.ReadDataW(ReadDataWfromDCache),
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.ReadDataW(ReadDataWfromDCache),
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.DCacheStall(DCacheStall),
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.DCacheStall(DCacheStall),
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.CommittedM(CommittedM),
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.CommittedM(CommittedM),
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.FaultM(LoadMisalignedFaultM | StoreMisalignedFaultM), // this is wrong needs to be all faults.
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.ExceptionM(ExceptionM),
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.PendingInterruptM(PendingInterruptM),
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.DTLBMissM(DTLBMissM),
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.DTLBMissM(DTLBMissM),
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.CacheableM(CacheableM),
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.CacheableM(CacheableM),
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@ -64,6 +64,8 @@ module privileged (
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input logic LoadAccessFaultM,
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input logic LoadAccessFaultM,
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input logic StoreAccessFaultM,
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input logic StoreAccessFaultM,
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output logic ExceptionM,
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output logic PendingInterruptM,
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output logic IllegalFPUInstrE,
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output logic IllegalFPUInstrE,
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output logic [1:0] PrivilegeModeW,
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output logic [1:0] PrivilegeModeW,
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output logic [`XLEN-1:0] SATP_REGW,
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output logic [`XLEN-1:0] SATP_REGW,
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@ -44,6 +44,9 @@ module trap (
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input logic InstrValidM, CommittedM,
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input logic InstrValidM, CommittedM,
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output logic NonBusTrapM, TrapM, MTrapM, STrapM, UTrapM, RetM,
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output logic NonBusTrapM, TrapM, MTrapM, STrapM, UTrapM, RetM,
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output logic InterruptM,
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output logic InterruptM,
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output logic ExceptionM,
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output logic PendingInterruptM,
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output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM
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output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM
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// output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW,
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// output logic [11:0] MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW,
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// input logic WriteMIPM, WriteSIPM, WriteUIPM, WriteMIEM, WriteSIEM, WriteUIEM
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// input logic WriteMIPM, WriteSIPM, WriteUIPM, WriteMIEM, WriteSIEM, WriteUIEM
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@ -59,7 +62,10 @@ module trap (
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assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9
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assign MIntGlobalEnM = (PrivilegeModeW != `M_MODE) || STATUS_MIE; // if M ints enabled or lower priv 3.1.9
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assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) || STATUS_SIE; // if S ints enabled or lower priv 3.1.9
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assign SIntGlobalEnM = (PrivilegeModeW == `U_MODE) || STATUS_SIE; // if S ints enabled or lower priv 3.1.9
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assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222));
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assign PendingIntsM = ((MIP_REGW & MIE_REGW) & ({12{MIntGlobalEnM}} & 12'h888)) | ((SIP_REGW & SIE_REGW) & ({12{SIntGlobalEnM}} & 12'h222));
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assign InterruptM = (|PendingIntsM) & InstrValidM & ~CommittedM;
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assign PendingInterruptM = (|PendingIntsM) & InstrValidM;
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assign InterruptM = PendingInterruptM & ~CommittedM;
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assign ExceptionM = BusTrapM | NonBusTrapM;
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// interrupt if any sources are pending
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// interrupt if any sources are pending
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// & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage)
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// & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage)
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// & with ~CommittedM to make sure MEPC isn't chosen so as to rerun the same instr twice
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// & with ~CommittedM to make sure MEPC isn't chosen so as to rerun the same instr twice
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@ -161,6 +161,8 @@ module wallypipelinedhart
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logic InstrAccessFaultF;
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logic InstrAccessFaultF;
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logic [2:0] DCtoAHBSizeM;
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logic [2:0] DCtoAHBSizeM;
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logic ExceptionM;
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logic PendingInterruptM;
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ifu ifu(.InstrInF(InstrRData),
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ifu ifu(.InstrInF(InstrRData),
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@ -180,6 +182,8 @@ module wallypipelinedhart
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.Funct3M(Funct3M),
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.Funct3M(Funct3M),
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.Funct7M(InstrM[31:25]),
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.Funct7M(InstrM[31:25]),
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.AtomicM(AtomicM),
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.AtomicM(AtomicM),
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.ExceptionM(ExceptionM),
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.PendingInterruptM(PendingInterruptM),
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.CommittedM(CommittedM),
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.CommittedM(CommittedM),
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.SquashSCW(SquashSCW),
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.SquashSCW(SquashSCW),
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.DataMisalignedM(DataMisalignedM),
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.DataMisalignedM(DataMisalignedM),
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