From 4db17cde2fbcedbf779a26e88c3cf3e59d27cbf4 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 8 Mar 2023 17:11:27 -0600 Subject: [PATCH 1/2] Updated testbench to record coremark performance counters. Added comment about mtval probably not being correct for compressed instructions. --- sim/wave.do | 9 ++++----- src/privileged/csr.sv | 2 +- testbench/testbench.sv | 11 +++++++++++ 3 files changed, 16 insertions(+), 6 deletions(-) diff --git a/sim/wave.do b/sim/wave.do index fd95f6f17..5aa5deb0a 100644 --- a/sim/wave.do +++ b/sim/wave.do @@ -366,11 +366,9 @@ add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VI add wave -noupdate -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/NextPageType add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PageType add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ValidNonLeafPTE -add wave -noupdate -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM add wave -noupdate -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF @@ -467,7 +465,6 @@ add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/d add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/IFUCacheBusStallD add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/ITLBMissF add wave -noupdate -group ifu -group Spill -expand -group takespill /testbench/dut/core/ifu/Spill/spill/TakeSpillF -add wave -noupdate -group ifu -group Spill /testbench/dut/core/ifu/SelNextSpillF add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST add wave -noupdate -group ifu -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS @@ -635,8 +632,10 @@ add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/DCacheMis add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/InstrValidNotFlushedM add wave -noupdate /testbench/clk add wave -noupdate /testbench/HPMCSample/InitialHPMCOUNTERH +add wave -noupdate /testbench/HPMCSample/EndSample +add wave -noupdate /testbench/HPMCSample/StartSample TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {49231900 ns} 0} {{Cursor 5} {394987 ns} 1} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {23 ns} 0} {{Cursor 5} {394987 ns} 1} quietly wave cursor active 4 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -652,4 +651,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {49231842 ns} {49231960 ns} +WaveRestoreZoom {0 ns} {52 ns} diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index d97be53f6..0764e6c69 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -133,7 +133,7 @@ module csr #(parameter if (InterruptM) NextFaultMtvalM = 0; else case (CauseM) 12, 1, 3: NextFaultMtvalM = PCM; // Instruction page/access faults, breakpoint - 2: NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM}; // Illegal instruction fault + 2: NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM}; // Illegal instruction fault // *** this should probably set to the uncompressed instruction 0, 4, 6, 13, 15, 5, 7: NextFaultMtvalM = IEUAdrM; // Instruction misaligned, Load/Store Misaligned/page/access faults default: NextFaultMtvalM = 0; // Ecall, interrupts endcase diff --git a/testbench/testbench.sv b/testbench/testbench.sv index c4581fa8b..b0af190a9 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -447,6 +447,17 @@ logic [3:0] dummy; flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed); assign EndSample = EndSampleFirst & ~ EndSampleDelayed; + end else if(TEST == "coremark") begin + // embench runs warmup then runs start_trigger + // embench end with stop_trigger. + assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time"; + flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed); + assign StartSample = StartSampleFirst & ~ StartSampleDelayed; + + assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time"; + flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed); + assign EndSample = EndSampleFirst & ~ EndSampleDelayed; + end else begin // default start condiction is reset // default end condiction is end of test (DCacheFlushDone) From 0233130d9cc8d3c5df60a3d4ca17a5edee33fe43 Mon Sep 17 00:00:00 2001 From: eroom1966 Date: Fri, 10 Mar 2023 14:09:22 +0000 Subject: [PATCH 2/2] Enhancements to support the PMA ranges --- sim/imperas.ic | 50 +++++++++++++++++++++------------- sim/wally-imperas.do | 2 ++ testbench/testbench_imperas.sv | 27 ++++-------------- 3 files changed, 38 insertions(+), 41 deletions(-) diff --git a/sim/imperas.ic b/sim/imperas.ic index 8b4ef2d45..6a34466f0 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -1,42 +1,54 @@ #--showoverrides -#--help --helpall +#--showcommands ---override cpu/show_c_prefix=T +# Core settings --override cpu/unaligned=F --override cpu/ignore_non_leaf_DAU=1 --override cpu/wfi_is_nop=T +--override cpu/mimpid=0x100 -# this should be 16 not 0 +# THIS NEEDS FIXING to 16 --override cpu/PMP_registers=0 +# PMA Settings +# 'r': read access allowed +# 'w': write access allowed +# 'x': execute access allowed +# 'a': aligned access required +# 'A': atomic instructions NOT allowed (actually USER1 privilege needed) +# 'P': push/pop instructions NOT allowed (actually USER2 privilege needed) +# '1': 1-byte accesses allowed +# '2': 2-byte accesses allowed +# '4': 4-byte accesses allowed +# '8': 8-byte accesses allowed +# '-', space: ignored (use for input string formatting). +# +# SV39 Memory 0x0000000000 0x7FFFFFFFFF +# +--callcommand refRoot/cpu/setPMA -lo 0x0000000000 -hi 0x7FFFFFFFFF -attributes " ------ ---- "; # INITIAL +--callcommand refRoot/cpu/setPMA -lo 0x0000001000 -hi 0x0000001FFF -attributes " r-x-A- 1248 "; # BOOTROM +--callcommand refRoot/cpu/setPMA -lo 0x0000012100 -hi 0x000001211F -attributes " rw--A- --48 "; # SDC +--callcommand refRoot/cpu/setPMA -lo 0x0002000000 -hi 0x000200FFFF -attributes " rw--A- 1248 "; # CLINT +--callcommand refRoot/cpu/setPMA -lo 0x000C000000 -hi 0x000FFFFFFF -attributes " rw--A- --4- "; # PLIC +--callcommand refRoot/cpu/setPMA -lo 0x0010000000 -hi 0x0010000007 -attributes " rw--A- 1--- "; # UART0 error - 0x10000000 - 0x100000FF +--callcommand refRoot/cpu/setPMA -lo 0x0010060000 -hi 0x00100600FF -attributes " rw--A- --4- "; # GPIO error - 0x10006000 - 0x100060FF +--callcommand refRoot/cpu/setPMA -lo 0x0080000000 -hi 0x008FFFFFFF -attributes " rwx--- 1248 "; # UNCORE_RAM + # Enable the Imperas instruction coverage #-extlib refRoot/cpu/cv=imperas.com/intercept/riscvInstructionCoverage/1.0 #-override refRoot/cpu/cv/cover=basic #-override refRoot/cpu/cv/extensions=RV32I # Add Imperas simulator application instruction tracing ---trace ---tracechange ---traceshowicount ---tracemode ---tracemem ASX ---monitornetschange +--override cpu/show_c_prefix=T +--trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange # Exceptions and pagetables debug --override cpu/debugflags=6 -# Turn on verbose output for Imperas simulator +# Turn on verbose output for Imperas simulator and Model --verbose - -# Turn on verbose output for RISCV model --override cpu/verbose=1 # Store simulator output to logfile --output imperas.log - - -# ignore settings of bits DAU for non leaf page table walks ---override cpu/ignore_non_leaf_DAU=1 - -# mimpid = 0x100 ---override cpu/mimpid=0x100 diff --git a/sim/wally-imperas.do b/sim/wally-imperas.do index 985739cb4..2de97be20 100644 --- a/sim/wally-imperas.do +++ b/sim/wally-imperas.do @@ -24,6 +24,7 @@ vlib work # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals # *** modelsim won't take `PA_BITS, but will take other defines for the lengths of DTIM_RANGE and IROM_LEN. For now just live with the warnings. + vlog +incdir+../config/$1 \ +incdir+../config/shared \ +define+USE_IMPERAS_DV \ @@ -42,6 +43,7 @@ vlog +incdir+../config/$1 \ ../src/*/*/*.sv \ -suppress 2583 \ -suppress 7063 + vopt +acc work.testbench -G DEBUG=1 -o workopt vsim workopt +nowarn3829 -fatal 7 \ -sv_lib $env(IMPERAS_HOME)/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model \ diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv index f5ad63bcd..27bd12467 100644 --- a/testbench/testbench_imperas.sv +++ b/testbench/testbench_imperas.sv @@ -138,11 +138,6 @@ module testbench; .CMP_CSR (1) ) idv_trace2api(rvvi); - int PRIV_RWX = RVVI_MEMORY_PRIVILEGE_READ | RVVI_MEMORY_PRIVILEGE_WRITE | RVVI_MEMORY_PRIVILEGE_EXEC; - int PRIV_RW = RVVI_MEMORY_PRIVILEGE_READ | RVVI_MEMORY_PRIVILEGE_WRITE; - int PRIV_RX = RVVI_MEMORY_PRIVILEGE_READ | RVVI_MEMORY_PRIVILEGE_EXEC; - int PRIV_X = RVVI_MEMORY_PRIVILEGE_EXEC; - initial begin MAX_ERRS = 3; @@ -173,37 +168,25 @@ module testbench; void'(rvviRefCsrSetVolatile(0, 32'h344)); // MIP void'(rvviRefCsrSetVolatile(0, 32'h144)); // SIP -/* - // Memory lo, hi, priv (RVVI_MEMORY_PRIVILEGE_{READ,WRITE,EXEC}) - void'(rvviRefMemorySetPrivilege(56'h0, 56'h7fffffffff, 0)); - if (`BOOTROM_SUPPORTED) - void'(rvviRefMemorySetPrivilege(`BOOTROM_BASE, (`BOOTROM_BASE + `BOOTROM_RANGE), PRIV_RX)); - if (`UNCORE_RAM_SUPPORTED) - void'(rvviRefMemorySetPrivilege(`UNCORE_RAM_BASE, (`UNCORE_RAM_BASE + `UNCORE_RAM_RANGE), PRIV_RWX)); - if (`EXT_MEM_SUPPORTED) - void'(rvviRefMemorySetPrivilege(`EXT_MEM_BASE, (`EXT_MEM_BASE + `EXT_MEM_RANGE), PRIV_RWX)); - + // Privileges for PMA are set in the imperas.ic + // volatile (IO) regions are defined here + // only real ROM/RAM areas are BOOTROM and UNCORE_RAM if (`CLINT_SUPPORTED) begin - void'(rvviRefMemorySetPrivilege(`CLINT_BASE, (`CLINT_BASE + `CLINT_RANGE), PRIV_RW)); void'(rvviRefMemorySetVolatile(`CLINT_BASE, (`CLINT_BASE + `CLINT_RANGE))); end if (`GPIO_SUPPORTED) begin - void'(rvviRefMemorySetPrivilege(`GPIO_BASE, (`GPIO_BASE + `GPIO_RANGE), PRIV_RW)); void'(rvviRefMemorySetVolatile(`GPIO_BASE, (`GPIO_BASE + `GPIO_RANGE))); end if (`UART_SUPPORTED) begin - void'(rvviRefMemorySetPrivilege(`UART_BASE, (`UART_BASE + `UART_RANGE), PRIV_RW)); - void'(rvviRefMemorySetVolatile(`UART_BASE, (`UART_BASE + `UART_RANGE))); + //void'(rvviRefMemorySetVolatile(`UART_BASE, (`UART_BASE + `UART_RANGE))); + void'(rvviRefMemorySetVolatile(`UART_BASE, (`UART_BASE + 7))); // BUG end if (`PLIC_SUPPORTED) begin - void'(rvviRefMemorySetPrivilege(`PLIC_BASE, (`PLIC_BASE + `PLIC_RANGE), PRIV_RW)); void'(rvviRefMemorySetVolatile(`PLIC_BASE, (`PLIC_BASE + `PLIC_RANGE))); end if (`SDC_SUPPORTED) begin - void'(rvviRefMemorySetPrivilege(`SDC_BASE, (`SDC_BASE + `SDC_RANGE), PRIV_RW)); void'(rvviRefMemorySetVolatile(`SDC_BASE, (`SDC_BASE + `SDC_RANGE))); end -*/ if(`XLEN==32) begin void'(rvviRefCsrSetVolatile(0, 32'hC80)); // CYCLEH