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Merge branch 'openhwgroup:main' into main

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Matthew-Otto 2024-06-12 22:43:10 -05:00 committed by GitHub
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10 changed files with 98 additions and 83 deletions
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2
bin/derivgen.pl
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@ -90,7 +90,7 @@ foreach my $key (@derivnames) {
my $datestring = localtime(); my $datestring = localtime();
my %hit = (); my %hit = ();
print $fh "// Config $key automatically derived from $basederiv{$key} on $datestring usubg derivgen.pl\n"; print $fh "// Config $key automatically derived from $basederiv{$key} on $datestring using derivgen.pl\n";
foreach my $line (<$unmod>) { foreach my $line (<$unmod>) {
foreach my $entry (@{$derivs{$key}}) { foreach my $entry (@{$derivs{$key}}) {
my @ent = @{$entry}; my @ent = @{$entry};

30
bin/regression-wally
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@ -99,6 +99,29 @@ derivconfigtests = [
["zaamo_rv32gc", ["arch32i", "arch32a_amo"]], ["zaamo_rv32gc", ["arch32i", "arch32a_amo"]],
["zalrsc_rv32gc", ["arch32i", "wally32a_lrsc"]], ["zalrsc_rv32gc", ["arch32i", "wally32a_lrsc"]],
# Bit manipulation and crypto variants
["zba_rv32gc", ["arch32i", "arch32zba"]],
["zbb_rv32gc", ["arch32i", "arch32zbb"]],
["zbc_rv32gc", ["arch32i", "arch32zbc"]],
["zbs_rv32gc", ["arch32i", "arch32zbs"]],
["zbkb_rv32gc", ["arch32i", "arch32zbkb"]],
["zbkc_rv32gc", ["arch32i", "arch32zbkc"]],
["zbkx_rv32gc", ["arch32i", "arch32zbkx"]],
["zkne_rv32gc", ["arch32i", "arch32zkne"]],
["zknd_rv32gc", ["arch32i", "arch32zknd"]],
["zknh_rv32gc", ["arch32i", "arch32zknh"]],
["zba_rv64gc", ["arch64i", "arch64zba"]],
["zbb_rv64gc", ["arch64i", "arch64zbb"]],
["zbc_rv64gc", ["arch64i", "arch64zbc"]],
["zbs_rv64gc", ["arch64i", "arch64zbs"]],
["zbkb_rv64gc", ["arch64i", "arch64zbkb"]],
["zbkc_rv64gc", ["arch64i", "arch64zbkc"]],
["zbkx_rv64gc", ["arch64i", "arch64zbkx"]],
["zkne_rv64gc", ["arch64i", "arch64zkne"]],
["zknd_rv64gc", ["arch64i", "arch64zknd"]],
["zknh_rv64gc", ["arch64i", "arch64zknh"]],
### add misaligned tests ### add misaligned tests
# fp/int divider permutations # fp/int divider permutations
@ -325,7 +348,8 @@ else:
# run derivative configurations in nightly regression # run derivative configurations in nightly regression
if (nightly): if (nightly):
addTests(tests_buildrootboot, defaultsim) # addTests(tests_buildrootboot, defaultsim)
addTests(tests_buildrootshort, defaultsim)
addTests(derivconfigtests, defaultsim) addTests(derivconfigtests, defaultsim)
else: else:
addTests(tests_buildrootshort, defaultsim) addTests(tests_buildrootshort, defaultsim)
@ -389,7 +413,7 @@ if (testfloat or nightly): # for nightly, run testfloat along with othres
tc = TestCase( tc = TestCase(
name=test, name=test,
variant=config, variant=config,
cmd="wsim --tb testbench_fp --sim questa " + config + " " + test + " > " + sim_log, cmd="wsim --tb testbench_fp " + config + " " + test + " > " + sim_log,
grepstr="All Tests completed with 0 errors", grepstr="All Tests completed with 0 errors",
grepfile = WALLY + "/sim/questa/logs/"+config+"_"+test+".log") grepfile = WALLY + "/sim/questa/logs/"+config+"_"+test+".log")
configs.append(tc) configs.append(tc)
@ -415,7 +439,7 @@ def main():
elif '--nightly' in sys.argv: elif '--nightly' in sys.argv:
TIMEOUT_DUR = 60*1440 # 1 day TIMEOUT_DUR = 60*1440 # 1 day
elif '--testfloat' in sys.argv: elif '--testfloat' in sys.argv:
TIMEOUT_DUR = 5*60 # seconds TIMEOUT_DUR = 30*60 # seconds
else: else:
TIMEOUT_DUR = 10*60 # seconds TIMEOUT_DUR = 10*60 # seconds

6
config/derivlist.txt
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@ -296,9 +296,6 @@ RAS_SIZE 32'd6
deriv bpred_GSHARE_10_10_10_1_rv32gc rv32gc deriv bpred_GSHARE_10_10_10_1_rv32gc rv32gc
RAS_SIZE 32'd10 RAS_SIZE 32'd10
deriv bpred_GSHARE_10_16_10_1_rv32gc rv32gc
RAS_SIZE 32'd16
deriv bpred_GSHARE_10_16_6_1_rv32gc rv32gc deriv bpred_GSHARE_10_16_6_1_rv32gc rv32gc
BTB_SIZE 32'd6 BTB_SIZE 32'd6
@ -365,9 +362,6 @@ INSTR_CLASS_PRED 0
deriv bpred_GSHARE_10_10_10_0_rv32gc bpred_GSHARE_10_10_10_1_rv32gc deriv bpred_GSHARE_10_10_10_0_rv32gc bpred_GSHARE_10_10_10_1_rv32gc
INSTR_CLASS_PRED 0 INSTR_CLASS_PRED 0
deriv bpred_GSHARE_10_16_10_0_rv32gc bpred_GSHARE_10_16_10_1_rv32gc
INSTR_CLASS_PRED 0
deriv bpred_GSHARE_10_16_6_0_rv32gc bpred_GSHARE_10_16_6_1_rv32gc deriv bpred_GSHARE_10_16_6_0_rv32gc bpred_GSHARE_10_16_6_1_rv32gc
INSTR_CLASS_PRED 0 INSTR_CLASS_PRED 0

2
src/fpu/fpu.sv
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@ -309,7 +309,7 @@ module fpu import cvw::*; #(parameter cvw_t P) (
// fround // fround
fround #(P) fround(.X(XE), .Xs(XsE), .Xe(XeE), .Xm(XmE), fround #(P) fround(.X(XE), .Xs(XsE), .Xe(XeE), .Xm(XmE),
.XNaN(XNaNE), .XSNaN(XSNaNE), .XZero(XZeroE), .Fmt(FmtE), .Frm(FrmE), .Nf(NfE), .XNaN(XNaNE), .XSNaN(XSNaNE), .Fmt(FmtE), .Frm(FrmE), .Nf(NfE),
.ZfaFRoundNX(ZfaFRoundNXE), .ZfaFRoundNX(ZfaFRoundNXE),
.FRound(FRoundE), .FRoundNV(FRoundNVE), .FRoundNX(FRoundNXE)); .FRound(FRoundE), .FRoundNV(FRoundNVE), .FRoundNX(FRoundNXE));

23
src/fpu/fround.sv
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@ -34,7 +34,6 @@ module fround import cvw::*; #(parameter cvw_t P) (
input logic [P.NF:0] Xm, // input's fraction with leading integer bit (U1.NF) input logic [P.NF:0] Xm, // input's fraction with leading integer bit (U1.NF)
input logic XNaN, // X is NaN input logic XNaN, // X is NaN
input logic XSNaN, // X is Signalling NaN input logic XSNaN, // X is Signalling NaN
input logic XZero, // X is Zero
input logic [P.FMTBITS-1:0] Fmt, // the input's precision (11=quad 01=double 00=single 10=half) input logic [P.FMTBITS-1:0] Fmt, // the input's precision (11=quad 01=double 00=single 10=half)
input logic [2:0] Frm, // rounding mode input logic [2:0] Frm, // rounding mode
input logic [P.LOGFLEN-1:0] Nf, // Number of fractional bits in selected format input logic [P.LOGFLEN-1:0] Nf, // Number of fractional bits in selected format
@ -44,10 +43,10 @@ module fround import cvw::*; #(parameter cvw_t P) (
output logic FRoundNX // fround inexact output logic FRoundNX // fround inexact
); );
logic [P.NE-1:0] E, Xep1, EminusNf; logic [P.NE-1:0] E, Xep1;
logic [P.NF:0] IMask, Tmasknonneg, Tmaskneg, Tmask, HotE, HotEP1, Trunc, Rnd; logic [P.NF:0] IMask, Tmasknonneg, Tmaskneg, Tmask, HotE, HotEP1, Trunc, Rnd;
logic [P.FLEN-1:0] W, PackedW; logic [P.FLEN-1:0] W, PackedW;
logic Elt0, Eeqm1, Lnonneg, Lp, Rnonneg, Rp, Tp, RoundUp, Two, EgeNf, Exact; logic Elt0, Eeqm1, Lnonneg, Lp, Rnonneg, Rp, Tp, RoundUp, Two, EgeNf;
// Unbiased exponent // Unbiased exponent
assign E = Xe - P.BIAS[P.NE-1:0]; assign E = Xe - P.BIAS[P.NE-1:0];
@ -78,7 +77,7 @@ module fround import cvw::*; #(parameter cvw_t P) (
assign Eeqm1 = ($signed(E) == -1); assign Eeqm1 = ($signed(E) == -1);
// Logic for nonnegative mask and rounding bits // Logic for nonnegative mask and rounding bits
assign IMask = {1'b1, {P.NF{1'b0}}} >>> E; assign IMask = {1'b1, {P.NF{1'b0}}} >>> E; /// if E > Nf, this produces all 0s instead of all 1s. Hence exact handling is needed below.
assign Tmasknonneg = ~IMask >>> 1'b1; assign Tmasknonneg = ~IMask >>> 1'b1;
assign HotE = IMask & ~(IMask << 1'b1); assign HotE = IMask & ~(IMask << 1'b1);
assign HotEP1 = HotE >> 1'b1; assign HotEP1 = HotE >> 1'b1;
@ -100,7 +99,7 @@ module fround import cvw::*; #(parameter cvw_t P) (
// if (X is NaN) // if (X is NaN)
// W = Canonical NaN // W = Canonical NaN
// Invalid = (X is signaling NaN) // Invalid = (X is signaling NaN)
// else if (E >= Nf or X is +/- 0) // else if (E >= Nf)
// W = X // is exact; this also handles infinity // W = X // is exact; this also handles infinity
// else // else
// RoundUp = RoundingLogic(Xs, L', R', T', rm) // Table 16.4 // RoundUp = RoundingLogic(Xs, L', R', T', rm) // Table 16.4
@ -117,11 +116,9 @@ module fround import cvw::*; #(parameter cvw_t P) (
/////////////////////////// ///////////////////////////
// Exact logic // Exact logic
/* verilator lint_off WIDTH */ // verilator lint_off WIDTHEXPAND
assign EminusNf = E - Nf; assign EgeNf = (E >= Nf) & Xe[P.NE-1]; // Check if E >= Nf. Also check that Xe is positive to avoid wraparound problems
/* verilator lint_on WIDTH */ // verilator lint_on WIDTHEXPAND
assign EgeNf = ~EminusNf[P.NE-1] & (~E[P.NE-1] | E[P.NE-2:0] == '0); // E >= Nf if MSB of E-Nf is 0 and E was positive
assign Exact = (EgeNf | XZero) & ~XNaN; // result will be exact; no need to round
// Rounding logic: determine whether to round up in magnitude // Rounding logic: determine whether to round up in magnitude
always_comb begin always_comb begin
@ -136,6 +133,7 @@ module fround import cvw::*; #(parameter cvw_t P) (
// If result is not exact, select output in unpacked FLEN format initially // If result is not exact, select output in unpacked FLEN format initially
if (XNaN) W = {1'b0, {P.NE{1'b1}}, 1'b1, {(P.NF-1){1'b0}}}; // Canonical NaN if (XNaN) W = {1'b0, {P.NE{1'b1}}, 1'b1, {(P.NF-1){1'b0}}}; // Canonical NaN
else if (EgeNf) W = {Xs, Xe, Xm[P.NF-1:0]}; // Exact, no rounding needed
else if (Elt0) // 0 <= |X| < 1 rounds to 0 or 1 else if (Elt0) // 0 <= |X| < 1 rounds to 0 or 1
if (RoundUp) W = {Xs, P.BIAS[P.NE-1:0], {P.NF{1'b0}}}; // round to +/- 1 if (RoundUp) W = {Xs, P.BIAS[P.NE-1:0], {P.NF{1'b0}}}; // round to +/- 1
else W = {Xs, {(P.FLEN-1){1'b0}}}; // round to +/- 0 else W = {Xs, {(P.FLEN-1){1'b0}}}; // round to +/- 0
@ -146,11 +144,10 @@ module fround import cvw::*; #(parameter cvw_t P) (
end end
end end
packoutput #(P) packoutput(W, Fmt, PackedW); // pack and NaN-box based on selected format. packoutput #(P) packoutput(W, Fmt, FRound); // pack and NaN-box based on selected format.
mux2 #(P.FLEN) resultmux(PackedW, X, Exact, FRound);
// Flags // Flags
assign FRoundNV = XSNaN; // invalid if input is signaling NaN assign FRoundNV = XSNaN; // invalid if input is signaling NaN
assign FRoundNX = ZfaFRoundNX & ~(XNaN | Exact) & (Rp | Tp); // Inexact if Round or Sticky bit set for FRoundNX instruction assign FRoundNX = ZfaFRoundNX & ~EgeNf & (Rp | Tp); // Inexact if Round or Sticky bit set for FRoundNX instruction
endmodule endmodule

4
src/fpu/postproc/divshiftcalc.sv
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@ -28,10 +28,8 @@
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module divshiftcalc import cvw::*; #(parameter cvw_t P) ( module divshiftcalc import cvw::*; #(parameter cvw_t P) (
input logic [P.DIVb:0] DivUm, // divsqrt significand
input logic [P.NE+1:0] DivUe, // divsqrt exponent input logic [P.NE+1:0] DivUe, // divsqrt exponent
output logic [P.LOGNORMSHIFTSZ-1:0] DivShiftAmt, // divsqrt shift amount output logic [P.LOGNORMSHIFTSZ-1:0] DivShiftAmt, // divsqrt shift amount
output logic [P.NORMSHIFTSZ-1:0] DivShiftIn, // divsqrt shift input
output logic DivResSubnorm, // is the divsqrt result subnormal output logic DivResSubnorm, // is the divsqrt result subnormal
output logic DivSubnormShiftPos // is the subnormal shift amount positive output logic DivSubnormShiftPos // is the subnormal shift amount positive
); );
@ -68,6 +66,4 @@ module divshiftcalc import cvw::*; #(parameter cvw_t P) (
assign DivSubnormShiftAmt = DivSubnormShiftPos ? DivSubnormShift[P.LOGNORMSHIFTSZ-1:0] : '0; assign DivSubnormShiftAmt = DivSubnormShiftPos ? DivSubnormShift[P.LOGNORMSHIFTSZ-1:0] : '0;
assign DivShiftAmt = DivResSubnorm ? DivSubnormShiftAmt : NormShift; assign DivShiftAmt = DivResSubnorm ? DivSubnormShiftAmt : NormShift;
// pre-shift the divider result for normalization
assign DivShiftIn = {{P.NF{1'b0}}, DivUm, {P.NORMSHIFTSZ-P.DIVb-1-P.NF{1'b0}}};
endmodule endmodule

28
src/fpu/postproc/fmashiftcalc.sv
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@ -35,8 +35,7 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) (
output logic [P.NE+1:0] NormSumExp, // exponent of the normalized sum not taking into account Subnormal or zero results output logic [P.NE+1:0] NormSumExp, // exponent of the normalized sum not taking into account Subnormal or zero results
output logic FmaSZero, // is the sum zero output logic FmaSZero, // is the sum zero
output logic FmaPreResultSubnorm, // is the result subnormal - calculated before LZA corection output logic FmaPreResultSubnorm, // is the result subnormal - calculated before LZA corection
output logic [$clog2(P.FMALEN+1)-1:0] FmaShiftAmt, // normalization shift count output logic [$clog2(P.FMALEN+1)-1:0] FmaShiftAmt // normalization shift count
output logic [P.FMALEN+1:0] FmaShiftIn
); );
logic [P.NE+1:0] PreNormSumExp; // the exponent of the normalized sum with the P.FLEN bias logic [P.NE+1:0] PreNormSumExp; // the exponent of the normalized sum with the P.FLEN bias
logic [P.NE+1:0] BiasCorr; // correction for bias logic [P.NE+1:0] BiasCorr; // correction for bias
@ -54,6 +53,7 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) (
//convert the sum's exponent into the proper precision //convert the sum's exponent into the proper precision
if (P.FPSIZES == 1) begin if (P.FPSIZES == 1) begin
assign NormSumExp = PreNormSumExp; assign NormSumExp = PreNormSumExp;
assign BiasCorr = '0;
end else if (P.FPSIZES == 2) begin end else if (P.FPSIZES == 2) begin
assign BiasCorr = Fmt ? (P.NE+2)'(0) : (P.NE+2)'(P.BIAS1-P.BIAS); assign BiasCorr = Fmt ? (P.NE+2)'(0) : (P.NE+2)'(P.BIAS1-P.BIAS);
assign NormSumExp = PreNormSumExp+BiasCorr; assign NormSumExp = PreNormSumExp+BiasCorr;
@ -79,19 +79,19 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) (
assign NormSumExp = PreNormSumExp+BiasCorr; assign NormSumExp = PreNormSumExp+BiasCorr;
end end
// determine if the result is subnormal: (NormSumExp <= 0) & (NormSumExp >= -FracLen) & ~FmaSZero // determine if the result is subnormal: (NormSumExp <= 0) & (NormSumExp >= -FracLen)
if (P.FPSIZES == 1) begin if (P.FPSIZES == 1) begin
logic Sum0LEZ, Sum0GEFL; logic Sum0LEZ, Sum0GEFL;
assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp; assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1)); // changed from -2 dh 4/3/24 for issue 655 assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1)); // changed from -2 dh 4/3/24 for issue 655
assign FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL & ~FmaSZero; assign FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL;
end else if (P.FPSIZES == 2) begin end else if (P.FPSIZES == 2) begin
logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL; logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL;
assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp; assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1)); // changed from -2 dh 4/3/24 for issue 655 assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1)); // changed from -2 dh 4/3/24 for issue 655
assign Sum1LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.BIAS1)); assign Sum1LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.BIAS1));
assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF1-1+P.BIAS-P.BIAS1)) | ~|PreNormSumExp; assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF1-1+P.BIAS-P.BIAS1)) | ~|PreNormSumExp;
assign FmaPreResultSubnorm = (Fmt ? Sum0LEZ : Sum1LEZ) & (Fmt ? Sum0GEFL : Sum1GEFL) & ~FmaSZero; assign FmaPreResultSubnorm = (Fmt ? Sum0LEZ : Sum1LEZ) & (Fmt ? Sum0GEFL : Sum1GEFL);
end else if (P.FPSIZES == 3) begin end else if (P.FPSIZES == 3) begin
logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL; logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL;
assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp; assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
@ -102,9 +102,9 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) (
assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF2-1+P.BIAS-P.BIAS2)) | ~|PreNormSumExp; assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF2-1+P.BIAS-P.BIAS2)) | ~|PreNormSumExp;
always_comb begin always_comb begin
case (Fmt) case (Fmt)
P.FMT: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL; // & ~FmaSZero; // checking sum is not zero is harmless but turns out to be unnecessary P.FMT: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL;
P.FMT1: FmaPreResultSubnorm = Sum1LEZ & Sum1GEFL; // & ~FmaSZero; P.FMT1: FmaPreResultSubnorm = Sum1LEZ & Sum1GEFL;
P.FMT2: FmaPreResultSubnorm = Sum2LEZ & Sum2GEFL; // & ~FmaSZero; P.FMT2: FmaPreResultSubnorm = Sum2LEZ & Sum2GEFL;
default: FmaPreResultSubnorm = 1'bx; default: FmaPreResultSubnorm = 1'bx;
endcase endcase
end end
@ -120,17 +120,15 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) (
assign Sum3GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.H_NF-1+P.BIAS-P.H_BIAS)) | ~|PreNormSumExp; assign Sum3GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.H_NF-1+P.BIAS-P.H_BIAS)) | ~|PreNormSumExp;
always_comb begin always_comb begin
case (Fmt) case (Fmt)
2'h3: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL & ~FmaSZero; 2'h3: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL;
2'h1: FmaPreResultSubnorm = Sum1LEZ & Sum1GEFL & ~FmaSZero; 2'h1: FmaPreResultSubnorm = Sum1LEZ & Sum1GEFL;
2'h0: FmaPreResultSubnorm = Sum2LEZ & Sum2GEFL & ~FmaSZero; 2'h0: FmaPreResultSubnorm = Sum2LEZ & Sum2GEFL;
2'h2: FmaPreResultSubnorm = Sum3LEZ & Sum3GEFL & ~FmaSZero; 2'h2: FmaPreResultSubnorm = Sum3LEZ & Sum3GEFL;
endcase endcase
end end
end end
// set and calculate the shift input and amount // set and calculate the shift input and amount
// - shift once if killing a product and the result is subnormal // - shift once if killing a product and the result is subnormal
assign FmaShiftIn = {2'b0, FmaSm}; assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(P.FMALEN-1)-1:0]+($clog2(P.FMALEN-1))'(P.NF+3)+BiasCorr[$clog2(P.FMALEN-1)-1:0]: FmaSCnt+1;
if (P.FPSIZES == 1) assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(P.FMALEN-1)-1:0]+($clog2(P.FMALEN-1))'(P.NF+3): FmaSCnt+1;
else assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(P.FMALEN-1)-1:0]+($clog2(P.FMALEN-1))'(P.NF+3)+BiasCorr[$clog2(P.FMALEN-1)-1:0]: FmaSCnt+1;
endmodule endmodule

12
src/fpu/postproc/postprocess.sv
View File

@ -86,13 +86,11 @@ module postprocess import cvw::*; #(parameter cvw_t P) (
// fma signals // fma signals
logic [P.NE+1:0] FmaMe; // exponent of the normalized sum logic [P.NE+1:0] FmaMe; // exponent of the normalized sum
logic FmaSZero; // is the sum zero logic FmaSZero; // is the sum zero
logic [P.FMALEN+1:0] FmaShiftIn; // fma shift input
logic [P.NE+1:0] NormSumExp; // exponent of the normalized sum not taking into account Subnormal or zero results logic [P.NE+1:0] NormSumExp; // exponent of the normalized sum not taking into account Subnormal or zero results
logic FmaPreResultSubnorm; // is the result subnormal - calculated before LZA corection logic FmaPreResultSubnorm; // is the result subnormal - calculated before LZA corection
logic [$clog2(P.FMALEN+1)-1:0] FmaShiftAmt; // normalization shift amount for fma logic [$clog2(P.FMALEN+1)-1:0] FmaShiftAmt; // normalization shift amount for fma
// division signals // division signals
logic [P.LOGNORMSHIFTSZ-1:0] DivShiftAmt; // divsqrt shif amount logic [P.LOGNORMSHIFTSZ-1:0] DivShiftAmt; // divsqrt shif amount
logic [P.NORMSHIFTSZ-1:0] DivShiftIn; // divsqrt shift input
logic [P.NE+1:0] Ue; // divsqrt corrected exponent after corretion shift logic [P.NE+1:0] Ue; // divsqrt corrected exponent after corretion shift
logic DivByZero; // divide by zero flag logic DivByZero; // divide by zero flag
logic DivResSubnorm; // is the divsqrt result subnormal logic DivResSubnorm; // is the divsqrt result subnormal
@ -145,17 +143,17 @@ module postprocess import cvw::*; #(parameter cvw_t P) (
cvtshiftcalc #(P) cvtshiftcalc(.ToInt, .CvtCe, .CvtResSubnormUf, .Xm, .CvtLzcIn, cvtshiftcalc #(P) cvtshiftcalc(.ToInt, .CvtCe, .CvtResSubnormUf, .Xm, .CvtLzcIn,
.XZero, .IntToFp, .OutFmt, .CvtResUf, .CvtShiftIn); .XZero, .IntToFp, .OutFmt, .CvtResUf, .CvtShiftIn);
fmashiftcalc #(P) fmashiftcalc(.FmaSm, .FmaSCnt, .Fmt, .NormSumExp, .FmaSe, fmashiftcalc #(P) fmashiftcalc(.FmaSCnt, .Fmt, .NormSumExp, .FmaSe, .FmaSm,
.FmaSZero, .FmaPreResultSubnorm, .FmaShiftAmt, .FmaShiftIn); .FmaSZero, .FmaPreResultSubnorm, .FmaShiftAmt);
divshiftcalc #(P) divshiftcalc(.DivUe, .DivUm, .DivResSubnorm, .DivSubnormShiftPos, .DivShiftAmt, .DivShiftIn); divshiftcalc #(P) divshiftcalc(.DivUe, .DivResSubnorm, .DivSubnormShiftPos, .DivShiftAmt);
// select which unit's output to shift // select which unit's output to shift
always_comb always_comb
case(PostProcSel) case(PostProcSel)
2'b10: begin // fma 2'b10: begin // fma
ShiftAmt = {{P.LOGNORMSHIFTSZ-$clog2(P.FMALEN-1){1'b0}}, FmaShiftAmt}; ShiftAmt = {{P.LOGNORMSHIFTSZ-$clog2(P.FMALEN-1){1'b0}}, FmaShiftAmt};
ShiftIn = {FmaShiftIn, {P.NORMSHIFTSZ-(P.FMALEN+2){1'b0}}}; ShiftIn = {{2'b00, FmaSm}, {P.NORMSHIFTSZ-(P.FMALEN+2){1'b0}}};
end end
2'b00: begin // cvt 2'b00: begin // cvt
ShiftAmt = {{P.LOGNORMSHIFTSZ-$clog2(P.CVTLEN+1){1'b0}}, CvtShiftAmt}; ShiftAmt = {{P.LOGNORMSHIFTSZ-$clog2(P.CVTLEN+1){1'b0}}, CvtShiftAmt};
@ -163,7 +161,7 @@ module postprocess import cvw::*; #(parameter cvw_t P) (
end end
2'b01: begin //divsqrt 2'b01: begin //divsqrt
ShiftAmt = DivShiftAmt; ShiftAmt = DivShiftAmt;
ShiftIn = DivShiftIn; ShiftIn = {{P.NF{1'b0}}, DivUm, {P.NORMSHIFTSZ-P.DIVb-1-P.NF{1'b0}}};
end end
default: begin default: begin
ShiftAmt = {P.LOGNORMSHIFTSZ{1'bx}}; ShiftAmt = {P.LOGNORMSHIFTSZ{1'bx}};

2
src/ieu/bmu/bitmanipalu.sv
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@ -93,7 +93,7 @@ module bitmanipalu import cvw::*; #(parameter cvw_t P) (
// ZBC and ZBKCUnit // ZBC and ZBKCUnit
if (P.ZBC_SUPPORTED | P.ZBKC_SUPPORTED) begin: zbc if (P.ZBC_SUPPORTED | P.ZBKC_SUPPORTED) begin: zbc
zbc #(P.XLEN) ZBC(.A(ABMU), .RevA, .B(BBMU), .Funct3, .ZBCResult); zbc #(P) ZBC(.A(ABMU), .RevA, .B(BBMU), .Funct3, .ZBCResult);
end else assign ZBCResult = '0; end else assign ZBCResult = '0;
// ZBB Unit // ZBB Unit

32
src/ieu/bmu/zbc.sv
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@ -28,23 +28,31 @@
// and limitations under the License. // and limitations under the License.
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module zbc #(parameter WIDTH=32) ( module zbc import cvw::*; #(parameter cvw_t P) (
input logic [WIDTH-1:0] A, RevA, B, // Operands input logic [P.XLEN-1:0] A, RevA, B, // Operands
input logic [2:0] Funct3, // Indicates operation to perform input logic [2:0] Funct3, // Indicates operation to perform
output logic [WIDTH-1:0] ZBCResult); // ZBC result output logic [P.XLEN-1:0] ZBCResult); // ZBC result
logic [WIDTH-1:0] ClmulResult, RevClmulResult; logic [P.XLEN-1:0] ClmulResult, RevClmulResult;
logic [WIDTH-1:0] RevB; logic [P.XLEN-1:0] RevB;
logic [WIDTH-1:0] X, Y; logic [P.XLEN-1:0] X, Y;
bitreverse #(WIDTH) brB(B, RevB); bitreverse #(P.XLEN) brB(B, RevB);
mux3 #(WIDTH) xmux({RevA[WIDTH-2:0], {1'b0}}, RevA, A, ~Funct3[1:0], X); // choose X = A for clmul, Rev(A) << 1 for clmulh, Rev(A) for clmulr
mux2 #(WIDTH) ymux(RevB, B, ~Funct3[1], Y); // unshifted Rev(A) source is only needed for clmulr in ZBC, not in ZBKC
if (P.ZBC_SUPPORTED)
mux3 #(P.XLEN) xmux({RevA[P.XLEN-2:0], {1'b0}}, RevA, A, ~Funct3[1:0], X);
else
mux2 #(P.XLEN) xmux(A, {RevA[P.XLEN-2:0], {1'b0}}, Funct3[1], X);
clmul #(WIDTH) clm(.X, .Y, .ClmulResult); // choose X = B for clmul, Rev(B) for clmulH
mux2 #(P.XLEN) ymux(B, RevB, Funct3[1], Y);
bitreverse #(WIDTH) brClmulResult(ClmulResult, RevClmulResult); // carry free multiplier
clmul #(P.XLEN) clm(.X, .Y, .ClmulResult);
mux2 #(WIDTH) zbcresultmux(ClmulResult, RevClmulResult, Funct3[1], ZBCResult); // choose result = rev(X @ Y) for clmulh/clmulr
bitreverse #(P.XLEN) brClmulResult(ClmulResult, RevClmulResult);
mux2 #(P.XLEN) zbcresultmux(ClmulResult, RevClmulResult, Funct3[1], ZBCResult);
endmodule endmodule