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Started make allsynth to try many experiments

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This commit is contained in:
David Harris 2022-02-17 17:57:02 +00:00
parent eafd52e2bc
commit f3c7025ade
2 changed files with 33 additions and 4 deletions
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2
pipelined/src/ebu/ahblite.sv
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@ -111,7 +111,7 @@ module ahblite (
else if (IFUBusRead) NextBusState = INSTRREAD; else if (IFUBusRead) NextBusState = INSTRREAD;
else NextBusState = IDLE; else NextBusState = IDLE;
INSTRREAD: if (~HREADY) NextBusState = INSTRREAD; INSTRREAD: if (~HREADY) NextBusState = INSTRREAD;
else NextBusState = IDLE; // if (IFUBusRead still high) else NextBusState = IDLE; // if (IFUBusRead still high) *** need to wait?
default: NextBusState = IDLE; default: NextBusState = IDLE;
endcase endcase

35
synthDC/Makefile
View File

@ -21,10 +21,39 @@ hash := $(shell git rev-parse --short HEAD)
export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(hash) export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(hash)
export SAIFPOWER ?= 0 export SAIFPOWER ?= 0
CONFIGDIR ?= ~/riscv-wally/pipelined/config
#CONFIGS ?= $(shell find $(CONFIGDIR) -name "rv*")
CONFIGS ?= ("rv32e", "rv32ic")
print:
echo "files in $(CONFIGDIR) are $(CONFIGS)."
default: default:
@echo "Basic synthesis procedure for OSU/HMC/UNLV:" @echo "Basic synthesis procedure for Wally:"
@echo " adapt Makefile to your liking..." @echo " Invoke with make synth"
@echo
test: rv%
echo "Running test on $<"
rv%.log: rv%
echo $<
flavors:
rm -rf $(CONFIGDIR)/rv32em
cp -r $(CONFIGDIR)/rv32e $(CONFIGDIR)/rv32em
sed -i 's/h00000010/h00001010/' $(CONFIGDIR)/rv32em/wally-config.vh
# rv32e, 32ic, 32gc 64ic, 64gc
# 64gc - FPU
# PMP16
# PMP0
# No virtual memory
# Muldiv
allsynth:
make flavors
make synth DESIGN=wallypipelinedcore CONFIG=rv32e TECH=sky90 FREQ=500 MAXCORES=1
make synth DESIGN=wallypipelinedcore CONFIG=rv32em TECH=sky90 FREQ=500 MAXCORES=1
synth: synth:
@echo "DC Synthesis" @echo "DC Synthesis"