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Spacing cleanup
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@ -87,7 +87,7 @@ module alu import cvw::*; #(parameter cvw_t P) (
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endcase
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endcase
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// Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits
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// Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits
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if (P.XLEN == 64) assign PreALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
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if (P.XLEN == 64) assign PreALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
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else assign PreALUResult = FullResult;
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else assign PreALUResult = FullResult;
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// Bit manipulation muxing
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// Bit manipulation muxing
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