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adapt testbench linux to use reset_ext

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bbracker 2021-10-25 13:26:44 -07:00
parent f50787203f
commit f39a509b5b
2 changed files with 17 additions and 8 deletions
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3
wally-pipelined/regression/linux-wave.do
View File

@ -2,6 +2,7 @@ onerror {resume}
quietly WaveActivateNextPane {} 0 quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/clk add wave -noupdate /testbench/clk
add wave -noupdate /testbench/reset add wave -noupdate /testbench/reset
add wave -noupdate /testbench/reset_ext
add wave -noupdate -radix unsigned /testbench/InstrCountW add wave -noupdate -radix unsigned /testbench/InstrCountW
add wave -noupdate /testbench/dut/hart/SATP_REGW add wave -noupdate /testbench/dut/hart/SATP_REGW
add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
@ -509,7 +510,7 @@ add wave -noupdate /testbench/dut/uncore/dtim/memwrite
add wave -noupdate /testbench/dut/uncore/dtim/HWDATA add wave -noupdate /testbench/dut/uncore/dtim/HWDATA
add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 23} {209183247 ns} 0} {{Cursor 5} {197 ns} 0} WaveRestoreCursors {{Cursor 23} {209183247 ns} 0} {{Cursor 5} {229 ns} 0}
quietly wave cursor active 2 quietly wave cursor active 2
configure wave -namecolwidth 250 configure wave -namecolwidth 250
configure wave -valuecolwidth 314 configure wave -valuecolwidth 314

22
wally-pipelined/testbench/testbench-linux.sv
View File

@ -48,8 +48,8 @@ module testbench();
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
////////////////////////////////// HARDWARE /////////////////////////////////// ////////////////////////////////// HARDWARE ///////////////////////////////////
/////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////
logic clk, reset; logic clk, reset, reset_ext;
initial begin reset <= 1; # 22; reset <= 0; end initial begin reset_ext <= 1; # 22; reset_ext <= 0; end
always begin clk <= 1; # 5; clk <= 0; # 5; end always begin clk <= 1; # 5; clk <= 0; # 5; end
logic [`AHBW-1:0] HRDATAEXT; logic [`AHBW-1:0] HRDATAEXT;
@ -69,7 +69,7 @@ module testbench();
logic UARTSout; logic UARTSout;
assign GPIOPinsIn = 0; assign GPIOPinsIn = 0;
assign UARTSin = 1; assign UARTSin = 1;
wallypipelinedsoc dut(.clk, .reset, wallypipelinedsoc dut(.clk, .reset_ext, .reset,
.HRDATAEXT, .HREADYEXT, .HRESPEXT, .HCLK, .HRESETn, .HADDR, .HRDATAEXT, .HREADYEXT, .HRESPEXT, .HCLK, .HRESETn, .HADDR,
.HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK,
.GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
@ -219,7 +219,9 @@ module testbench();
initial begin \ initial begin \
if (CHECKPOINT!=0) begin \ if (CHECKPOINT!=0) begin \
force `SIGNAL = init``SIGNAL[ARRAY_MAX:ARRAY_MIN]; \ force `SIGNAL = init``SIGNAL[ARRAY_MAX:ARRAY_MIN]; \
#23; \ while (reset!==1) #1; \
while (reset!==0) #1; \
#1; \
release `SIGNAL; \ release `SIGNAL; \
end \ end \
end end
@ -232,7 +234,9 @@ module testbench();
initial begin \ initial begin \
if (CHECKPOINT!=0) begin \ if (CHECKPOINT!=0) begin \
force `SIGNAL_BASE[i].`SIGNAL = init``SIGNAL[i]; \ force `SIGNAL_BASE[i].`SIGNAL = init``SIGNAL[i]; \
#23; \ while (reset!==1) #1; \
while (reset!==0) #1; \
#1; \
release `SIGNAL_BASE[i].`SIGNAL; \ release `SIGNAL_BASE[i].`SIGNAL; \
end \ end \
end \ end \
@ -245,7 +249,9 @@ module testbench();
initial begin \ initial begin \
if (CHECKPOINT!=0) begin \ if (CHECKPOINT!=0) begin \
force `SIGNAL = init``SIGNAL[0]; \ force `SIGNAL = init``SIGNAL[0]; \
#23; \ while (reset!==1) #1; \
while (reset!==0) #1; \
#1; \
release `SIGNAL; \ release `SIGNAL; \
end \ end \
end end
@ -302,7 +308,9 @@ module testbench();
force {`STATUS_SIE,`STATUS_UIE} = initMSTATUS[0][1:0]; force {`STATUS_SIE,`STATUS_UIE} = initMSTATUS[0][1:0];
force `INSTRET = CHECKPOINT; force `INSTRET = CHECKPOINT;
force `CURR_PRIV = initPriv; force `CURR_PRIV = initPriv;
#23; while (reset!==1) #1;
while (reset!==0) #1;
#1;
release {`STATUS_TSR,`STATUS_TW,`STATUS_TVM,`STATUS_MXR,`STATUS_SUM,`STATUS_MPRV}; release {`STATUS_TSR,`STATUS_TW,`STATUS_TVM,`STATUS_MXR,`STATUS_SUM,`STATUS_MPRV};
release {`STATUS_FS,`STATUS_MPP}; release {`STATUS_FS,`STATUS_MPP};
release {`STATUS_SPP,`STATUS_MPIE}; release {`STATUS_SPP,`STATUS_MPIE};