diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index 1bdea74a7..eaedcd726 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -126,3 +126,4 @@ `define TESTSBP 0 `define REPLAY 0 +`define HPTW_WRITES_SUPPORTED 1 diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index 223aa3d80..2e8063e23 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -132,3 +132,4 @@ `define TESTSBP 1 `define REPLAY 0 +`define HPTW_WRITES_SUPPORTED 1 diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index 9102cf637..aadc41cbc 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -130,3 +130,4 @@ `define TESTSBP 0 `define REPLAY 0 +`define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index af6ef40cf..da45b57ba 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -128,3 +128,4 @@ `define TESTSBP 0 `define REPLAY 0 +`define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index 4d7b0418a..bddc02337 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -128,3 +128,4 @@ `define TESTSBP 0 `define REPLAY 0 +`define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64BP/wally-config.vh b/pipelined/config/rv64BP/wally-config.vh index f8ee8903b..dea046868 100644 --- a/pipelined/config/rv64BP/wally-config.vh +++ b/pipelined/config/rv64BP/wally-config.vh @@ -131,3 +131,4 @@ `define TESTSBP 1 `define REPLAY 0 +`define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index ea17620c3..a7dc78386 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -131,3 +131,4 @@ `define TESTSBP 0 `define REPLAY 0 +`define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/config/rv64ic/wally-config.vh b/pipelined/config/rv64ic/wally-config.vh index ec497db2a..927924721 100644 --- a/pipelined/config/rv64ic/wally-config.vh +++ b/pipelined/config/rv64ic/wally-config.vh @@ -131,3 +131,4 @@ `define TESTSBP 0 `define REPLAY 0 +`define HPTW_WRITES_SUPPORTED 0 diff --git a/pipelined/regression/buildrootBugFinder.py b/pipelined/regression/buildrootBugFinder.py index a20b7bf57..b6639e714 100755 --- a/pipelined/regression/buildrootBugFinder.py +++ b/pipelined/regression/buildrootBugFinder.py @@ -22,7 +22,7 @@ def main(): break checkpoint = checkpointList[0] logFile = logDir+"checkpoint"+str(checkpoint)+".log" - runCommand="{\nvsim -c < 1) begin:vict cachereplacementpolicy #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cachereplacementpolicy( - .clk, .reset, .HitWay(HitWayFinal), .VictimWay, .PAdr, .RAdr, .LRUWriteEn); + .clk, .reset, .HitWay(HitWayFinal), .VictimWay, .RAdr, .LRUWriteEn); end else assign VictimWay = 1'b1; // one hot. assign CacheHit = | HitWay; assign VictimDirty = | VictimDirtyWay; diff --git a/pipelined/src/cache/cachereplacementpolicy.sv b/pipelined/src/cache/cachereplacementpolicy.sv index 818a0abe1..80fc251c7 100644 --- a/pipelined/src/cache/cachereplacementpolicy.sv +++ b/pipelined/src/cache/cachereplacementpolicy.sv @@ -34,7 +34,6 @@ module cachereplacementpolicy input logic clk, reset, input logic [NUMWAYS-1:0] HitWay, output logic [NUMWAYS-1:0] VictimWay, - input logic [`PA_BITS-1:0] PAdr, input logic [SETLEN-1:0] RAdr, input logic LRUWriteEn); @@ -53,7 +52,6 @@ module cachereplacementpolicy // Pipeline Delay Registers flopr #(SETLEN) RAdrDelayReg(clk, reset, RAdr, RAdrD); - flopr #(SETLEN) PAdrDelayReg(clk, reset, PAdr[SETLEN+OFFSETLEN-1:OFFSETLEN], PAdrD); flopr #(1) LRUWriteEnDelayReg(clk, reset, LRUWriteEn, LRUWriteEnD); flopr #(NUMWAYS-1) NewReplacementDelayReg(clk, reset, NewReplacement, NewReplacementD); @@ -61,7 +59,7 @@ module cachereplacementpolicy // Needs to be resettable for simulation, but could omit reset for synthesis *** always_ff @(posedge clk) if (reset) for (int set = 0; set < NUMLINES; set++) ReplacementBits[set] = '0; - else if (LRUWriteEnD) ReplacementBits[PAdrD[SETLEN+OFFSETLEN-1:OFFSETLEN]] = NewReplacementD; + else if (LRUWriteEnD) ReplacementBits[RAdrD] = NewReplacementD; assign LineReplacementBits = ReplacementBits[RAdrD]; genvar index; diff --git a/pipelined/src/ebu/ahblite.sv b/pipelined/src/ebu/ahblite.sv index 9b82aff47..a68370cdb 100644 --- a/pipelined/src/ebu/ahblite.sv +++ b/pipelined/src/ebu/ahblite.sv @@ -111,7 +111,7 @@ module ahblite ( else if (IFUBusRead) NextBusState = INSTRREAD; else NextBusState = IDLE; INSTRREAD: if (~HREADY) NextBusState = INSTRREAD; - else NextBusState = IDLE; // if (IFUBusRead still high) + else NextBusState = IDLE; // if (IFUBusRead still high) *** need to wait? default: NextBusState = IDLE; endcase diff --git a/pipelined/src/ieu/regfile.sv b/pipelined/src/ieu/regfile.sv index 2dfb0626d..71ef621a7 100644 --- a/pipelined/src/ieu/regfile.sv +++ b/pipelined/src/ieu/regfile.sv @@ -49,6 +49,7 @@ module regfile ( // register 0 hardwired to 0 // reset is intended for simulation only, not synthesis + // can logic be adjusted to not need resettable registers? always_ff @(negedge clk) // or posedge reset) // *** make this a preload in testbench rather than reset if (reset) for(i=1; i