diff --git a/config/buildroot/config.vh b/config/buildroot/config.vh index d334ab373..2730a9706 100644 --- a/config/buildroot/config.vh +++ b/config/buildroot/config.vh @@ -130,6 +130,10 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF; // Bus Interface width localparam AHBW = 32'd64; +// AHB +localparam RAM_LATENCY = 32'b0; +localparam BURST_EN = 1; + // Test modes // Tie GPIO outputs back to inputs diff --git a/config/rv32e/config.vh b/config/rv32e/config.vh index 9abf11bf7..60153fdd2 100644 --- a/config/rv32e/config.vh +++ b/config/rv32e/config.vh @@ -133,7 +133,7 @@ localparam AHBW = 32'd32; // Test modes // AHB -localparam RAM_LATENCY = 0; +localparam RAM_LATENCY = 32'b0; localparam BURST_EN = 1; // Tie GPIO outputs back to inputs diff --git a/config/rv32gc/config.vh b/config/rv32gc/config.vh index 9a1ca7fea..eb021ab0e 100644 --- a/config/rv32gc/config.vh +++ b/config/rv32gc/config.vh @@ -134,7 +134,7 @@ localparam AHBW = 32'd32; // Test modes // AHB -localparam RAM_LATENCY = 0; +localparam RAM_LATENCY = 32'b0; localparam BURST_EN = 1; // Tie GPIO outputs back to inputs diff --git a/config/rv32i/config.vh b/config/rv32i/config.vh index a6ebe0985..fe2aa9e51 100644 --- a/config/rv32i/config.vh +++ b/config/rv32i/config.vh @@ -133,7 +133,7 @@ localparam AHBW = 32'd32; // Test modes // AHB -localparam RAM_LATENCY = 0; +localparam RAM_LATENCY = 32'b0; localparam BURST_EN = 1; // Tie GPIO outputs back to inputs diff --git a/config/rv32imc/config.vh b/config/rv32imc/config.vh index 5d8a3690b..3714f0749 100644 --- a/config/rv32imc/config.vh +++ b/config/rv32imc/config.vh @@ -132,7 +132,7 @@ localparam AHBW = 32'd32; // Test modes // AHB -localparam RAM_LATENCY = 0; +localparam RAM_LATENCY = 32'b0; localparam BURST_EN = 1; // Tie GPIO outputs back to inputs diff --git a/config/rv64fpquad/config.vh b/config/rv64fpquad/config.vh index 9a3416524..941e11382 100644 --- a/config/rv64fpquad/config.vh +++ b/config/rv64fpquad/config.vh @@ -135,7 +135,7 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF; // Test modes // AHB -localparam RAM_LATENCY = 0; +localparam RAM_LATENCY = 32'b0; localparam BURST_EN = 1; // Tie GPIO outputs back to inputs diff --git a/config/rv64gc/config.vh b/config/rv64gc/config.vh index fa397471b..c4e54e346 100644 --- a/config/rv64gc/config.vh +++ b/config/rv64gc/config.vh @@ -135,7 +135,7 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF; // Test modes // AHB -localparam RAM_LATENCY = 0; +localparam RAM_LATENCY = 32'b0; localparam BURST_EN = 1; // Tie GPIO outputs back to inputs diff --git a/config/rv64i/config.vh b/config/rv64i/config.vh index 9061da2a5..3067e9eab 100644 --- a/config/rv64i/config.vh +++ b/config/rv64i/config.vh @@ -135,7 +135,7 @@ localparam logic [63:0] SPI_RANGE = 64'h00000FFF; // Test modes // AHB -localparam RAM_LATENCY = 0; +localparam RAM_LATENCY = 32'b0; localparam BURST_EN = 1; // Tie GPIO outputs back to inputs diff --git a/config/shared/parameter-defs.vh b/config/shared/parameter-defs.vh index 7dc0a0bcf..bf4c11198 100644 --- a/config/shared/parameter-defs.vh +++ b/config/shared/parameter-defs.vh @@ -8,6 +8,8 @@ localparam cvw_t P = '{ IEEE754 : IEEE754, MISA : MISA, AHBW : AHBW, + RAM_LATENCY : RAM_LATENCY, + BURST_EN : BURST_EN, ZICSR_SUPPORTED : ZICSR_SUPPORTED, ZIFENCEI_SUPPORTED : ZIFENCEI_SUPPORTED, COUNTERS : COUNTERS, diff --git a/src/cvw.sv b/src/cvw.sv index a9ee9d093..c9d737d8f 100644 --- a/src/cvw.sv +++ b/src/cvw.sv @@ -41,6 +41,8 @@ typedef struct packed { logic IEEE754; // IEEE754 NaN handling (0 = use RISC-V NaN propagation instead) int MISA; // Machine Instruction Set Architecture int AHBW; // AHB bus width (usually = XLEN) + int RAM_LATENCY; // Latency to stress AHB + logic BURST_EN; // Support AHB Burst Mode // RISC-V Features logic ZICSR_SUPPORTED; diff --git a/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv index 89135966e..f033b40cc 100644 --- a/src/ebu/ahbcacheinterface.sv +++ b/src/ebu/ahbcacheinterface.sv @@ -28,10 +28,8 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module ahbcacheinterface #( - parameter AHBW, - parameter LLEN, - parameter PA_BITS, +module ahbcacheinterface import cvw::*; #( + parameter cvw_t P, parameter BEATSPERLINE, // Number of AHBW words (beats) in cacheline parameter AHBWLOGBWPL, // Log2 of ^ parameter LINELEN, // Number of bits in cacheline @@ -46,14 +44,14 @@ module ahbcacheinterface #( output logic [2:0] HSIZE, // AHB transaction width output logic [2:0] HBURST, // AHB burst length // bus interface buses - input logic [AHBW-1:0] HRDATA, // AHB read data - output logic [PA_BITS-1:0] HADDR, // AHB address - output logic [AHBW-1:0] HWDATA, // AHB write data - output logic [AHBW/8-1:0] HWSTRB, // AHB byte mask + input logic [P.AHBW-1:0] HRDATA, // AHB read data + output logic [P.PA_BITS-1:0] HADDR, // AHB address + output logic [P.AHBW-1:0] HWDATA, // AHB write data + output logic [P.AHBW/8-1:0] HWSTRB, // AHB byte mask // cache interface - input logic [PA_BITS-1:0] CacheBusAdr, // Address of cache line - input logic [LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback + input logic [P.PA_BITS-1:0] CacheBusAdr, // Address of cache line + input logic [P.LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$ input logic Cacheable, // Memory operation is cachable input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch @@ -63,8 +61,8 @@ module ahbcacheinterface #( output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr // uncached interface - input logic [PA_BITS-1:0] PAdr, // Physical address of uncached memory operation - input logic [LLEN-1:0] WriteDataM, // IEU write data for uncached store + input logic [P.PA_BITS-1:0] PAdr, // Physical address of uncached memory operation + input logic [P.LLEN-1:0] WriteDataM, // IEU write data for uncached store input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write input logic BusAtomic, // Uncache atomic memory operation input logic [2:0] Funct3, // Size of uncached memory operation @@ -78,12 +76,12 @@ module ahbcacheinterface #( localparam BeatCountThreshold = BEATSPERLINE - 1; // Largest beat index - logic [PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation + logic [P.PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA - logic [AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s - logic [AHBW-1:0] PreHWDATA; // AHB Address phase write data - logic [PA_BITS-1:0] PAdrZero; + logic [P.AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s + logic [P.AHBW-1:0] PreHWDATA; // AHB Address phase write data + logic [P.PA_BITS-1:0] PAdrZero; genvar index; @@ -91,38 +89,38 @@ module ahbcacheinterface #( for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer logic [BEATSPERLINE-1:0] CaptureBeat; assign CaptureBeat[index] = CaptureEn & (index == BeatCountDelayed); - flopen #(AHBW) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA), - .q(FetchBuffer[(index+1)*AHBW-1:index*AHBW])); + flopen #(P.AHBW) fb(.clk(HCLK), .en(CaptureBeat[index]), .d(HRDATA), + .q(FetchBuffer[(index+1)*P.AHBW-1:index*P.AHBW])); end - assign PAdrZero = BusCMOZero ? {PAdr[PA_BITS-1:$clog2(LINELEN/8)], {$clog2(LINELEN/8){1'b0}}} : PAdr; - mux2 #(PA_BITS) localadrmux(PAdrZero, CacheBusAdr, Cacheable, LocalHADDR); - assign HADDR = ({{PA_BITS-AHBWLOGBWPL{1'b0}}, BeatCount} << $clog2(AHBW/8)) + LocalHADDR; + assign PAdrZero = BusCMOZero ? {PAdr[P.PA_BITS-1:$clog2(LINELEN/8)], {$clog2(LINELEN/8){1'b0}}} : PAdr; + mux2 #(P.PA_BITS) localadrmux(PAdrZero, CacheBusAdr, Cacheable, LocalHADDR); + assign HADDR = ({{P.PA_BITS-AHBWLOGBWPL{1'b0}}, BeatCount} << $clog2(P.AHBW/8)) + LocalHADDR; - mux2 #(3) sizemux(.d0(Funct3), .d1(AHBW == 32 ? 3'b010 : 3'b011), .s(Cacheable | BusCMOZero), .y(HSIZE)); + mux2 #(3) sizemux(.d0(Funct3), .d1(P.AHBW == 32 ? 3'b010 : 3'b011), .s(Cacheable | BusCMOZero), .y(HSIZE)); // When AHBW is less than LLEN need extra muxes to select the subword from cache's read data. - logic [AHBW-1:0] CacheReadDataWordAHB; + logic [P.AHBW-1:0] CacheReadDataWordAHB; if(LLENPOVERAHBW > 1) begin - logic [AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0]; + logic [P.AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0]; genvar index; for (index = 0; index < LLENPOVERAHBW; index++) begin:readdatalinesetsmux - assign AHBWordSets[index] = CacheReadDataWordM[(index*AHBW)+AHBW-1: (index*AHBW)]; + assign AHBWordSets[index] = CacheReadDataWordM[(index*P.AHBW)+P.AHBW-1: (index*P.AHBW)]; end assign CacheReadDataWordAHB = AHBWordSets[BeatCount[$clog2(LLENPOVERAHBW)-1:0]]; - end else assign CacheReadDataWordAHB = CacheReadDataWordM[AHBW-1:0]; + end else assign CacheReadDataWordAHB = CacheReadDataWordM[P.AHBW-1:0]; - mux2 #(AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[AHBW-1:0]), + mux2 #(P.AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[P.AHBW-1:0]), .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA)); - flopen #(AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec + flopen #(P.AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec // *** bummer need a second byte mask for bus as it is AHBW rather than LLEN. // probably can merge by muxing PAdrM's LLEN/8-1 index bit based on HTRANS being != 0. - swbytemask #(AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(AHBW/8)-1:0]), .ByteMask(BusByteMaskM), .ByteMaskExtended()); + swbytemask #(P.AHBW) busswbytemask(.Size(HSIZE), .Adr(HADDR[$clog2(P.AHBW/8)-1:0]), .ByteMask(BusByteMaskM), .ByteMaskExtended()); - flopen #(AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[AHBW/8-1:0], HWSTRB); + flopen #(P.AHBW/8) HWSTRBReg(HCLK, HREADY, BusByteMaskM[P.AHBW/8-1:0], HWSTRB); - buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE) AHBBuscachefsm( + buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE, P.BURST_EN) AHBBuscachefsm( .HCLK, .HRESETn, .Flush, .BusRW, .BusAtomic, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat, .CacheBusRW, .BusCMOZero, .CacheBusAck, .BeatCount, .BeatCountDelayed, .HREADY, .HTRANS, .HWRITE, .HBURST); diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv index e9dadb515..75f444e4b 100644 --- a/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -28,13 +28,12 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`define BURST_EN 1 // Enables burst mode. Disable to show the lost performance. - // HCLK and clk must be the same clock! module buscachefsm #( parameter BeatCountThreshold, // Largest beat index parameter AHBWLOGBWPL, // Log2 of BEATSPERLINE - parameter READ_ONLY_CACHE + parameter READ_ONLY_CACHE, // 1 for read-only instruction cache + parameter BURST_EN // burst mode supported )( input logic HCLK, input logic HRESETn, @@ -142,11 +141,11 @@ module buscachefsm #( assign HTRANS = (CurrState == ADR_PHASE & HREADY & ((|BusRW) | (|CacheBusRW) | BusCMOZero) & ~Flush) | (CurrState == ATOMIC_READ_DATA_PHASE & BusAtomic) | (CacheAccess & FinalBeatCount & |CacheBusRW & HREADY & ~Flush) ? AHB_NONSEQ : // if we have a pipelined request - (CacheAccess & |BeatCount) ? (`BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE; + (CacheAccess & |BeatCount) ? (BURST_EN ? AHB_SEQ : AHB_NONSEQ) : AHB_IDLE; assign HWRITE = ((BusRW[0] & ~BusAtomic) | BusWrite & ~Flush) | (CurrState == ATOMIC_READ_DATA_PHASE & BusAtomic) | (CurrState == CACHE_WRITEBACK & |BeatCount); - assign HBURST = `BURST_EN & ((|CacheBusRW & ~Flush) | (CacheAccess & |BeatCount)) ? LocalBurstType : 3'b0; + assign HBURST = BURST_EN & ((|CacheBusRW & ~Flush) | (CacheAccess & |BeatCount)) ? LocalBurstType : 3'b0; always_comb begin case(BeatCountThreshold) diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv index d9a95fc3d..b91eb75b0 100644 --- a/src/ebu/ebu.sv +++ b/src/ebu/ebu.sv @@ -32,31 +32,31 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module ebu #(parameter XLEN, PA_BITS, AHBW)( +module ebu import cvw::*; #(parameter cvw_t P) ( input logic clk, reset, // Signals from IFU input logic [1:0] IFUHTRANS, // IFU AHB transaction request input logic [2:0] IFUHSIZE, // IFU AHB transaction size input logic [2:0] IFUHBURST, // IFU AHB burst length - input logic [PA_BITS-1:0] IFUHADDR, // IFU AHB address + input logic [P.PA_BITS-1:0] IFUHADDR, // IFU AHB address output logic IFUHREADY, // AHB peripheral ready gated by possible non-grant // Signals from LSU input logic [1:0] LSUHTRANS, // LSU AHB transaction request input logic LSUHWRITE, // LSU AHB transaction direction. 1: write, 0: read input logic [2:0] LSUHSIZE, // LSU AHB size input logic [2:0] LSUHBURST, // LSU AHB burst length - input logic [PA_BITS-1:0] LSUHADDR, // LSU AHB address - input logic [XLEN-1:0] LSUHWDATA, // initially support AHBW = XLEN - input logic [XLEN/8-1:0] LSUHWSTRB, // AHB byte mask + input logic [P.PA_BITS-1:0] LSUHADDR, // LSU AHB address + input logic [P.XLEN-1:0] LSUHWDATA, // initially support AHBW = XLEN + input logic [P.XLEN/8-1:0] LSUHWSTRB, // AHB byte mask output logic LSUHREADY, // AHB peripheral. Never gated as LSU always has priority // AHB-Lite external signals output logic HCLK, HRESETn, input logic HREADY, // AHB peripheral ready input logic HRESP, // AHB peripheral response. 0: OK 1: Error. Presently ignored. - output logic [PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration - output logic [AHBW-1:0] HWDATA, // AHB Write data after arbitration - output logic [XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration + output logic [P.PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration + output logic [P.AHBW-1:0] HWDATA, // AHB Write data after arbitration + output logic [P.XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration output logic HWRITE, // AHB transaction direction after arbitration output logic [2:0] HSIZE, // AHB transaction size after arbitration output logic [2:0] HBURST, // AHB burst length after arbitration @@ -72,13 +72,13 @@ module ebu #(parameter XLEN, PA_BITS, AHBW)( logic IFUDisable; logic IFUSelect; - logic [PA_BITS-1:0] IFUHADDROut; + logic [P.PA_BITS-1:0] IFUHADDROut; logic [1:0] IFUHTRANSOut; logic [2:0] IFUHBURSTOut; logic [2:0] IFUHSIZEOut; logic IFUHWRITEOut; - logic [PA_BITS-1:0] LSUHADDROut; + logic [P.PA_BITS-1:0] LSUHADDROut; logic [1:0] LSUHTRANSOut; logic [2:0] LSUHBURSTOut; logic [2:0] LSUHSIZEOut; @@ -97,14 +97,14 @@ module ebu #(parameter XLEN, PA_BITS, AHBW)( // input stages and muxing for IFU and LSU //////////////////////////////////////////////////////////////////////////////////////////////////// - controllerinput #(PA_BITS) IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable), + controllerinput #(P.PA_BITS) IFUInput(.HCLK, .HRESETn, .Save(IFUSave), .Restore(IFURestore), .Disable(IFUDisable), .Request(IFUReq), .HWRITEIn(1'b0), .HSIZEIn(IFUHSIZE), .HBURSTIn(IFUHBURST), .HTRANSIn(IFUHTRANS), .HADDRIn(IFUHADDR), .HWRITEOut(IFUHWRITEOut), .HSIZEOut(IFUHSIZEOut), .HBURSTOut(IFUHBURSTOut), .HREADYOut(IFUHREADY), .HTRANSOut(IFUHTRANSOut), .HADDROut(IFUHADDROut), .HREADYIn(HREADY)); // LSU always has priority so there should never be a need to save and restore the address phase inputs. - controllerinput #(PA_BITS, 0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable), + controllerinput #(P.PA_BITS, 0) LSUInput(.HCLK, .HRESETn, .Save(1'b0), .Restore(1'b0), .Disable(LSUDisable), .Request(LSUReq), .HWRITEIn(LSUHWRITE), .HSIZEIn(LSUHSIZE), .HBURSTIn(LSUHBURST), .HTRANSIn(LSUHTRANS), .HADDRIn(LSUHADDR), .HREADYOut(LSUHREADY), .HWRITEOut(LSUHWRITEOut), .HSIZEOut(LSUHSIZEOut), .HBURSTOut(LSUHBURSTOut), diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index be2595ea6..4848b5ebb 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -255,7 +255,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( .PAdr(PCPF), .CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM), .CMOpM('0)); - ahbcacheinterface #(P.AHBW, P.LLEN, P.PA_BITS, WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW, 1) + ahbcacheinterface #(P, WORDSPERLINE, LOGBWPL, LINELEN, LLENPOVERAHBW, 1) ahbcacheinterface(.HCLK(clk), .HRESETn(~reset), .HRDATA, .Flush(FlushD), .CacheBusRW, .BusCMOZero(1'b0), .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(), diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index ca4e14f53..c997d58ff 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -346,7 +346,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign DCacheStallM = CacheStall & ~IgnoreRequestTLB; assign CacheBusRW = CacheBusRWTemp; - ahbcacheinterface #(.AHBW(P.AHBW), .LLEN(P.LLEN), .PA_BITS(P.PA_BITS), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface( + ahbcacheinterface #(.P(P), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface( .HCLK(clk), .HRESETn(~reset), .Flush(FlushW | IgnoreRequestTLB), .HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY), diff --git a/src/uncore/ram_ahb.sv b/src/uncore/ram_ahb.sv index 0b15504c9..e14728513 100644 --- a/src/uncore/ram_ahb.sv +++ b/src/uncore/ram_ahb.sv @@ -27,8 +27,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`define RAM_LATENCY 0 - module ram_ahb import cvw::*; #(parameter cvw_t P, parameter BASE=0, RANGE = 65535, PRELOAD = 0) ( input logic HCLK, HRESETn, @@ -76,7 +74,7 @@ module ram_ahb import cvw::*; #(parameter cvw_t P, .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HREADRam)); // use this to add arbitrary latency to ram. Helps test AHB controller correctness - if(`RAM_LATENCY > 0) begin + if(P.RAM_LATENCY > 0) begin logic [7:0] NextCycle, Cycle; logic CntEn, CntRst; logic CycleFlag; @@ -101,7 +99,7 @@ module ram_ahb import cvw::*; #(parameter cvw_t P, endcase end - assign CycleFlag = Cycle == `RAM_LATENCY; + assign CycleFlag = Cycle == P.RAM_LATENCY; assign CntEn = NextState == DELAY; assign DelayReady = NextState == DELAY; assign CntRst = NextState == READY; diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index c0d08dd8c..ec0679f13 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -252,7 +252,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .LSUStallM); if(P.BUS_SUPPORTED) begin : ebu - ebu #(P.XLEN, P.PA_BITS, P.AHBW) ebu(// IFU connections + ebu #(P) ebu(// IFU connections .clk, .reset, // IFU interface .IFUHADDR, .IFUHBURST, .IFUHTRANS, .IFUHREADY, .IFUHSIZE,