diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv
index e917b6680..655714762 100644
--- a/wally-pipelined/src/ebu/ahblite.sv
+++ b/wally-pipelined/src/ebu/ahblite.sv
@@ -69,7 +69,7 @@ module ahblite (
 
   logic GrantData;
   logic [2:0] ISize;
-  logic [`AHBW-1:0] HRDATAMasked, ReadDataM;
+  logic [`AHBW-1:0] HRDATAMasked, ReadDataM, ReadDataPreW;
   logic IReady, DReady;
 //  logic [3:0] HSIZED; // size delayed by one cycle for reads
 //  logic [2:0] HADDRD; // address delayed for subword reads
@@ -114,6 +114,12 @@ module ahblite (
   assign #2 DataStall = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE) || (NextBusState == INSTRREADMEMPENDING);
   assign #1 InstrStall = (NextBusState == INSTRREAD);
  // assign InstrUpdate = (BusState == INSTRREADMEMPENDING) && (NextBusState != INSTRREADMEMPENDING);
+
+  // DH 2/20/22: A cyclic path presently exists
+  // HREADY->NextBusState->GrantData->HSIZE->HSELUART->HREADY
+  // This is because the peripherals assert HREADY on the same cycle
+  // When memory is working, also fix the peripherals to respond on the subsequent cycle
+  // and this path should be fixed.
       
   //  bus outputs
   assign #1 GrantData = (NextBusState == MEMREAD) || (NextBusState == MEMWRITE); 
@@ -131,6 +137,16 @@ module ahblite (
   flop #(4)   sizereg(HCLK, {UnsignedLoadM, HSIZE}, HSIZED);
   flop #(1)   writereg(HCLK, HWRITE, HWRITED);
 
+    // Route signals to Instruction and Data Caches
+  // *** assumes AHBW = XLEN
+  assign InstrRData = HRDATAMasked[31:0];
+//  assign ReadDataW = HRDATAMasked;
+  assign ReadDataM = HRDATAMasked; // changed from W to M dh 2/7/2021
+  assign CaptureDataM = (BusState == MEMREAD) && (NextBusState != MEMREAD);
+  flopenr #(`XLEN) ReadDataPreWReg(clk, reset, CaptureDataM, ReadDataM, ReadDataPreW); // *** this may break when there is no instruction read after data read
+  flopenr #(`XLEN) ReadDataWReg(clk, reset, ~StallW, ReadDataPreW, ReadDataW);
+
+
   /*
   typedef enum {IDLE, MEMREAD, MEMWRITE, INSTRREAD} statetype;
   statetype AdrState, DataState, NextAdrState; // what is happening in the first and second phases of the bus
@@ -209,13 +225,6 @@ module ahblite (
   assign HTRANS = InstrReadF | MemReadM | MemWriteM ? 2'b10 : 2'b00; // NONSEQ if reading or writing, IDLE otherwise
   assign HMASTLOCK = 0; // no locking supported
            */       
-  // Route signals to Instruction and Data Caches
-  // *** assumes AHBW = XLEN
-  assign InstrRData = HRDATAMasked[31:0];
-//  assign ReadDataW = HRDATAMasked;
-  assign ReadDataM = HRDATAMasked; // changed from W to M dh 2/7/2021
-  assign CaptureDataM = (BusState == MEMREAD) && (NextBusState != MEMREAD);
-  flopenr #(`XLEN) ReadDataWReg(clk, reset, CaptureDataM, ReadDataM, ReadDataW);
 
 
   // stalls
diff --git a/wally-pipelined/src/uncore/clint.sv b/wally-pipelined/src/uncore/clint.sv
index 00804a480..e3fc1ea04 100644
--- a/wally-pipelined/src/uncore/clint.sv
+++ b/wally-pipelined/src/uncore/clint.sv
@@ -54,6 +54,11 @@ module clint (
       assign #2 entry = {HADDR[15:2], 2'b00}; 
   endgenerate
   
+  // DH 2/20/21: Eventually allow MTIME to run off a separate clock
+  // This will require synchronizing MTIME to the system clock
+  // before it is read or compared to MTIMECMP.
+  // It will also require synchronizing the write to MTIMECMP.
+  // Use req and ack signals synchronized across the clock domains.
 
   // register access
   generate
diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv
index cad2d68d2..fd49fee0a 100644
--- a/wally-pipelined/testbench/testbench-imperas.sv
+++ b/wally-pipelined/testbench/testbench-imperas.sv
@@ -75,6 +75,7 @@ string tests64iNOc[] = {
                      "rv64i/I-MISALIGN_JMP-01","2000"
   };
  string tests64i[] = '{                 
+                     "rv64i/I-ECALL-01", "2000",
                      "rv64i/I-ENDIANESS-01", "2010",
                      "rv64i/I-ADD-01", "3000",
                      "rv64i/I-ADDI-01", "3000",
@@ -90,8 +91,8 @@ string tests64iNOc[] = {
                      "rv64i/I-BLTU-01", "4000",
                      "rv64i/I-BNE-01", "4000",
                      "rv64i/I-DELAY_SLOTS-01", "2000",
-                     "rv64i/I-EBREAK-01", "2000",
-                     "rv64i/I-ECALL-01", "2000",
+//                     "rv64i/I-EBREAK-01", "2000",
+//                     "rv64i/I-ECALL-01", "2000",
                      "rv64i/I-ENDIANESS-01", "2010",
                      "rv64i/I-IO-01", "2050",
                      "rv64i/I-JAL-01", "3000",
@@ -104,7 +105,7 @@ string tests64iNOc[] = {
                      "rv64i/I-LUI-01", "2000",
                      "rv64i/I-LW-01", "4110",
                      "rv64i/I-LWU-01", "4110", 
-                     "rv64i/I-MISALIGN_LDST-01", "2010",
+                     //"rv64i/I-MISALIGN_LDST-01", "2010",
                      "rv64i/I-NOP-01", "2000",
                      "rv64i/I-OR-01", "3000",
                      "rv64i/I-ORI-01", "3000",